From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=TKhtHH7U; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by groups.io with SMTP; Wed, 29 May 2019 05:50:30 -0700 Received: by mail-wm1-f66.google.com with SMTP id w9so1537402wmi.0 for ; Wed, 29 May 2019 05:50:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=un+YiSTYkJY1OmlxkkV89emYvGXHpR067q963XUNPEY=; b=TKhtHH7U1fZPRXw31ZnQ8OMfdRjT0d++es7IQ4KuPl0It+zGg0qiz9ZS6ks2cmyJG/ EXBEvh265swPbxZ5fXoEAl7SO05oj8nWDMou8tEs43oLb9dhJp+xkBg6eeyUhzvUnPHe 8Iu+ePpcWxokIeYwpklgfms8dDSeWaB5NO6z6jg4cXltvdaSTLTpUbjcCaw+YOXqXVvo vKYs5wX8xwWhvswTp44vkFqTRtprGRGYzirQsLna5Y/oBSTSsuWaaL2cGBwRMJgHC2S+ d1Jhjnad1KmtEIqrfxya0eFtjuGLz2hTrHbKGHvMGTofw78Ujs69tdN67QdO2KPMJ/CC cMbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=un+YiSTYkJY1OmlxkkV89emYvGXHpR067q963XUNPEY=; b=RIBC229l+IY7HjiMO2iGalF1NrOiUnMCR3lgnmFUKRuTAk8n4KKbeHwZ31DmUi6KNY pFTmlgzlbuwSK5Ch+5SP59Jn3qz86IhX1Cs4K940ygA0noYkuGShFqp4FZF6xhEgD0qN oCLQFRmIedQtCTBnbU3XP1NwMMiGF7dmCYF6Le3NHutMoDB3RSXdEApS7T11PdOnrQyT wQGkiXz8E4G0YWyRfSwHsE0pIuulW99qBATPd3X6k5E7usEBJMghkZIxziw5Gz9dP/kr Wyt/Zkt3l9hWv+fN9SxFHApZkqjoX/sIAqYXnpum+Ax8+fLT1Q0NCfv6cN/WpDei2rQh auTg== X-Gm-Message-State: APjAAAVx6Efd3ZD4tps/mpadeYJZRvuoml7JOwilkVj5ejkQh3rECuX6 ocZpYzwg/NgM+/e9IoBZNb1KPjmH3BkRxg== X-Google-Smtp-Source: APXvYqyT9R4yeZ3bX5OcYGO5bSyGG7z65eupQuAEZev4iyRaPPLrbe6bWevKzpDXJPDPF0EfJPCrVw== X-Received: by 2002:a1c:d10e:: with SMTP id i14mr7248113wmg.161.1559134228129; Wed, 29 May 2019 05:50:28 -0700 (PDT) Return-Path: Received: from sudo.home ([2a01:cb1d:112:6f00:c225:e9ff:fe2e:ea8]) by smtp.gmail.com with ESMTPSA id l18sm18112608wrv.38.2019.05.29.05.50.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 May 2019 05:50:27 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: add ACPI description of second SPI controller Date: Wed, 29 May 2019 14:50:18 +0200 Message-Id: <20190529125021.28308-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190529125021.28308-1-ard.biesheuvel@linaro.org> References: <20190529125021.28308-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The primary SPI controller on SynQuacer is reserved for the NOR flash, and is not exposed to the OS. The second SPI controller is wired to the low speed 96boards connector on DeveloperBox, and so in order to use it, we must describe it to the OS (like we already do in the device tree). So add the description to the DSDT as well. Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 19 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index c8d8120d262a..f6ff3988aa91 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -251,5 +251,24 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Device (PWRB) { Name (_HID, "PNP0C0C") } + + Device (SPI0) { + Name (_HID, "SCX0004") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_SPI1_BASE, SYNQUACER_SPI1_SIZE) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 192, 193, 194 } + }) + + Name (_DSD, Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "socionext,ihclk-rate", 125000000 }, + Package (2) { "socionext,use-rtm", 1 }, + Package (2) { "socionext,set-aces", 1 }, + } + }) + } } // Scope (_SB) } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index deb9c81e82e6..29c5f73f2057 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -78,4 +78,8 @@ #define SYNQUACER_UART1_BASE 0x51040000 #define SYNQUACER_UART1_SIZE SIZE_4KB +// SPI controller #1 +#define SYNQUACER_SPI1_BASE 0x54810000 +#define SYNQUACER_SPI1_SIZE SIZE_4KB + #endif -- 2.20.1