From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:23 -0700 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F215B30B96FC; Wed, 29 May 2019 15:12:22 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id AF2F54DA; Wed, 29 May 2019 15:12:16 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [PATCH for-edk2-stable201905 1/6] Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear" Date: Wed, 29 May 2019 17:12:04 +0200 Message-Id: <20190529151209.17503-2-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Wed, 29 May 2019 15:12:23 +0000 (UTC) Content-Transfer-Encoding: quoted-printable This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/Platform.h | 2 -- OvmfPkg/PlatformPei/MemDetect.c | 23 +++----------------- OvmfPkg/PlatformPei/Platform.c | 4 +++- 3 files changed, 6 insertions(+), 23 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platfor= m.h index 4476ddd871cd..81af8b71480f 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -114,6 +114,4 @@ extern UINT32 mMaxCpuCount; =20 extern UINT16 mHostBridgeDevId; =20 -extern UINT32 mQemuUc32Base; - #endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDet= ect.c index ae73c63d27d5..e890e36408a6 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -42,8 +42,6 @@ STATIC UINT32 mS3AcpiReservedMemorySize; =20 STATIC UINT16 mQ35TsegMbytes; =20 -UINT32 mQemuUc32Base; - VOID Q35TsegMbytesInitialization ( VOID @@ -665,8 +663,6 @@ QemuInitializeRam ( // cover it exactly. // if (IsMtrrSupported ()) { - UINT32 Uc32Size; - MtrrGetAllMtrrs (&MtrrSettings); =20 // @@ -693,24 +689,11 @@ QemuInitializeRam ( =20 // // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4= GB as - // uncacheable. Make sure one variable MTRR suffices by truncating t= he size - // to a whole power of two. This will round the base *up*, and a gap= (not - // used for either RAM or MMIO) may stay in the middle, marked as - // cacheable-by-default. + // uncacheable // - Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); - mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); - if (mQemuUc32Base !=3D LowerMemorySize) { - DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x= , for " - "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize, - mQemuUc32Base, Uc32Size)); - } - - Status =3D MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size, - CacheUncacheable); + Status =3D MtrrSetMemoryAttribute (LowerMemorySize, + SIZE_4GB - LowerMemorySize, CacheUncacheable); ASSERT_EFI_ERROR (Status); - } else { - mQemuUc32Base =3D (UINT32)LowerMemorySize; } } =20 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platfor= m.c index c064b4ed9b8f..fd8eccaf3e50 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -174,12 +174,14 @@ MemMapInitialization ( AddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 if (!mXen) { + UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; =20 + TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); PciExBarBase =3D 0; - PciBase =3D (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base; + PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The 32-bit PCI host aperture is expected to fall between the to= p of --=20 2.19.1.3.g30247aa5d201