From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:34 -0700 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C0D0230C62A8; Wed, 29 May 2019 15:12:28 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2A78A4DA; Wed, 29 May 2019 15:12:24 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [PATCH for-edk2-stable201905 2/6] Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35" Date: Wed, 29 May 2019 17:12:05 +0200 Message-Id: <20190529151209.17503-3-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Wed, 29 May 2019 15:12:28 +0000 (UTC) Content-Transfer-Encoding: quoted-printable This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkgIa32.dsc | 5 ++++- OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++++- OvmfPkg/OvmfPkgX64.dsc | 5 ++++- OvmfPkg/PlatformPei/Platform.c | 9 +++++---- 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index b3446ece311a..578fc6c98ec8 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -490,7 +490,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarch= y. It # is only consulted when OVMF runs on Q35. In that case it is programm= ed into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, = QEMU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 679d4eb8dd36..eade8f62d3de 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarch= y. It # is only consulted when OVMF runs on Q35. In that case it is programm= ed into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, = QEMU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 56a9560262aa..733a4c9d8a43 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarch= y. It # is only consulted when OVMF runs on Q35. In that case it is programm= ed into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, = QEMU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platfor= m.c index fd8eccaf3e50..9c013613a1a0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,13 +184,14 @@ MemMapInitialization ( PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // - // The 32-bit PCI host aperture is expected to fall between the to= p of - // low RAM and the base of the MMCONFIG area. + // The MMCONFIG area is expected to fall between the top of low RA= M and + // the base of the 32-bit PCI host aperture. // PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (PciBase < PciExBarBase); + ASSERT (TopOfLowRam <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciSize =3D (UINT32)(PciExBarBase - PciBase); + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + PciSize =3D 0xFC000000 - PciBase; } else { PciSize =3D 0xFC000000 - PciBase; } --=20 2.19.1.3.g30247aa5d201