* [PATCH 0/2] Support DynamicExPCD from FSP @ 2019-05-31 11:42 Chiu, Chasel 2019-05-31 11:42 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel 2019-05-31 11:42 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 0 siblings, 2 replies; 5+ messages in thread From: Chiu, Chasel @ 2019-05-31 11:42 UTC (permalink / raw) To: devel; +Cc: Michael A Kubacki, Sai Chaganty, Nate DeSimone FSP Dispatch mode can consume DynamicEx PCDs from boot loader side so boot loader must build those PCDs into PcdDatabase. 0001-KabylakeSiliconPkg: Support DynamicExPCD from FSP. 0002-KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Chasel, Chiu (2): KabylakeSiliconPkg: Support DynamicExPCD from FSP. KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. .../PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 8 ++++-- .../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- .../KabylakeRvp3/OpenBoardPkg.dsc | 17 ++++++++++++- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 25 ++++++++++++++----- .../PeiDxeSmmCpuPlatformLib.inf | 7 +----- .../KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 6 ++++- .../PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 5 ++-- .../Library/SiliconInitLib/SiliconInitLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 8 ++++-- .../PeiDxeSmmSaPlatformLib.inf | 7 +----- .../Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 +-- .../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 3 +-- 12 files changed, 61 insertions(+), 34 deletions(-) -- 2.19.1.windows.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. 2019-05-31 11:42 [PATCH 0/2] Support DynamicExPCD from FSP Chiu, Chasel @ 2019-05-31 11:42 ` Chiu, Chasel 2019-06-05 19:45 ` Nate DeSimone 2019-05-31 11:42 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 1 sibling, 1 reply; 5+ messages in thread From: Chiu, Chasel @ 2019-05-31 11:42 UTC (permalink / raw) To: devel; +Cc: Chasel, Chiu, Michael A Kubacki, Sai Chaganty, Nate DeSimone From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 FSP Dispatch mode can consume DynamicEx PCD from boot loader so it must include those PCD in PCD database for FSP to consume. PeiPostMemSiliconPolicyInitLib.inf (this is for FSP Dispatch mode) has all PCDs included to ensure they can be built into PCD database. Also cleaned up unused PciExpress related PCD from INFs. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 6 +++++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf | 3 +-- 9 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c index 51a06528e0..d99ee8e644 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c @@ -1,7 +1,7 @@ /** @file This file contains routines that get PCI Express Address -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -27,5 +27,9 @@ MmPciBase ( { ASSERT ((Bus <= 0xFF) && (Device <= 0x1F) && (Function <= 0x7)); - return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#ifdef FSP_FLAG + return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#else + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#endif } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf index 21d441a577..d2e813fea3 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for CPU Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,11 +34,6 @@ MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] CpuPlatformLibrary.h CpuPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc index 5b114ae99e..aa481d0307 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc @@ -47,7 +47,11 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000 +# +# This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild +# +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress [Defines] PLATFORM_NAME = KabylakeSiliconPkg diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf index 8ae40a0c9e..02495953a7 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiDxeSmmMmPciLib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,11 +31,12 @@ DebugLib [Packages] MdePkg/MdePkg.dec +KabylakeSiliconPkg/SiPkg.dec [Pcd] +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - [Sources] PeiDxeSmmMmPciLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf index 9007f299bb..132080e876 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf @@ -1,6 +1,6 @@ ### @file # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ SiliconInitPreMem.c [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec index a613079dd4..baee73038b 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -573,8 +573,12 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock |1843200|UINT32|0x00100003 ## PCI Express MMIO region length ## Valid settings: 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB ## -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0010004 - +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000|UINT32|0x0010004 +## +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress. +## This PCD is added for supporting different PCD type in different phases. +## +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xE0000000|UINT64|0x0010008 [PcdsFeatureFlag] ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf index 9fe71e5bac..5b034c2e9d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SA Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,11 +28,6 @@ IoLib MdePkg/MdePkg.dec KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] SaPlatformLibrary.h SaPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..2adfc28d6c 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,7 +35,6 @@ UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf index cc05f336b3..3c4c79affb 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SystemAgent Initialization driver # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -53,7 +53,6 @@ KabylakeSiliconPkg/KabylakeSiliconPrivate.dec [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId gSiPkgTokenSpaceGuid.PcdMchBaseAddress -- 2.19.1.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. 2019-05-31 11:42 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel @ 2019-06-05 19:45 ` Nate DeSimone 0 siblings, 0 replies; 5+ messages in thread From: Nate DeSimone @ 2019-06-05 19:45 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Chaganty, Rangasai V Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Friday, May 31, 2019 4:42 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 FSP Dispatch mode can consume DynamicEx PCD from boot loader so it must include those PCD in PCD database for FSP to consume. PeiPostMemSiliconPolicyInitLib.inf (this is for FSP Dispatch mode) has all PCDs included to ensure they can be built into PCD database. Also cleaned up unused PciExpress related PCD from INFs. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 6 +++++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf | 3 +-- 9 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c index 51a06528e0..d99ee8e644 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeS +++ mmMmPciLib.c @@ -1,7 +1,7 @@ /** @file This file contains routines that get PCI Express Address -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -27,5 +27,9 @@ MmPciBase ( { ASSERT ((Bus <= 0xFF) && (Device <= 0x1F) && (Function <= 0x7)); - return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#ifdef FSP_FLAG + return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus +<< 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); #else + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#endif } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf index 21d441a577..d2e813fea3 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformL +++ ib/PeiDxeSmmCpuPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for CPU Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,11 +34,6 @@ MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] CpuPlatformLibrary.h CpuPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc index 5b114ae99e..aa481d0307 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc @@ -47,7 +47,11 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000 +# +# This DSC mainly for GreenH Silicon code build so +PciExpressBaseAddress can be FixedAtBuild # +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui +d.PcdPciExpressBaseAddress [Defines] PLATFORM_NAME = KabylakeSiliconPkg diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf index 8ae40a0c9e..02495953a7 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeS +++ mmMmPciLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiDxeSmmMmPciLib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,11 +31,12 @@ DebugLib [Packages] MdePkg/MdePkg.dec +KabylakeSiliconPkg/SiPkg.dec [Pcd] +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - [Sources] PeiDxeSmmMmPciLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf index 9007f299bb..132080e876 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconIni +++ tLib.inf @@ -1,6 +1,6 @@ ### @file # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ SiliconInitPreMem.c [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec index a613079dd4..baee73038b 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -573,8 +573,12 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock |1843200|UINT32|0x00100003 ## PCI Express MMIO region length ## Valid settings: 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB ## -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0010004 - +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000|UINT32|0x00 +10004 +## +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress. +## This PCD is added for supporting different PCD type in different phases. +## +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress +|0xE0000000|UINT64|0x0010008 [PcdsFeatureFlag] ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf index 9fe71e5bac..5b034c2e9d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPl +++ atformLib/PeiDxeSmmSaPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SA Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,11 +28,6 @@ IoLib MdePkg/MdePkg.dec KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] SaPlatformLibrary.h SaPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..2adfc28d6c 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,7 +35,6 @@ UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf index cc05f336b3..3c4c79affb 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe. +++ inf @@ -1,7 +1,7 @@ ## @file # Component description file for SystemAgent Initialization driver # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -53,7 +53,6 @@ KabylakeSiliconPkg/KabylakeSiliconPrivate.dec [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId gSiPkgTokenSpaceGuid.PcdMchBaseAddress -- 2.19.1.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. 2019-05-31 11:42 [PATCH 0/2] Support DynamicExPCD from FSP Chiu, Chasel 2019-05-31 11:42 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel @ 2019-05-31 11:42 ` Chiu, Chasel 2019-06-05 19:45 ` Nate DeSimone 1 sibling, 1 reply; 5+ messages in thread From: Chiu, Chasel @ 2019-05-31 11:42 UTC (permalink / raw) To: devel; +Cc: Chasel, Chiu, Michael A Kubacki, Sai Chaganty, Nate DeSimone From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 Cleaned up unused PciExpress related PCD from INF and remove unnecessary DEFINE from DSC. Defines some PCDs as different types per API mode or Dispatch mode, also enlarge PeiMemory for Dispatch mode as both FSP and boot loader shares the same PeiMemory. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 17 ++++++++++++++++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 25 +++++++++++++++++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 9218c8fe67..8bc2f8729f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the ThunderBolt Smm module. # -# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..8dbdf25787 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,6 @@ DEFINE PLATFORM_PACKAGE = MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg DEFINE BOARD = KabylakeRvp3 DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) @@ -40,6 +39,22 @@ DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg !endif +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == TRUE +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform requirement. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength +!endif +!endif + ################################################################################ # # Defines Section - statements that will be processed to create a Makefile. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 63d0c4c2e6..fbd43a6947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -48,7 +48,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 @@ -147,6 +147,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild + # (They will be DynamicEx in FSP Dispatch mode) + # ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 @@ -155,10 +164,6 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 - ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -167,6 +172,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags @@ -294,4 +308,3 @@ gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 - -- 2.19.1.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. 2019-05-31 11:42 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel @ 2019-06-05 19:45 ` Nate DeSimone 0 siblings, 0 replies; 5+ messages in thread From: Nate DeSimone @ 2019-06-05 19:45 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Chaganty, Rangasai V Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Friday, May 31, 2019 4:42 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 Cleaned up unused PciExpress related PCD from INF and remove unnecessary DEFINE from DSC. Defines some PCDs as different types per API mode or Dispatch mode, also enlarge PeiMemory for Dispatch mode as both FSP and boot loader shares the same PeiMemory. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 17 ++++++++++++++++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 25 +++++++++++++++++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 9218c8fe67..8bc2f8729f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm +++ m.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the ThunderBolt Smm module. # -# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2018 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..8dbdf25787 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,6 @@ DEFINE PLATFORM_PACKAGE = MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg DEFINE BOARD = KabylakeRvp3 DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) @@ -40,6 +39,22 @@ DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg !endif +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == TRUE !if +gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform requirement. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress +|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp +aceGuid.PcdPciExpressRegionLength +!endif +!endif + ################################################################################ # # Defines Section - statements that will be processed to create a Makefile. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 63d0c4c2e6..fbd43a6947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d +++ sc @@ -48,7 +48,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 @@ -147,6 +147,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are +FixedAtBuild + # (They will be DynamicEx in FSP Dispatch mode) + # ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 @@ -155,10 +164,6 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 - ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -167,6 +172,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui +d.PcdPciExpressBaseAddress + +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp +aceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and +FSP sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags @@ -294,4 +308,3 @@ gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 - -- 2.19.1.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-06-05 19:45 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-05-31 11:42 [PATCH 0/2] Support DynamicExPCD from FSP Chiu, Chasel 2019-05-31 11:42 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel 2019-06-05 19:45 ` Nate DeSimone 2019-05-31 11:42 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 2019-06-05 19:45 ` Nate DeSimone
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