From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: devel@edk2.groups.io
Cc: "Chasel, Chiu" <chasel.chiu@intel.com>,
Michael A Kubacki <michael.a.kubacki@intel.com>,
Sai Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
Date: Tue, 4 Jun 2019 00:46:57 +0800 [thread overview]
Message-ID: <20190603164658.4668-2-chasel.chiu@intel.com> (raw)
In-Reply-To: <20190603164658.4668-1-chasel.chiu@intel.com>
From: "Chasel, Chiu" <chasel.chiu@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870
FSP in dispatch mode will produce DefaultPolicyInit
PPI for boot loader to consume and install policy
with default settings built-in by FSP.
Boot loader then may patch policy with per-board
settings and then install PolicyReady PPI to start
silicon initialization (policy consumer code)
Since different version FSP has different version
policy structure, the policy revision check code has
been extended to support newer revision policy and
the policy structure boot loader consuming has been
aligned with the same structure inside FSP.
(FSP will maintain policy structure backward
compatibility)
Also removed microcode location searching code from
silicon scope because silicon code should not access
hard-coded flash region unconditionally.
This should be done by platform/boot loader side.
Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 133 +++++++------------------------------------------------------------------------------------------------------------------------------
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++-----
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++----
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c | 32 +++++++++++++++++++++++++-------
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 39 +++++++++++++++++++++++++++------------
Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c | 6 +++---
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 4 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c | 14 +++++++-------
Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h | 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h | 4 +---
Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h | 32 ++++++++++++++++++++++++++++----
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 8 +++++---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h | 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf | 5 +++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 1 +
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h | 16 ++++++++++++++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 ++-
22 files changed, 384 insertions(+), 186 deletions(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
index cb7f379e0f..eb83cd4918 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
@@ -1,7 +1,7 @@
/** @file
This file is PeiCpuPolicy library.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/ConfigBlockLib.h>
#include <Library/PostCodeLib.h>
-#ifndef FSP_FLAG
-/**
- Get the next microcode patch pointer.
-
- @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
- and output points to the next patch address found.
-
- @retval EFI_SUCCESS - Patch found.
- @retval EFI_NOT_FOUND - Patch not found.
-**/
-EFI_STATUS
-EFIAPI
-RetrieveMicrocode (
- IN OUT CPU_MICROCODE_HEADER **MicrocodeData
- )
-{
- UINTN MicrocodeStart;
- UINTN MicrocodeEnd;
- UINTN TotalSize;
-
- if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
- return EFI_NOT_FOUND;
- }
-
- ///
- /// Microcode binary in SEC
- ///
- MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
- ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
- sizeof (EFI_FFS_FILE_HEADER);
-
- MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
-
- if (*MicrocodeData == NULL) {
- *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
- } else {
- if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
- DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
- return EFI_NOT_FOUND;
- }
-
- TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
- if (TotalSize == 0) {
- TotalSize = 2048;
- }
-
- *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
- if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
- DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
- return EFI_NOT_FOUND;
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Get the microcode patch pointer.
-
- @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
-**/
-EFI_PHYSICAL_ADDRESS
-PlatformCpuLocateMicrocodePatch (
- VOID
- )
-{
- EFI_STATUS Status;
- CPU_MICROCODE_HEADER *MicrocodeData;
- EFI_CPUID_REGISTER Cpuid;
- UINT32 UcodeRevision;
- UINTN MicrocodeBufferSize;
- VOID *MicrocodeBuffer = NULL;
-
- AsmCpuid (
- CPUID_VERSION_INFO,
- &Cpuid.RegEax,
- &Cpuid.RegEbx,
- &Cpuid.RegEcx,
- &Cpuid.RegEdx
- );
-
- UcodeRevision = GetCpuUcodeRevision ();
- MicrocodeData = NULL;
- while (TRUE) {
- ///
- /// Find the next patch address
- ///
- Status = RetrieveMicrocode (&MicrocodeData);
- DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
-
- if (Status != EFI_SUCCESS) {
- break;
- } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
- break;
- }
- }
-
- if (EFI_ERROR (Status)) {
- return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
- }
-
- ///
- /// Check that microcode patch size is <= 128K max size,
- /// then copy the patch from FV to temp buffer for faster access.
- ///
- MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
-
- if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
- MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
- if (MicrocodeBuffer != NULL) {
- DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
- CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
-
- return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
- } else {
- DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
- }
- } else {
- DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
- }
- return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
-}
-#endif
/**
Load Config block default
@@ -158,9 +36,12 @@ LoadCpuConfigDefault (
CpuConfig->AesEnable = CPU_FEATURE_ENABLE;
CpuConfig->EnableRsr = CPU_FEATURE_ENABLE;
CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 (PcdSmmbaseSwSmi);
-#ifndef FSP_FLAG
- CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
-#endif
+ //
+ // This function is shared by both non-FSP and FSP scenarios and always executed unconditionally.
+ // Since FSP/silicon code should not unconditionally access any hardcoding flash regions (that region might not be accessible
+ // in unknown platforms), the microcode location searching code should be moved to outside silicon code scope.
+ //
+ CpuConfig->MicrocodePatchAddress = 0;
}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
index 813b868fcf..c3a8bbf539 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
@@ -2,7 +2,7 @@
This file is PeiSiPolicyLib library creates default settings of RC
Policy and installs RC Policy PPI.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -196,8 +196,6 @@ DumpSiPolicy (
/**
SiInstallPolicyPpi installs SiPolicyPpi.
- While installed, RC assumes the Policy is ready and finalized. So please update and override
- any setting before calling this function.
@param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
@@ -226,11 +224,56 @@ SiInstallPolicyPpi (
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig);
ASSERT_EFI_ERROR (Status);
+ //
+ // Install Silicon Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc;
+ SI_POLICY_PPI *SiPolicy;
+
+ SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid;
+ SiPolicyPpiDesc->Ppi = NULL;
+
+ SiPolicy = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicy
+ );
+ ASSERT_EFI_ERROR(Status);
+
DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n"));
- DumpSiPolicy (SiPolicyPpi);
+ DumpSiPolicy (SiPolicy);
//
- // Install Silicon Policy PPI
+ // Install Silicon Policy Ready PPI
//
Status = PeiServicesInstallPpi (SiPolicyPpiDesc);
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
index e0d83cb467..e6506a0445 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
@@ -2,7 +2,7 @@
This file is PeiSiPolicyLib library creates default settings of RC
Policy and installs RC Policy PPI.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks (
/**
SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
- While installed, RC assumes the Policy is ready and finalized. So please update and override
- any setting before calling this function.
@param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance
@@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi (
SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi;
//
+ // Install Silicon Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc;
+ SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi;
+
+ SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid;
+ SiPolicyPreMemPpiDesc->Ppi = NULL;
+
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicyPreMemPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
// Print whole PCH_POLICY_PPI and serial out.
//
PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi);
@@ -114,7 +156,7 @@ SiPreMemInstallPolicyPpi (
CpuPreMemPrintPolicy (SiPolicyPreMemPpi);
//
- // Install Silicon Policy PPI
+ // Install PreMem Silicon Policy Ready PPI
//
Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
index 0de415ad19..6cbc39c29e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
@@ -1,7 +1,7 @@
/** @file
This file is SampleCode for Intel PEI Platform Policy initialization.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -35,19 +35,37 @@ SiliconPolicyInitPostMem (
IN OUT VOID *Policy
)
{
- EFI_STATUS Status;
- SI_POLICY_PPI *SiPolicyPpi;
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi;
DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n"));
ASSERT (Policy == NULL);
//
- // Call SiCreateConfigBlocks to initialize Silicon Policy structure
- // and get all Intel default policy settings.
+ // Locate Policy init PPI to install default silicon policy
//
- Status = SiCreateConfigBlocks (&SiPolicyPpi);
+ Status = PeiServicesLocatePpi (
+ &gSiDefaultPolicyInitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiSiDefaultPolicyInitPpi
+ );
ASSERT_EFI_ERROR (Status);
+ if (PeiSiDefaultPolicyInitPpi != NULL) {
+ Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit ();
+ ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_SUCCESS) {
+ Status = PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
return SiPolicyPpi;
}
@@ -78,7 +96,7 @@ SiliconPolicyDonePostMem (
// While installed, RC assumes the Policy is ready and finalized. So please
// update and override any setting before calling this function.
//
- Status = SiInstallPolicyPpi (SiPolicyPpi);
+ Status = SiInstallPolicyReadyPpi ();
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n"));
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
index fd76b4fac3..8e138b1eb2 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
@@ -1,7 +1,7 @@
/** @file
This file is SampleCode for Intel PEI Platform Policy initialization.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -35,20 +35,38 @@ SiliconPolicyInitPreMem (
IN OUT VOID *Policy
)
{
- EFI_STATUS Status;
- SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI *PeiPreMemSiDefaultPolicyInitPpi;
DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n"));
ASSERT (Policy == NULL);
+ SiPreMemPolicyPpi = NULL;
//
- // Call SiCreatePreMemConfigBlocks to initialize platform policy structure
- // and get all intel default policy settings.
+ // Locate Policy init PPI to install default silicon policy
//
- Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemDefaultPolicyInitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiPreMemSiDefaultPolicyInitPpi
+ );
ASSERT_EFI_ERROR (Status);
-
+ if (PeiPreMemSiDefaultPolicyInitPpi != NULL) {
+ Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();
+ ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_SUCCESS) {
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
return SiPreMemPolicyPpi;
}
@@ -69,16 +87,13 @@ SiliconPolicyDonePreMem (
)
{
EFI_STATUS Status;
- SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
-
- SiPreMemPolicyPpi = Policy;
//
- // Install SiPreMemPolicyPpi.
+ // Install Policy Ready PPI
// While installed, RC assumes the Policy is ready and finalized. So please
// update and override any setting before calling this function.
//
- Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
+ Status = SiPreMemInstallPolicyReadyPpi ();
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n"));
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
index 31c7d59d1d..803de0999e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
@@ -1,7 +1,7 @@
/** @file
This file is PeiMePolicy library.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -97,7 +97,7 @@ PrintMePeiPreMemConfig (
DEBUG_CODE_BEGIN ();
DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----------------\n"));
DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiPreMemConfig->Header.Revision));
- ASSERT (MePeiPreMemConfig->Header.Revision == ME_PEI_PREMEM_CONFIG_REVISION);
+ ASSERT (MePeiPreMemConfig->Header.Revision >= ME_PEI_PREMEM_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", MePeiPreMemConfig->HeciTimeouts));
DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", MePeiPreMemConfig->DidInitStat));
@@ -129,7 +129,7 @@ PrintMePeiConfig (
DEBUG_CODE_BEGIN ();
DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -----------------\n"));
DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig->Header.Revision));
- ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION);
+ ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig->EndOfPostMessage));
DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig->Heci3Enabled));
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
index 67fe214d0e..be36468b1e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
@@ -1,7 +1,7 @@
/** @file
This file provide services for DXE phase policy default initialization
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -38,7 +38,7 @@ SaPrintPolicyProtocol (
DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n"));
DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
- ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION);
+ ASSERT (SaPolicy->TableHeader.Header.Revision >= SA_POLICY_PROTOCOL_REVISION);
DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio));
DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n"));
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c
index 8b3a81a1c4..5c80fca88e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c
@@ -1,7 +1,7 @@
/** @file
This file provides service for PEI phase policy printing
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem (
DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n"));
DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision));
- ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION);
+ ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= SI_PREMEM_POLICY_REVISION);
DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG -----------------\n"));
DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision));
- ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION);
+ ASSERT (MiscPeiPreMemConfig->Header.Revision >= SA_MISC_PEI_PREMEM_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) {
DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index]));
@@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem (
DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n"));
DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header.GuidHob.Name));
DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Header.Revision));
- ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION);
+ ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength));
DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBufferSize));
DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSupport));
@@ -296,17 +296,17 @@ SaPrintPolicyPpi (
DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n"));
DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision));
- ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION);
+ ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= SI_POLICY_REVISION);
DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n"));
DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision));
- ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION);
+ ASSERT (GtConfig->Header.Revision >= GRAPHICS_PEI_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit));
DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr));
DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize));
DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr));
DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n"));
DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision));
- ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION);
+ ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION);
DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable));
DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut));
DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER));
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
index 2dc7be45d2..aa88e761b8 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
@@ -1,7 +1,7 @@
/** @file
This file declares various data structures used in CPU reference code.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define CPU_CAUSE_BY_ASSOCIATION 0x0100
#define CPU_CAUSE_UNSPECIFIED 0x8000
+#define MAX_MICROCODE_PATCH_SIZE 0x20000
+
typedef UINT32 CPU_STATE_CHANGE_CAUSE;
///
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
index d2a475591d..23321d6432 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
@@ -1,7 +1,7 @@
/** @file
Header file for the PeiCpuPolicyLib library.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Register/Cpuid.h>
#include <Library/PcdLib.h>
-#define MAX_MICROCODE_PATCH_SIZE 0x20000
-
#endif // _PEI_CPU_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
index 7bd26863b5..2c0387f678 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
@@ -1,7 +1,7 @@
/** @file
Prototype of the SiPolicyLib library.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -65,8 +65,6 @@ SiCreateConfigBlocks (
/**
SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
- While installed, RC assumes the Policy is ready and finalized. So please update and override
- any setting before calling this function.
@param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance
@@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi (
);
/**
- SiInstallPolicyPpi installs SiPolicyPpi.
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
While installed, RC assumes the Policy is ready and finalized. So please update and override
any setting before calling this function.
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
+ SiInstallPolicyPpi installs SiPolicyPpi.
+
@param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
@retval EFI_SUCCESS The policy is installed.
@@ -96,6 +106,20 @@ SiInstallPolicyPpi (
);
/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
Print out all silicon policy information.
@param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
new file mode 100644
index 0000000000..b8a526b9b7
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
@@ -0,0 +1,36 @@
+/** @file
+ This file defines the PPI function for installing PreMem silicon policy
+ PPI with default settings.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit;
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
new file mode 100644
index 0000000000..d620cf29d4
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
@@ -0,0 +1,36 @@
+/** @file
+ This file defines the PPI function for installing PostMem silicon policy
+ PPI with default settings.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit;
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
index 1d992cfbbd..47f58d16e9 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
@@ -1,7 +1,7 @@
## @file
# Component description file for the PeiSiPolicyLib library.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES
[Ppis]
-gSiPolicyPpiGuid ## PRODUCES
-gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyReadyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid ## PRODUCES
[Pcd]
gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
index c38294cfbe..f2fecee8c6 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
@@ -1,7 +1,7 @@
/** @file
Header file for the PolicyInitPei PEIM.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Ppi/PeiPreMemSiDefaultPolicyInit.h>
+#include <Ppi/PeiSiDefaultPolicyInit.h>
#include "PeiSiPolicyInit.h"
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
new file mode 100644
index 0000000000..83c909e681
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
@@ -0,0 +1,75 @@
+## @file
+# Library functions for Policy Initialization Library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPostMemSiliconPolicyInitLib
+ FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiPolicyInit.c
+ PeiPolicyInit.h
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ SiPolicyLib
+ DebugLib
+ PeiServicesLib
+
+[Ppis]
+ gSiDefaultPolicyInitPpiGuid ## CONSUMES
+
+[Pcd]
+ #
+ # Below PCD may not be consumed by this library but still adding them here
+ # to make sure all of them can be built into PcdDataBase.
+ # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type.
+ #
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
+ gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
+ gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate
+
+[Depex]
+ gSiDefaultPolicyInitPpiGuid
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf
similarity index 83%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf
index 7982a5d87f..782e04a476 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf
@@ -1,7 +1,7 @@
### @file
# Library functions for Policy Initialization Library.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -14,7 +14,7 @@
################################################################################
[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = PeiSiliconPolicyInitLib
+ BASE_NAME = PeiPreMemSiliconPolicyInitLib
FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69
MODULE_TYPE = BASE
VERSION_STRING = 1.0
@@ -34,7 +34,6 @@
[Sources]
PeiPolicyInitPreMem.c
- PeiPolicyInit.c
PeiPolicyInit.h
################################################################################
@@ -53,3 +52,9 @@
SiPolicyLib
DebugLib
PeiServicesLib
+
+[Ppis]
+ gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES
+
+[Depex]
+ gSiPreMemDefaultPolicyInitPpiGuid
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
index 9ffb84fa1e..c11680656d 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
@@ -1,7 +1,7 @@
### @file
# Library functions for Fsp Policy Initialization Library.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -72,6 +72,7 @@
MemoryAllocationLib
DebugPrintErrorLevelLib
FspWrapperApiLib
+ SiPolicyLib
[Pcd]
gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
@@ -84,7 +85,7 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
-
+
[Ppis]
gSiPolicyPpiGuid ## CONSUMES
gSiPreMemPolicyPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
index aebd3583bc..1ace9aeb52 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
@@ -72,6 +72,7 @@
MemoryAllocationLib
DebugPrintErrorLevelLib
FspWrapperApiLib
+ SiPolicyLib
[Pcd]
gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index a613079dd4..e9d3e5f918 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0x
##
gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}
gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
+gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}}
+gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
##
## SystemAgent
##
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h
index 4063f800e8..b835155c68 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h
@@ -1,7 +1,7 @@
/** @file
Policy definition for Internal Graphics Config Block (PostMem)
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
typedef struct {
CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+ UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ /**
+ Offset 28:3
+ CdClock Frequency select\n
+ 0 = 337.5 Mhz, 1 = 450 Mhz,\n
+ 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n
+ **/
+ UINT32 CdClock : 3;
UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
- UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future use
+ UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+ UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+ UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for future use
VOID* LogoPtr; ///< Offset 32 Address of Logo to be displayed in PEI
UINT32 LogoSize; ///< Offset 36 Logo Size
VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
index 8fae4cee61..c7454bd4a5 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
@@ -1,7 +1,7 @@
## @file
# Component description file for the PeiSaPolicy library.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -28,6 +28,7 @@ CpuMailboxLib
SiConfigBlockLib
RngLib
SmbusLib
+PchCycleDecodingLib
[Packages]
MdePkg/MdePkg.dec
--
2.13.3.windows.1
next prev parent reply other threads:[~2019-06-03 16:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-03 16:46 [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI Chiu, Chasel
2019-06-03 16:46 ` Chiu, Chasel [this message]
2019-06-06 9:43 ` [PATCH 1/2] KabylakeSiliconPkg: " Nate DeSimone
2019-06-11 2:11 ` [edk2-devel] " Ni, Ray
2019-06-11 5:13 ` Chiu, Chasel
2019-06-11 0:37 ` Chaganty, Rangasai V
2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel
2019-06-06 9:43 ` Nate DeSimone
2019-06-11 0:43 ` Chaganty, Rangasai V
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190603164658.4668-2-chasel.chiu@intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox