* [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI.
@ 2019-06-03 16:46 Chiu, Chasel
2019-06-03 16:46 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel
2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel
0 siblings, 2 replies; 9+ messages in thread
From: Chiu, Chasel @ 2019-06-03 16:46 UTC (permalink / raw)
To: devel; +Cc: Michael A Kubacki, Sai Chaganty, Nate DeSimone
FSP in dispatch mode will produce DefaultPolicyInit
PPI for boot loader to consume and install policy
with default settings built-in by FSP.
Boot loader then may patch policy with per-board
settings and then install PolicyReady PPI to start
silicon initialization (policy consumer code)
0001-KabylakeSiliconPkg: Add PPI definition and library
0002-KabylakeOpenBoardPkg: Link and add library instances
Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Chasel, Chiu (2):
KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI.
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 564 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 133 +++++++------------------------------------------------------------------------------------------------------------------------------
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++-----
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++----
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c | 32 +++++++++++++++++++++++++-------
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 39 +++++++++++++++++++++++++++------------
Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c | 6 +++---
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 4 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c | 14 +++++++-------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h | 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h | 4 +---
Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h | 32 ++++++++++++++++++++++++++++----
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 8 +++++---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h | 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf | 5 +++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 1 +
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h | 16 ++++++++++++++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 ++-
25 files changed, 1084 insertions(+), 186 deletions(-)
create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
rename Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} (83%)
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI Chiu, Chasel @ 2019-06-03 16:46 ` Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 0:37 ` Chaganty, Rangasai V 2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 1 sibling, 2 replies; 9+ messages in thread From: Chiu, Chasel @ 2019-06-03 16:46 UTC (permalink / raw) To: devel; +Cc: Chasel, Chiu, Michael A Kubacki, Sai Chaganty, Nate DeSimone From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to consume and install policy with default settings built-in by FSP. Boot loader then may patch policy with per-board settings and then install PolicyReady PPI to start silicon initialization (policy consumer code) Since different version FSP has different version policy structure, the policy revision check code has been extended to support newer revision policy and the policy structure boot loader consuming has been aligned with the same structure inside FSP. (FSP will maintain policy structure backward compatibility) Also removed microcode location searching code from silicon scope because silicon code should not access hard-coded flash region unconditionally. This should be done by platform/boot loader side. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 133 +++++++------------------------------------------------------------------------------------------------------------------------------ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c | 32 +++++++++++++++++++++++++------- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 39 +++++++++++++++++++++++++++------------ Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c | 6 +++--- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 4 ++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c | 14 +++++++------- Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h | 4 +--- Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h | 32 ++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 8 +++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 1 + Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 4 ++++ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h | 16 ++++++++++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 ++- 22 files changed, 384 insertions(+), 186 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c index cb7f379e0f..eb83cd4918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/ConfigBlockLib.h> #include <Library/PostCodeLib.h> -#ifndef FSP_FLAG -/** - Get the next microcode patch pointer. - - @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, - and output points to the next patch address found. - - @retval EFI_SUCCESS - Patch found. - @retval EFI_NOT_FOUND - Patch not found. -**/ -EFI_STATUS -EFIAPI -RetrieveMicrocode ( - IN OUT CPU_MICROCODE_HEADER **MicrocodeData - ) -{ - UINTN MicrocodeStart; - UINTN MicrocodeEnd; - UINTN TotalSize; - - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { - return EFI_NOT_FOUND; - } - - /// - /// Microcode binary in SEC - /// - MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + - sizeof (EFI_FFS_FILE_HEADER); - - MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); - - if (*MicrocodeData == NULL) { - *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; - } else { - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); - return EFI_NOT_FOUND; - } - - TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); - if (TotalSize == 0) { - TotalSize = 2048; - } - - *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); - if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); - return EFI_NOT_FOUND; - } - } - return EFI_SUCCESS; -} - -/** - Get the microcode patch pointer. - - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. -**/ -EFI_PHYSICAL_ADDRESS -PlatformCpuLocateMicrocodePatch ( - VOID - ) -{ - EFI_STATUS Status; - CPU_MICROCODE_HEADER *MicrocodeData; - EFI_CPUID_REGISTER Cpuid; - UINT32 UcodeRevision; - UINTN MicrocodeBufferSize; - VOID *MicrocodeBuffer = NULL; - - AsmCpuid ( - CPUID_VERSION_INFO, - &Cpuid.RegEax, - &Cpuid.RegEbx, - &Cpuid.RegEcx, - &Cpuid.RegEdx - ); - - UcodeRevision = GetCpuUcodeRevision (); - MicrocodeData = NULL; - while (TRUE) { - /// - /// Find the next patch address - /// - Status = RetrieveMicrocode (&MicrocodeData); - DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); - - if (Status != EFI_SUCCESS) { - break; - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { - break; - } - } - - if (EFI_ERROR (Status)) { - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; - } - - /// - /// Check that microcode patch size is <= 128K max size, - /// then copy the patch from FV to temp buffer for faster access. - /// - MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; - - if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { - MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); - if (MicrocodeBuffer != NULL) { - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); - - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; - } else { - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); - } - } else { - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n")); - } - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif /** Load Config block default @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( CpuConfig->AesEnable = CPU_FEATURE_ENABLE; CpuConfig->EnableRsr = CPU_FEATURE_ENABLE; CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 (PcdSmmbaseSwSmi); -#ifndef FSP_FLAG - CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch (); -#endif + // + // This function is shared by both non-FSP and FSP scenarios and always executed unconditionally. + // Since FSP/silicon code should not unconditionally access any hardcoding flash regions (that region might not be accessible + // in unknown platforms), the microcode location searching code should be moved to outside silicon code scope. + // + CpuConfig->MicrocodePatchAddress = 0; } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c index 813b868fcf..c3a8bbf539 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -196,8 +196,6 @@ DumpSiPolicy ( /** SiInstallPolicyPpi installs SiPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig); ASSERT_EFI_ERROR (Status); + // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; + SI_POLICY_PPI *SiPolicy; + + SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (SiPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid; + SiPolicyPpiDesc->Ppi = NULL; + + SiPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicy + ); + ASSERT_EFI_ERROR(Status); + DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); - DumpSiPolicy (SiPolicyPpi); + DumpSiPolicy (SiPolicy); // - // Install Silicon Policy PPI + // Install Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c index e0d83cb467..e6506a0445 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi; // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; + + SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (SiPolicyPreMemPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid; + SiPolicyPreMemPpiDesc->Ppi = NULL; + + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPreMemPpi + ); + ASSERT_EFI_ERROR (Status); + + // // Print whole PCH_POLICY_PPI and serial out. // PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ SiPreMemInstallPolicyPpi ( CpuPreMemPrintPolicy (SiPolicyPreMemPpi); // - // Install Silicon Policy PPI + // Install PreMem Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c index 0de415ad19..6cbc39c29e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n")); ASSERT (Policy == NULL); // - // Call SiCreateConfigBlocks to initialize Silicon Policy structure - // and get all Intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreateConfigBlocks (&SiPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); + if (PeiSiDefaultPolicyInitPpi != NULL) { + Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPolicyPpi; } @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiInstallPolicyPpi (SiPolicyPpi); + Status = SiInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c index fd76b4fac3..8e138b1eb2 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI *PeiPreMemSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); ASSERT (Policy == NULL); + SiPreMemPolicyPpi = NULL; // - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure - // and get all intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiPreMemDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); - + if (PeiPreMemSiDefaultPolicyInitPpi != NULL) { + Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPreMemPolicyPpi; } @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( ) { EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - SiPreMemPolicyPpi = Policy; // - // Install SiPreMemPolicyPpi. + // Install Policy Ready PPI // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + Status = SiPreMemInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c index 31c7d59d1d..803de0999e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiMePolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiPreMemConfig->Header.Revision)); - ASSERT (MePeiPreMemConfig->Header.Revision == ME_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MePeiPreMemConfig->Header.Revision >= ME_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", MePeiPreMemConfig->HeciTimeouts)); DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", MePeiPreMemConfig->DidInitStat)); @@ -129,7 +129,7 @@ PrintMePeiConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig->Header.Revision)); - ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION); + ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig->EndOfPostMessage)); DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig->Heci3Enabled)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c index 67fe214d0e..be36468b1e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file provide services for DXE phase policy default initialization -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision)); - ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION); + ASSERT (SaPolicy->TableHeader.Header.Revision >= SA_POLICY_PROTOCOL_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n")); DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio)); DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c index 8b3a81a1c4..5c80fca88e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c @@ -1,7 +1,7 @@ /** @file This file provides service for PEI phase policy printing -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION); + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= SI_PREMEM_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision)); - ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MiscPeiPreMemConfig->Header.Revision >= SA_MISC_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS)); for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) { DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index])); @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n")); DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Header.Revision)); - ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION); + ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength)); DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBufferSize)); DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSupport)); @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION); + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= SI_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); - ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION); + ASSERT (GtConfig->Header.Revision >= GRAPHICS_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit)); DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr)); DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); - ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION); + ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h index 2dc7be45d2..aa88e761b8 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -1,7 +1,7 @@ /** @file This file declares various data structures used in CPU reference code. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define CPU_CAUSE_BY_ASSOCIATION 0x0100 #define CPU_CAUSE_UNSPECIFIED 0x8000 +#define MAX_MICROCODE_PATCH_SIZE 0x20000 + typedef UINT32 CPU_STATE_CHANGE_CAUSE; /// diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h index d2a475591d..23321d6432 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h @@ -1,7 +1,7 @@ /** @file Header file for the PeiCpuPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Register/Cpuid.h> #include <Library/PcdLib.h> -#define MAX_MICROCODE_PATCH_SIZE 0x20000 - #endif // _PEI_CPU_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h index 7bd26863b5..2c0387f678 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -1,7 +1,7 @@ /** @file Prototype of the SiPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( ); /** - SiInstallPolicyPpi installs SiPolicyPpi. + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function. + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ); + +/** + SiInstallPolicyPpi installs SiPolicyPpi. + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @retval EFI_SUCCESS The policy is installed. @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( ); /** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ); + +/** Print out all silicon policy information. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h new file mode 100644 index 0000000000..b8a526b9b7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PreMem silicon policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_PREMEM_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy +/// +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; +}; + +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; + +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h new file mode 100644 index 0000000000..d620cf29d4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PostMem silicon policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy +/// +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { + PEI_POLICY_INIT PeiPolicyInit; +}; + +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; + +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf index 1d992cfbbd..47f58d16e9 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSiPolicyLib library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES [Ppis] -gSiPolicyPpiGuid ## PRODUCES -gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyReadyPpiGuid ## PRODUCES +gSiPolicyReadyPpiGuid ## PRODUCES [Pcd] gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h index c38294cfbe..f2fecee8c6 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h @@ -1,7 +1,7 @@ /** @file Header file for the PolicyInitPei PEIM. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <PiPei.h> #include <Library/DebugLib.h> #include <Library/MemoryAllocationLib.h> +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h> +#include <Ppi/PeiSiDefaultPolicyInit.h> #include "PeiSiPolicyInit.h" diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf new file mode 100644 index 0000000000..83c909e681 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf @@ -0,0 +1,75 @@ +## @file +# Library functions for Policy Initialization Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPostMemSiliconPolicyInitLib + FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiPolicyInit.c + PeiPolicyInit.h + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + SiPolicyLib + DebugLib + PeiServicesLib + +[Ppis] + gSiDefaultPolicyInitPpiGuid ## CONSUMES + +[Pcd] + # + # Below PCD may not be consumed by this library but still adding them here + # to make sure all of them can be built into PcdDataBase. + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type. + # + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate + +[Depex] + gSiDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf similarity index 83% rename from Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf index 7982a5d87f..782e04a476 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ ################################################################################ [Defines] INF_VERSION = 0x00010005 - BASE_NAME = PeiSiliconPolicyInitLib + BASE_NAME = PeiPreMemSiliconPolicyInitLib FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 MODULE_TYPE = BASE VERSION_STRING = 1.0 @@ -34,7 +34,6 @@ [Sources] PeiPolicyInitPreMem.c - PeiPolicyInit.c PeiPolicyInit.h ################################################################################ @@ -53,3 +52,9 @@ SiPolicyLib DebugLib PeiServicesLib + +[Ppis] + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES + +[Depex] + gSiPreMemDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf index 9ffb84fa1e..c11680656d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Fsp Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES @@ -84,7 +85,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES - + [Ppis] gSiPolicyPpiGuid ## CONSUMES gSiPreMemPolicyPpiGuid ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf index aebd3583bc..1ace9aeb52 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec index a613079dd4..e9d3e5f918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}} +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} +gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}} +gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} ## ## SystemAgent ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h index 4063f800e8..b835155c68 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h @@ -1,7 +1,7 @@ /** @file Policy definition for Internal Graphics Config Block (PostMem) -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ typedef struct { CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b> + UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + /** + Offset 28:3 + CdClock Frequency select\n + 0 = 337.5 Mhz, 1 = 450 Mhz,\n + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n + **/ + UINT32 CdClock : 3; UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable - UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future use + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable + UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b> + UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for future use VOID* LogoPtr; ///< Offset 32 Address of Logo to be displayed in PEI UINT32 LogoSize; ///< Offset 36 Logo Size VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..c7454bd4a5 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ CpuMailboxLib SiConfigBlockLib RngLib SmbusLib +PchCycleDecodingLib [Packages] MdePkg/MdePkg.dec -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel @ 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 2:11 ` [edk2-devel] " Ni, Ray 2019-06-11 0:37 ` Chaganty, Rangasai V 1 sibling, 1 reply; 9+ messages in thread From: Nate DeSimone @ 2019-06-06 9:43 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Chaganty, Rangasai V Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Monday, June 3, 2019 9:47 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to consume and install policy with default settings built-in by FSP. Boot loader then may patch policy with per-board settings and then install PolicyReady PPI to start silicon initialization (policy consumer code) Since different version FSP has different version policy structure, the policy revision check code has been extended to support newer revision policy and the policy structure boot loader consuming has been aligned with the same structure inside FSP. (FSP will maintain policy structure backward compatibility) Also removed microcode location searching code from silicon scope because silicon code should not access hard-coded flash region unconditionally. This should be done by platform/boot loader side. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 133 +++++++------------------------------------------------------------------------------------------------------------------------------ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c | 32 +++++++++++++++++++++++++------- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 39 +++++++++++++++++++++++++++------------ Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c | 6 +++--- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 4 ++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c | 14 +++++++------- Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h | 4 +--- Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h | 32 ++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 8 +++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 1 + Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 4 ++++ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h | 16 ++++++++++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 ++- 22 files changed, 384 insertions(+), 186 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c index cb7f379e0f..eb83cd4918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp +++ uPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/ConfigBlockLib.h> #include <Library/PostCodeLib.h> -#ifndef FSP_FLAG -/** - Get the next microcode patch pointer. - - @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, - and output points to the next patch address found. - - @retval EFI_SUCCESS - Patch found. - @retval EFI_NOT_FOUND - Patch not found. -**/ -EFI_STATUS -EFIAPI -RetrieveMicrocode ( - IN OUT CPU_MICROCODE_HEADER **MicrocodeData - ) -{ - UINTN MicrocodeStart; - UINTN MicrocodeEnd; - UINTN TotalSize; - - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { - return EFI_NOT_FOUND; - } - - /// - /// Microcode binary in SEC - /// - MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + - sizeof (EFI_FFS_FILE_HEADER); - - MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); - - if (*MicrocodeData == NULL) { - *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; - } else { - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); - return EFI_NOT_FOUND; - } - - TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); - if (TotalSize == 0) { - TotalSize = 2048; - } - - *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); - if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); - return EFI_NOT_FOUND; - } - } - return EFI_SUCCESS; -} - -/** - Get the microcode patch pointer. - - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. -**/ -EFI_PHYSICAL_ADDRESS -PlatformCpuLocateMicrocodePatch ( - VOID - ) -{ - EFI_STATUS Status; - CPU_MICROCODE_HEADER *MicrocodeData; - EFI_CPUID_REGISTER Cpuid; - UINT32 UcodeRevision; - UINTN MicrocodeBufferSize; - VOID *MicrocodeBuffer = NULL; - - AsmCpuid ( - CPUID_VERSION_INFO, - &Cpuid.RegEax, - &Cpuid.RegEbx, - &Cpuid.RegEcx, - &Cpuid.RegEdx - ); - - UcodeRevision = GetCpuUcodeRevision (); - MicrocodeData = NULL; - while (TRUE) { - /// - /// Find the next patch address - /// - Status = RetrieveMicrocode (&MicrocodeData); - DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); - - if (Status != EFI_SUCCESS) { - break; - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { - break; - } - } - - if (EFI_ERROR (Status)) { - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; - } - - /// - /// Check that microcode patch size is <= 128K max size, - /// then copy the patch from FV to temp buffer for faster access. - /// - MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; - - if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { - MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); - if (MicrocodeBuffer != NULL) { - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); - - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; - } else { - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); - } - } else { - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n")); - } - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif /** Load Config block default @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( CpuConfig->AesEnable = CPU_FEATURE_ENABLE; CpuConfig->EnableRsr = CPU_FEATURE_ENABLE; CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 (PcdSmmbaseSwSmi); -#ifndef FSP_FLAG - CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch (); -#endif + // + // This function is shared by both non-FSP and FSP scenarios and always executed unconditionally. + // Since FSP/silicon code should not unconditionally access any + hardcoding flash regions (that region might not be accessible // in unknown platforms), the microcode location searching code should be moved to outside silicon code scope. + // + CpuConfig->MicrocodePatchAddress = 0; } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c index 813b868fcf..c3a8bbf539 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLib.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -196,8 +196,6 @@ DumpSiPolicy ( /** SiInstallPolicyPpi installs SiPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig); ASSERT_EFI_ERROR (Status); + // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So +please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; + SI_POLICY_PPI *SiPolicy; + + SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof + (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid; + SiPolicyPpiDesc->Ppi = NULL; + + SiPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicy + ); + ASSERT_EFI_ERROR(Status); + DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); - DumpSiPolicy (SiPolicyPpi); + DumpSiPolicy (SiPolicy); // - // Install Silicon Policy PPI + // Install Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c index e0d83cb467..e6506a0445 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLibPreMem.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi; // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So +please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; + + SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPreMemPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid; + SiPolicyPreMemPpiDesc->Ppi = NULL; + + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPreMemPpi + ); + ASSERT_EFI_ERROR (Status); + + // // Print whole PCH_POLICY_PPI and serial out. // PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ SiPreMemInstallPolicyPpi ( CpuPreMemPrintPolicy (SiPolicyPreMemPpi); // - // Install Silicon Policy PPI + // Install PreMem Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c index 0de415ad19..6cbc39c29e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInit.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n")); ASSERT (Policy == NULL); // - // Call SiCreateConfigBlocks to initialize Silicon Policy structure - // and get all Intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreateConfigBlocks (&SiPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); + if (PeiSiDefaultPolicyInitPpi != NULL) { + Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPolicyPpi; } @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiInstallPolicyPpi (SiPolicyPpi); + Status = SiInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c index fd76b4fac3..8e138b1eb2 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInitPreMem.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI + *PeiPreMemSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); ASSERT (Policy == NULL); + SiPreMemPolicyPpi = NULL; // - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure - // and get all intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiPreMemDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); - + if (PeiPreMemSiDefaultPolicyInitPpi != NULL) { + Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPreMemPolicyPpi; } @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( ) { EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - SiPreMemPolicyPpi = Policy; // - // Install SiPreMemPolicyPpi. + // Install Policy Ready PPI // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + Status = SiPreMemInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c index 31c7d59d1d..803de0999e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePo +++ licyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiMePolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiPreMemConfig->Header.Revision)); - ASSERT (MePeiPreMemConfig->Header.Revision == ME_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MePeiPreMemConfig->Header.Revision >= + ME_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", MePeiPreMemConfig->HeciTimeouts)); DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", MePeiPreMemConfig->DidInitStat)); @@ -129,7 +129,7 @@ PrintMePeiConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig->Header.Revision)); - ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION); + ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig->EndOfPostMessage)); DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig->Heci3Enabled)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c index 67fe214d0e..be36468b1e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLi +++ b/DxeSaPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file provide services for DXE phase policy default initialization -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision)); - ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION); + ASSERT (SaPolicy->TableHeader.Header.Revision >= + SA_POLICY_PROTOCOL_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n")); DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio)); DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c index 8b3a81a1c4..5c80fca88e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/SaPrintPolicy.c @@ -1,7 +1,7 @@ /** @file This file provides service for PEI phase policy printing -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION); + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= + SI_PREMEM_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision)); - ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MiscPeiPreMemConfig->Header.Revision >= + SA_MISC_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS)); for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) { DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index])); @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n")); DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Header.Revision)); - ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION); + ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength)); DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBufferSize)); DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSupport)); @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION); + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= + SI_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); - ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION); + ASSERT (GtConfig->Header.Revision >= GRAPHICS_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit)); DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr)); DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); - ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION); + ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h index 2dc7be45d2..aa88e761b8 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -1,7 +1,7 @@ /** @file This file declares various data structures used in CPU reference code. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define CPU_CAUSE_BY_ASSOCIATION 0x0100 #define CPU_CAUSE_UNSPECIFIED 0x8000 +#define MAX_MICROCODE_PATCH_SIZE 0x20000 + typedef UINT32 CPU_STATE_CHANGE_CAUSE; /// diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h index d2a475591d..23321d6432 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp +++ uPolicyLibrary.h @@ -1,7 +1,7 @@ /** @file Header file for the PeiCpuPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Register/Cpuid.h> #include <Library/PcdLib.h> -#define MAX_MICROCODE_PATCH_SIZE 0x20000 - #endif // _PEI_CPU_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h index 7bd26863b5..2c0387f678 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -1,7 +1,7 @@ /** @file Prototype of the SiPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( ); /** - SiInstallPolicyPpi installs SiPolicyPpi. + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function. + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ); + +/** + SiInstallPolicyPpi installs SiPolicyPpi. + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @retval EFI_SUCCESS The policy is installed. @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( ); /** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So + please update and override any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ); + +/** Print out all silicon policy information. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h new file mode 100644 index 0000000000..b8a526b9b7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPol +++ icyInit.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PreMem silicon +policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI **/ typedef +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy /// +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; +}; + +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; + +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h new file mode 100644 index 0000000000..d620cf29d4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyIni +++ t.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PostMem silicon +policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI +PEI_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI **/ typedef +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy /// +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { + PEI_POLICY_INIT PeiPolicyInit; +}; + +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; + +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf index 1d992cfbbd..47f58d16e9 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSiPolicyLib library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES [Ppis] -gSiPolicyPpiGuid ## PRODUCES -gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyReadyPpiGuid ## PRODUCES +gSiPolicyReadyPpiGuid ## PRODUCES [Pcd] gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h index c38294cfbe..f2fecee8c6 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInit.h @@ -1,7 +1,7 @@ /** @file Header file for the PolicyInitPei PEIM. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <PiPei.h> #include <Library/DebugLib.h> #include <Library/MemoryAllocationLib.h> +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h> +#include <Ppi/PeiSiDefaultPolicyInit.h> #include "PeiSiPolicyInit.h" diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf new file mode 100644 index 0000000000..83c909e681 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPostMemSiliconPolicyInitLib.inf @@ -0,0 +1,75 @@ +## @file +# Library functions for Policy Initialization Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +####################################################################### +######### +# +# Defines Section - statements that will be processed to create a Makefile. +# +####################################################################### +######### +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPostMemSiliconPolicyInitLib + FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +####################################################################### +######### +# +# Sources Section - list of files that are required for the build to succeed. +# +####################################################################### +######### + +[Sources] + PeiPolicyInit.c + PeiPolicyInit.h + +####################################################################### +######### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +####################################################################### +######### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + SiPolicyLib + DebugLib + PeiServicesLib + +[Ppis] + gSiDefaultPolicyInitPpiGuid ## CONSUMES + +[Pcd] + # + # Below PCD may not be consumed by this library but still adding them +here + # to make sure all of them can be built into PcdDataBase. + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type. + # + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate + +[Depex] + gSiDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf similarity index 83% rename from Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf index 7982a5d87f..782e04a476 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPreMemSiliconPolicyInitLib.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ ################################################################################ [Defines] INF_VERSION = 0x00010005 - BASE_NAME = PeiSiliconPolicyInitLib + BASE_NAME = PeiPreMemSiliconPolicyInitLib FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 MODULE_TYPE = BASE VERSION_STRING = 1.0 @@ -34,7 +34,6 @@ [Sources] PeiPolicyInitPreMem.c - PeiPolicyInit.c PeiPolicyInit.h ################################################################################ @@ -53,3 +52,9 @@ SiPolicyLib DebugLib PeiServicesLib + +[Ppis] + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES + +[Depex] + gSiPreMemDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf index 9ffb84fa1e..c11680656d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs +++ p/PeiSiliconPolicyInitLibFsp.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Fsp Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES @@ -84,7 +85,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES - + [Ppis] gSiPolicyPpiGuid ## CONSUMES gSiPreMemPolicyPpiGuid ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf index aebd3583bc..1ace9aeb52 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs +++ p/PeiSiliconPolicyInitLibFspAml.inf @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec index a613079dd4..e9d3e5f918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}} +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGuid += {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} ## ## SystemAgent ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h index 4063f800e8..b835155c68 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/G +++ raphicsPeiConfig.h @@ -1,7 +1,7 @@ /** @file Policy definition for Internal Graphics Config Block (PostMem) -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ typedef struct { CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b> + UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + /** + Offset 28:3 + CdClock Frequency select\n + 0 = 337.5 Mhz, 1 = 450 Mhz,\n + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n + **/ + UINT32 CdClock : 3; UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable - UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future use + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable + UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b> + UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for future use VOID* LogoPtr; ///< Offset 32 Address of Logo to be displayed in PEI UINT32 LogoSize; ///< Offset 36 Logo Size VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..c7454bd4a5 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ CpuMailboxLib SiConfigBlockLib RngLib SmbusLib +PchCycleDecodingLib [Packages] MdePkg/MdePkg.dec -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. 2019-06-06 9:43 ` Nate DeSimone @ 2019-06-11 2:11 ` Ni, Ray 2019-06-11 5:13 ` Chiu, Chasel 0 siblings, 1 reply; 9+ messages in thread From: Ni, Ray @ 2019-06-11 2:11 UTC (permalink / raw) To: devel@edk2.groups.io, Desimone, Nathaniel L, Chiu, Chasel Cc: Kubacki, Michael A, Chaganty, Rangasai V Chasel, Where is the code that produces DefaultPolicyInit PPI? Is the code public available? And in general, I think the patch consists of several changes: 1. change version compare from "==" to ">=" to support FSP be used in newer board. 2. Add definition of SiDefaultPolicyPpi 3. Update non-FSP version of PeiSiliconPolicyInitLib to consume the SiDefaultPolicyPpi 4. Update config block for GFX 5. Add SiXXXInstallPolicyReadyPpi 6. maybe more.... Can you please try to separate the changes to small patches? Regarding to the changes in KabylakeSiliconPkg\Library\PeiSiPolicyLib\PeiSiPolicyLibPreMem.c: There are two APIs: SiPreMemInstallPolicyPpi and SiPreMemInstallPolicyReadyPpi. When FSP runs in API mode, the calling flow is as below: FspWrapperPeim::PeiMemoryDiscoveredNotify --> MinPlatformPkg/../PeiFspWrapperPlatformLib::UpdateFspsUpdData --> KabylakeSiliconPkg/.../SiliconPolicyInitPostMem --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiCreateConfigBlocks --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiInstallPolicyPpi Do you think that it's possible to update KabylakeSiliconPkg/.../SiliconPolicyInitPostMem() to call SiDefaultPolicyInitPpi->PeiPolicyInit()? To align the behavior when FSP runs in dispatch mode. Thanks, Ray > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate > DeSimone > Sent: Thursday, June 6, 2019 5:44 PM > To: Chiu, Chasel <chasel.chiu@intel.com>; devel@edk2.groups.io > Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V > <rangasai.v.chaganty@intel.com> > Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > DefaultPolicyInit PPI. > > Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > > -----Original Message----- > From: Chiu, Chasel > Sent: Monday, June 3, 2019 9:47 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A > <michael.a.kubacki@intel.com>; Chaganty, Rangasai V > <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com> > Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. > > From: "Chasel, Chiu" <chasel.chiu@intel.com> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 > > FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to > consume and install policy with default settings built-in by FSP. > Boot loader then may patch policy with per-board settings and then install > PolicyReady PPI to start silicon initialization (policy consumer code) > > Since different version FSP has different version policy structure, the policy > revision check code has been extended to support newer revision policy and > the policy structure boot loader consuming has been aligned with the same > structure inside FSP. > (FSP will maintain policy structure backward > compatibility) > > Also removed microcode location searching code from silicon scope because > silicon code should not access hard-coded flash region unconditionally. > This should be done by platform/boot loader side. > > Cc: Michael A Kubacki <michael.a.kubacki@intel.com> > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> > --- > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLi > b.c | 133 +++++++---------------------------------------- > -------------------------------------------------------------------------------------- > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem > .c | 50 > ++++++++++++++++++++++++++++++++++++++++++++++---- > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c > | 32 +++++++++++++++++++++++++------- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPr > eMem.c | 39 +++++++++++++++++++++++++++------- > ----- > > Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib. > c | 6 +++--- > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSa > PolicyLib.c | 4 ++-- > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrint > Policy.c | 14 +++++++------- > Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > | 4 +++- > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLi > brary.h | 4 +--- > Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > | 32 ++++++++++++++++++++++++++++---- > > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h > | 36 ++++++++++++++++++++++++++++++++++++ > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > | 36 ++++++++++++++++++++++++++++++++++++ > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > | 8 +++++--- > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h > | 4 +++- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSi > liconPolicyInitLib.inf | 75 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPoli > cyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconP > olicyInitLibFsp.inf | 5 +++-- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconP > olicyInitLibFspAml.inf | 1 + > Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > | 4 ++++ > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphics > PeiConfig.h | 16 ++++++++++++++-- > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaP > olicyLib.inf | 3 ++- > 22 files changed, 384 insertions(+), 186 deletions(-) > > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Lib.c > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Lib.c > index cb7f379e0f..eb83cd4918 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Lib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp > +++ uPolicyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file is PeiCpuPolicy library. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include <Library/ConfigBlockLib.h> #include <Library/PostCodeLib.h> > > -#ifndef FSP_FLAG > -/** > - Get the next microcode patch pointer. > - > - @param[in, out] MicrocodeData - Input is a pointer to the last microcode > patch address found, > - and output points to the next patch address found. > - > - @retval EFI_SUCCESS - Patch found. > - @retval EFI_NOT_FOUND - Patch not found. > -**/ > -EFI_STATUS > -EFIAPI > -RetrieveMicrocode ( > - IN OUT CPU_MICROCODE_HEADER **MicrocodeData > - ) > -{ > - UINTN MicrocodeStart; > - UINTN MicrocodeEnd; > - UINTN TotalSize; > - > - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 > (PcdFlashMicrocodeFvSize) == 0)) { > - return EFI_NOT_FOUND; > - } > - > - /// > - /// Microcode binary in SEC > - /// > - MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 > (PcdFlashMicrocodeFvBase))->HeaderLength + > - sizeof (EFI_FFS_FILE_HEADER); > - > - MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); > - > - if (*MicrocodeData == NULL) { > - *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) > MicrocodeStart; > - } else { > - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) > MicrocodeStart) { > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart > \n")); > - return EFI_NOT_FOUND; > - } > - > - TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); > - if (TotalSize == 0) { > - TotalSize = 2048; > - } > - > - *MicrocodeData = (CPU_MICROCODE_HEADER *) > ((UINTN)*MicrocodeData + TotalSize); > - if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) > (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd > \n")); > - return EFI_NOT_FOUND; > - } > - } > - return EFI_SUCCESS; > -} > - > -/** > - Get the microcode patch pointer. > - > - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL > if not found. > -**/ > -EFI_PHYSICAL_ADDRESS > -PlatformCpuLocateMicrocodePatch ( > - VOID > - ) > -{ > - EFI_STATUS Status; > - CPU_MICROCODE_HEADER *MicrocodeData; > - EFI_CPUID_REGISTER Cpuid; > - UINT32 UcodeRevision; > - UINTN MicrocodeBufferSize; > - VOID *MicrocodeBuffer = NULL; > - > - AsmCpuid ( > - CPUID_VERSION_INFO, > - &Cpuid.RegEax, > - &Cpuid.RegEbx, > - &Cpuid.RegEcx, > - &Cpuid.RegEdx > - ); > - > - UcodeRevision = GetCpuUcodeRevision (); > - MicrocodeData = NULL; > - while (TRUE) { > - /// > - /// Find the next patch address > - /// > - Status = RetrieveMicrocode (&MicrocodeData); > - DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); > - > - if (Status != EFI_SUCCESS) { > - break; > - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, > &UcodeRevision)) { > - break; > - } > - } > - > - if (EFI_ERROR (Status)) { > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; > - } > - > - /// > - /// Check that microcode patch size is <= 128K max size, > - /// then copy the patch from FV to temp buffer for faster access. > - /// > - MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; > - > - if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { > - MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES > (MicrocodeBufferSize)); > - if (MicrocodeBuffer != NULL) { > - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); > - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); > - > - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; > - } else { > - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for > Microcode Patch.\n")); > - } > - } else { > - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max > allowed size of 128K.\n")); > - } > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif > > /** > Load Config block default > @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( > CpuConfig->AesEnable = CPU_FEATURE_ENABLE; > CpuConfig->EnableRsr = CPU_FEATURE_ENABLE; > CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 > (PcdSmmbaseSwSmi); > -#ifndef FSP_FLAG > - CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch > (); -#endif > + // > + // This function is shared by both non-FSP and FSP scenarios and always > executed unconditionally. > + // Since FSP/silicon code should not unconditionally access any > + hardcoding flash regions (that region might not be accessible // in > unknown platforms), the microcode location searching code should be > moved to outside silicon code scope. > + // > + CpuConfig->MicrocodePatchAddress = 0; > } > > > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > index 813b868fcf..c3a8bbf539 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > +++ yLib.c > @@ -2,7 +2,7 @@ > This file is PeiSiPolicyLib library creates default settings of RC > Policy and installs RC Policy PPI. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -196,8 +196,6 @@ DumpSiPolicy ( > > /** > SiInstallPolicyPpi installs SiPolicyPpi. > - While installed, RC assumes the Policy is ready and finalized. So please > update and override > - any setting before calling this function. > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > > @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( > Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) > &SiConfig); > ASSERT_EFI_ERROR (Status); > > + // > + // Install Silicon Policy PPI > + // > + Status = PeiServicesInstallPpi (SiPolicyPpiDesc); > + ASSERT_EFI_ERROR (Status); > + return Status; > +} > + > +/** > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > + While installed, RC assumes the Policy is ready and finalized. So > +please update and override > + any setting before calling this function. > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > +**/ > +EFI_STATUS > +EFIAPI > +SiInstallPolicyReadyPpi ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; > + SI_POLICY_PPI *SiPolicy; > + > + SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof > + (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPpiDesc == NULL) { > + ASSERT (FALSE); > + return EFI_OUT_OF_RESOURCES; > + } > + > + SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid; > + SiPolicyPpiDesc->Ppi = NULL; > + > + SiPolicy = NULL; > + Status = PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **)&SiPolicy > + ); > + ASSERT_EFI_ERROR(Status); > + > DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); > - DumpSiPolicy (SiPolicyPpi); > + DumpSiPolicy (SiPolicy); > > // > - // Install Silicon Policy PPI > + // Install Silicon Policy Ready PPI > // > Status = PeiServicesInstallPpi (SiPolicyPpiDesc); > ASSERT_EFI_ERROR (Status); > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > m.c > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > m.c > index e0d83cb467..e6506a0445 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > m.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > +++ yLibPreMem.c > @@ -2,7 +2,7 @@ > This file is PeiSiPolicyLib library creates default settings of RC > Policy and installs RC Policy PPI. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( > > /** > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > - While installed, RC assumes the Policy is ready and finalized. So please > update and override > - any setting before calling this function. > > @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance > > @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( > SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi; > > // > + // Install Silicon Policy PPI > + // > + Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > + ASSERT_EFI_ERROR (Status); > + return Status; > +} > + > +/** > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > + While installed, RC assumes the Policy is ready and finalized. So > +please update and override > + any setting before calling this function. > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > +**/ > +EFI_STATUS > +EFIAPI > +SiPreMemInstallPolicyReadyPpi ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; > + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; > + > + SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool > + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPreMemPpiDesc == NULL) { > + ASSERT (FALSE); > + return EFI_OUT_OF_RESOURCES; > + } > + > + SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid; > + SiPolicyPreMemPpiDesc->Ppi = NULL; > + > + Status = PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **)&SiPolicyPreMemPpi > + ); > + ASSERT_EFI_ERROR (Status); > + > + // > // Print whole PCH_POLICY_PPI and serial out. > // > PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ > SiPreMemInstallPolicyPpi ( > CpuPreMemPrintPolicy (SiPolicyPreMemPpi); > > // > - // Install Silicon Policy PPI > + // Install PreMem Silicon Policy Ready PPI > // > Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > ASSERT_EFI_ERROR (Status); > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .c > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .c > index 0de415ad19..6cbc39c29e 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > +++ eiPolicyInit.c > @@ -1,7 +1,7 @@ > /** @file > This file is SampleCode for Intel PEI Platform Policy initialization. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( > IN OUT VOID *Policy > ) > { > - EFI_STATUS Status; > - SI_POLICY_PPI *SiPolicyPpi; > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicyPpi; > + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post- > Memory...\n")); > > ASSERT (Policy == NULL); > > // > - // Call SiCreateConfigBlocks to initialize Silicon Policy structure > - // and get all Intel default policy settings. > + // Locate Policy init PPI to install default silicon policy > // > - Status = SiCreateConfigBlocks (&SiPolicyPpi); > + Status = PeiServicesLocatePpi ( > + &gSiDefaultPolicyInitPpiGuid, > + 0, > + NULL, > + (VOID **) &PeiSiDefaultPolicyInitPpi > + ); > ASSERT_EFI_ERROR (Status); > + if (PeiSiDefaultPolicyInitPpi != NULL) { > + Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); > + ASSERT_EFI_ERROR (Status); > + if (Status == EFI_SUCCESS) { > + Status = PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPolicyPpi > + ); > + ASSERT_EFI_ERROR (Status); > + } > + } > > return SiPolicyPpi; > } > @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( > // While installed, RC assumes the Policy is ready and finalized. So please > // update and override any setting before calling this function. > // > - Status = SiInstallPolicyPpi (SiPolicyPpi); > + Status = SiInstallPolicyReadyPpi (); > ASSERT_EFI_ERROR (Status); > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post- > Memory\n")); diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > PreMem.c > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > PreMem.c > index fd76b4fac3..8e138b1eb2 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > PreMem.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > +++ eiPolicyInitPreMem.c > @@ -1,7 +1,7 @@ > /** @file > This file is SampleCode for Intel PEI Platform Policy initialization. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( > IN OUT VOID *Policy > ) > { > - EFI_STATUS Status; > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > + *PeiPreMemSiDefaultPolicyInitPpi; > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre- > Memory...\n")); > > ASSERT (Policy == NULL); > + SiPreMemPolicyPpi = NULL; > > // > - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure > - // and get all intel default policy settings. > + // Locate Policy init PPI to install default silicon policy > // > - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); > + Status = PeiServicesLocatePpi ( > + &gSiPreMemDefaultPolicyInitPpiGuid, > + 0, > + NULL, > + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi > + ); > ASSERT_EFI_ERROR (Status); > - > + if (PeiPreMemSiDefaultPolicyInitPpi != NULL) { > + Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); > + ASSERT_EFI_ERROR (Status); > + if (Status == EFI_SUCCESS) { > + Status = PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + ASSERT_EFI_ERROR (Status); > + } > + } > return SiPreMemPolicyPpi; > } > > @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( > ) > { > EFI_STATUS Status; > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > - > - SiPreMemPolicyPpi = Policy; > > // > - // Install SiPreMemPolicyPpi. > + // Install Policy Ready PPI > // While installed, RC assumes the Policy is ready and finalized. So please > // update and override any setting before calling this function. > // > - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); > + Status = SiPreMemInstallPolicyReadyPpi (); > ASSERT_EFI_ERROR (Status); > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre- > Memory\n")); diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > b.c > b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > b.c > index 31c7d59d1d..803de0999e 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > b.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePo > +++ licyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file is PeiMePolicy library. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( > DEBUG_CODE_BEGIN (); > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -- > ---------------\n")); > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", > MePeiPreMemConfig->Header.Revision)); > - ASSERT (MePeiPreMemConfig->Header.Revision == > ME_PEI_PREMEM_CONFIG_REVISION); > + ASSERT (MePeiPreMemConfig->Header.Revision >= > + ME_PEI_PREMEM_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", > MePeiPreMemConfig->HeciTimeouts)); > DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", > MePeiPreMemConfig->DidInitStat)); > @@ -129,7 +129,7 @@ PrintMePeiConfig ( > DEBUG_CODE_BEGIN (); > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG --------------- > --\n")); > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig- > >Header.Revision)); > - ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION); > + ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig- > >EndOfPostMessage)); > DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig- > >Heci3Enabled)); > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > SaPolicyLib.c > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > SaPolicyLib.c > index 67fe214d0e..be36468b1e 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > SaPolicyLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLi > +++ b/DxeSaPolicyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file provide services for DXE phase policy default initialization > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN > -----------------\n")); > DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy- > >TableHeader.Header.Revision)); > - ASSERT (SaPolicy->TableHeader.Header.Revision == > SA_POLICY_PROTOCOL_REVISION); > + ASSERT (SaPolicy->TableHeader.Header.Revision >= > + SA_POLICY_PROTOCOL_REVISION); > DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -- > ---------------\n")); > DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig- > >EnableAbove4GBMmio)); > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END --- > --------------\n")); diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > ntPolicy.c > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > ntPolicy.c > index 8b3a81a1c4..5c80fca88e 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > ntPolicy.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi > +++ b/SaPrintPolicy.c > @@ -1,7 +1,7 @@ > /** @file > This file provides service for PEI phase policy printing > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) > Print BEGIN -----------------\n")); > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi- > >TableHeader.Header.Revision)); > - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == > SI_PREMEM_POLICY_REVISION); > + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= > + SI_PREMEM_POLICY_REVISION); > > DEBUG ((DEBUG_INFO, "------------------------ > SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); > DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig- > >Header.Revision)); > - ASSERT (MiscPeiPreMemConfig->Header.Revision == > SA_MISC_PEI_PREMEM_CONFIG_REVISION); > + ASSERT (MiscPeiPreMemConfig->Header.Revision >= > + SA_MISC_PEI_PREMEM_CONFIG_REVISION); > DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", > SA_MC_MAX_SOCKETS)); > for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) { > DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig- > >SpdAddressTable[Index])); > @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( > DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------- > -----------------\n")); > DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig- > >Header.GuidHob.Name)); > DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig- > >Header.Revision)); > - ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION); > + ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION); > DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig- > >Header.GuidHob.Header.HobLength)); > DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig- > >HobBufferSize)); > DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig- > >EccSupport)); > @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN - > ----------------\n")); > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi- > >TableHeader.Header.Revision)); > - ASSERT (SiPolicyPpi->TableHeader.Header.Revision == > SI_POLICY_REVISION); > + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= > + SI_POLICY_REVISION); > DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG ------- > ----------\n")); > DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); > - ASSERT (GtConfig->Header.Revision == > GRAPHICS_PEI_CONFIG_REVISION); > + ASSERT (GtConfig->Header.Revision >= > GRAPHICS_PEI_CONFIG_REVISION); > DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig- > >PeiGraphicsPeimInit)); > DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); > DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); > DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig- > >GraphicsConfigPtr)); > DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG ----------------- > \n")); > DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); > - ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION); > + ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION); > DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); > DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); > DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", > SA_VTD_ENGINE_NUMBER)); diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > index 2dc7be45d2..aa88e761b8 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > @@ -1,7 +1,7 @@ > /** @file > This file declares various data structures used in CPU reference code. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define CPU_CAUSE_BY_ASSOCIATION 0x0100 > #define CPU_CAUSE_UNSPECIFIED 0x8000 > > +#define MAX_MICROCODE_PATCH_SIZE 0x20000 > + > typedef UINT32 CPU_STATE_CHANGE_CAUSE; > > /// > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Library.h > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Library.h > index d2a475591d..23321d6432 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > Library.h > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp > +++ uPolicyLibrary.h > @@ -1,7 +1,7 @@ > /** @file > Header file for the PeiCpuPolicyLib library. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include > <Register/Cpuid.h> #include <Library/PcdLib.h> > > -#define MAX_MICROCODE_PATCH_SIZE 0x20000 > - > #endif // _PEI_CPU_POLICY_LIBRARY_H_ > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > index 7bd26863b5..2c0387f678 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > @@ -1,7 +1,7 @@ > /** @file > Prototype of the SiPolicyLib library. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( > > /** > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > - While installed, RC assumes the Policy is ready and finalized. So please > update and override > - any setting before calling this function. > > @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI > instance > > @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( > ); > > /** > - SiInstallPolicyPpi installs SiPolicyPpi. > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > While installed, RC assumes the Policy is ready and finalized. So please > update and override > any setting before calling this function. > > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > +**/ > +EFI_STATUS > +EFIAPI > +SiPreMemInstallPolicyReadyPpi ( > + VOID > + ); > + > +/** > + SiInstallPolicyPpi installs SiPolicyPpi. > + > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > > @retval EFI_SUCCESS The policy is installed. > @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( > ); > > /** > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > + While installed, RC assumes the Policy is ready and finalized. So > + please update and override any setting before calling this function. > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > +**/ > +EFI_STATUS > +EFIAPI > +SiInstallPolicyReadyPpi ( > + VOID > + ); > + > +/** > Print out all silicon policy information. > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyIni > t.h > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyIni > t.h > new file mode 100644 > index 0000000000..b8a526b9b7 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPol > +++ icyInit.h > @@ -0,0 +1,36 @@ > +/** @file > + This file defines the PPI function for installing PreMem silicon > +policy > + PPI with default settings. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > + > +// > +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. > +// > +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; > + > +/** > + Initialize and install default silicon policy PPI **/ typedef > +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) ( > + VOID > + ); > + > +/// > +/// This PPI provides function to install default silicon policy /// > +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { > + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; > +}; > + > +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; > + > +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > new file mode 100644 > index 0000000000..d620cf29d4 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyIni > +++ t.h > @@ -0,0 +1,36 @@ > +/** @file > + This file defines the PPI function for installing PostMem silicon > +policy > + PPI with default settings. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > + > +// > +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. > +// > +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI > +PEI_SI_DEFAULT_POLICY_INIT_PPI; > + > +/** > + Initialize and install default silicon policy PPI **/ typedef > +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) ( > + VOID > + ); > + > +/// > +/// This PPI provides function to install default silicon policy /// > +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { > + PEI_POLICY_INIT PeiPolicyInit; > +}; > + > +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; > + > +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > index 1d992cfbbd..47f58d16e9 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > +++ yLib.inf > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the PeiSiPolicyLib library. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # > @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES > > > [Ppis] > -gSiPolicyPpiGuid ## PRODUCES > -gSiPreMemPolicyPpiGuid ## PRODUCES > +gSiPolicyPpiGuid ## PRODUCES > +gSiPreMemPolicyPpiGuid ## PRODUCES > +gSiPreMemPolicyReadyPpiGuid ## PRODUCES > +gSiPolicyReadyPpiGuid ## PRODUCES > > [Pcd] > gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .h > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .h > index c38294cfbe..f2fecee8c6 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > .h > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > +++ eiPolicyInit.h > @@ -1,7 +1,7 @@ > /** @file > Header file for the PolicyInitPei PEIM. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include > <PiPei.h> #include <Library/DebugLib.h> #include > <Library/MemoryAllocationLib.h> > +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h> > +#include <Ppi/PeiSiDefaultPolicyInit.h> > > #include "PeiSiPolicyInit.h" > > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMe > mSiliconPolicyInitLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMe > mSiliconPolicyInitLib.inf > new file mode 100644 > index 0000000000..83c909e681 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > +++ eiPostMemSiliconPolicyInitLib.inf > @@ -0,0 +1,75 @@ > +## @file > +# Library functions for Policy Initialization Library. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +######################################################### > ############## > +######### > +# > +# Defines Section - statements that will be processed to create a Makefile. > +# > +######################################################### > ############## > +######### > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = PeiPostMemSiliconPolicyInitLib > + FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = SiliconPolicyInitLib > + > +# > +# The following information is for reference only and not required by the > build tools. > +# > +# VALID_ARCHITECTURES = IA32 > +# > + > +######################################################### > ############## > +######### > +# > +# Sources Section - list of files that are required for the build to succeed. > +# > +######################################################### > ############## > +######### > + > +[Sources] > + PeiPolicyInit.c > + PeiPolicyInit.h > + > +######################################################### > ############## > +######### > +# > +# Package Dependency Section - list of Package files that are required for > +# this module. > +# > +######################################################### > ############## > +######### > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + KabylakeSiliconPkg/SiPkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + SiPolicyLib > + DebugLib > + PeiServicesLib > + > +[Ppis] > + gSiDefaultPolicyInitPpiGuid ## CONSUMES > + > +[Pcd] > + # > + # Below PCD may not be consumed by this library but still adding them > +here > + # to make sure all of them can be built into PcdDataBase. > + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type. > + # > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate > + > +[Depex] > + gSiDefaultPolicyInitPpiGuid > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPol > icyInitLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMem > SiliconPolicyInitLib.inf > similarity index 83% > rename from > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolic > yInitLib.inf > rename to > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSili > conPolicyInitLib.inf > index 7982a5d87f..782e04a476 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPol > icyInitLib.inf > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > +++ eiPreMemSiliconPolicyInitLib.inf > @@ -1,7 +1,7 @@ > ### @file > # Library functions for Policy Initialization Library. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ > ########################################################## > ###################### > [Defines] > INF_VERSION = 0x00010005 > - BASE_NAME = PeiSiliconPolicyInitLib > + BASE_NAME = PeiPreMemSiliconPolicyInitLib > FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 > MODULE_TYPE = BASE > VERSION_STRING = 1.0 > @@ -34,7 +34,6 @@ > > [Sources] > PeiPolicyInitPreMem.c > - PeiPolicyInit.c > PeiPolicyInit.h > > > ########################################################## > ###################### > @@ -53,3 +52,9 @@ > SiPolicyLib > DebugLib > PeiServicesLib > + > +[Ppis] > + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES > + > +[Depex] > + gSiPreMemDefaultPolicyInitPpiGuid > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFsp.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFsp.inf > index 9ffb84fa1e..c11680656d 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFsp.inf > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs > +++ p/PeiSiliconPolicyInitLibFsp.inf > @@ -1,7 +1,7 @@ > ### @file > # Library functions for Fsp Policy Initialization Library. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ > MemoryAllocationLib > DebugPrintErrorLevelLib > FspWrapperApiLib > + SiPolicyLib > > [Pcd] > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > @@ -84,7 +85,7 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## > CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES > - > + > [Ppis] > gSiPolicyPpiGuid ## CONSUMES > gSiPreMemPolicyPpiGuid ## CONSUMES > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFspAml.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFspAml.inf > index aebd3583bc..1ace9aeb52 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > nPolicyInitLibFspAml.inf > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs > +++ p/PeiSiliconPolicyInitLibFspAml.inf > @@ -72,6 +72,7 @@ > MemoryAllocationLib > DebugPrintErrorLevelLib > FspWrapperApiLib > + SiPolicyLib > > [Pcd] > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > index a613079dd4..e9d3e5f918 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, > 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, > 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} > gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, > 0xc1, 0x89, 0xd0, 0xab, 0x8d}} > +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, > 0x82, 0x7c, 0xe3, 0x17, 0x79}} > +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, > +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGuid > += {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, > +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, > +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} > ## > ## SystemAgent > ## > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > csPeiConfig.h > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > csPeiConfig.h > index 4063f800e8..b835155c68 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > csPeiConfig.h > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/G > +++ raphicsPeiConfig.h > @@ -1,7 +1,7 @@ > /** @file > Policy definition for Internal Graphics Config Block (PostMem) > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ > typedef struct { > CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block > Header > + UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This > field is used to enable or disable RC6 (Render Standby): 0=FALSE, > <b>1=TRUE</b> > + UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD > PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> > + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP > TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> > + /** > + Offset 28:3 > + CdClock Frequency select\n > + 0 = 337.5 Mhz, 1 = 450 Mhz,\n > + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n > + **/ > + UINT32 CdClock : 3; > UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used > to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable > - UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future > use > + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is > used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, > 0- Disable > + UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max > GT frequency limited by user in multiples of 50MHz: Default value which > indicates normal frequency is <b>0xFF</b> > + UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for future > use > VOID* LogoPtr; ///< Offset 32 Address of Logo to be > displayed in PEI > UINT32 LogoSize; ///< Offset 36 Logo Size > VOID* GraphicsConfigPtr; ///< Offset 40 Address of the > Graphics Configuration Table > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > aPolicyLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > aPolicyLib.inf > index 8fae4cee61..c7454bd4a5 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > aPolicyLib.inf > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi > +++ b/PeiSaPolicyLib.inf > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the PeiSaPolicy library. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ > CpuMailboxLib SiConfigBlockLib RngLib SmbusLib > +PchCycleDecodingLib > > [Packages] > MdePkg/MdePkg.dec > -- > 2.13.3.windows.1 > > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. 2019-06-11 2:11 ` [edk2-devel] " Ni, Ray @ 2019-06-11 5:13 ` Chiu, Chasel 0 siblings, 0 replies; 9+ messages in thread From: Chiu, Chasel @ 2019-06-11 5:13 UTC (permalink / raw) To: Ni, Ray, devel@edk2.groups.io, Desimone, Nathaniel L Cc: Kubacki, Michael A, Chaganty, Rangasai V Hi Ray, Please see my reply below inline. Thanks! Chasel > -----Original Message----- > From: Ni, Ray > Sent: Tuesday, June 11, 2019 10:11 AM > To: devel@edk2.groups.io; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com> > Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V > <rangasai.v.chaganty@intel.com> > Subject: RE: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > DefaultPolicyInit PPI. > > Chasel, > Where is the code that produces DefaultPolicyInit PPI? > Is the code public available? Only DefaultPolicyInit PPI definition public, no producer code in KabylakeSiliconPkg. The producer code of DefaultPolicyInit PPI is inside FSP binary so it can produce different ConfigBlock structures from different FSP binary, and ConfigBlocks in KabylakeSiliconPkg is only for boot loader to fill UPD buffer in API mode, it is not used in Dispatch mode. > > And in general, I think the patch consists of several changes: > 1. change version compare from "==" to ">=" to support FSP be used in newer > board. > 2. Add definition of SiDefaultPolicyPpi > 3. Update non-FSP version of PeiSiliconPolicyInitLib to consume the > SiDefaultPolicyPpi > 4. Update config block for GFX > 5. Add SiXXXInstallPolicyReadyPpi > 6. maybe more.... > > Can you please try to separate the changes to small patches? Yes. I will follow this suggestion next time working on big change. > > Regarding to the changes in > KabylakeSiliconPkg\Library\PeiSiPolicyLib\PeiSiPolicyLibPreMem.c: > There are two APIs: SiPreMemInstallPolicyPpi and > SiPreMemInstallPolicyReadyPpi. > > When FSP runs in API mode, the calling flow is as below: > FspWrapperPeim::PeiMemoryDiscoveredNotify > --> MinPlatformPkg/../PeiFspWrapperPlatformLib::UpdateFspsUpdData > --> KabylakeSiliconPkg/.../SiliconPolicyInitPostMem > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiCreateConfigBlocks > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiInstallPolicyPpi > > Do you think that it's possible to update > KabylakeSiliconPkg/.../SiliconPolicyInitPostMem() to > call SiDefaultPolicyInitPpi->PeiPolicyInit()? To align the behavior when FSP runs > in dispatch mode. The actual policy initialization flows are aligned between API mode and Dispatch mode: SiliconPolicyPeiPostMem.efi: SiliconPolicyInitPostMem () -> SiliconPolicyUpdatePostMem () -> SiliconPolicyDonePostMem (). Only the library instances are different: FSP Wrapper running in Dispatch mode: \Silicon\Intel\KabylakeSiliconPkg\Library\PeiSiliconPolicyInitLib\PeiPolicyInit.c (Initialize ConfigBlocks policy) FSP Wrapper running in API mode: \Silicon\Intel\KabylakeSiliconPkg\Library\PeiSiliconPolicyInitLibFsp\PeiFspPolicyInitLib.c (Initialize ConfigBlocks policy first and then fill into UPD buffer) Also when running API mode the PPI produced by FSP binary - "SiDefaultPolicyInitPpi->PeiPolicyInit()" cannot be seen by boot loader as they are running with different PeiCore stacks. > > Thanks, > Ray > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate > > DeSimone > > Sent: Thursday, June 6, 2019 5:44 PM > > To: Chiu, Chasel <chasel.chiu@intel.com>; devel@edk2.groups.io > > Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V > > <rangasai.v.chaganty@intel.com> > > Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > > DefaultPolicyInit PPI. > > > > Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > > > > -----Original Message----- > > From: Chiu, Chasel > > Sent: Monday, June 3, 2019 9:47 AM > > To: devel@edk2.groups.io > > Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A > > <michael.a.kubacki@intel.com>; Chaganty, Rangasai V > > <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L > > <nathaniel.l.desimone@intel.com> > > Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. > > > > From: "Chasel, Chiu" <chasel.chiu@intel.com> > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 > > > > FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to > > consume and install policy with default settings built-in by FSP. > > Boot loader then may patch policy with per-board settings and then install > > PolicyReady PPI to start silicon initialization (policy consumer code) > > > > Since different version FSP has different version policy structure, the policy > > revision check code has been extended to support newer revision policy and > > the policy structure boot loader consuming has been aligned with the same > > structure inside FSP. > > (FSP will maintain policy structure backward > > compatibility) > > > > Also removed microcode location searching code from silicon scope because > > silicon code should not access hard-coded flash region unconditionally. > > This should be done by platform/boot loader side. > > > > Cc: Michael A Kubacki <michael.a.kubacki@intel.com> > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> > > --- > > > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLi > > b.c | 133 > +++++++---------------------------------------- > > -------------------------------------------------------------------------------------- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > > | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem > > .c | 50 > > ++++++++++++++++++++++++++++++++++++++++++++++---- > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c > > | 32 +++++++++++++++++++++++++------- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPr > > eMem.c | 39 > +++++++++++++++++++++++++++------- > > ----- > > > > Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib. > > c | 6 +++--- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSa > > PolicyLib.c | 4 ++-- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrint > > Policy.c | 14 +++++++------- > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > | 4 +++- > > > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLi > > brary.h | 4 +--- > > Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > | 32 ++++++++++++++++++++++++++++---- > > > > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h > > | 36 ++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > > | 36 ++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > > | 8 +++++--- > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h > > | 4 +++- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSi > > liconPolicyInitLib.inf | 75 > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > +++++++++++++++++ > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPoli > > cyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconP > > olicyInitLibFsp.inf | 5 +++-- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconP > > olicyInitLibFspAml.inf | 1 + > > Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > | 4 ++++ > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphics > > PeiConfig.h | 16 ++++++++++++++-- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaP > > olicyLib.inf | 3 ++- > > 22 files changed, 384 insertions(+), 186 deletions(-) > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Lib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Lib.c > > index cb7f379e0f..eb83cd4918 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Lib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp > > +++ uPolicyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is PeiCpuPolicy library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include <Library/ConfigBlockLib.h> #include <Library/PostCodeLib.h> > > > > -#ifndef FSP_FLAG > > -/** > > - Get the next microcode patch pointer. > > - > > - @param[in, out] MicrocodeData - Input is a pointer to the last microcode > > patch address found, > > - and output points to the next patch address found. > > - > > - @retval EFI_SUCCESS - Patch found. > > - @retval EFI_NOT_FOUND - Patch not found. > > -**/ > > -EFI_STATUS > > -EFIAPI > > -RetrieveMicrocode ( > > - IN OUT CPU_MICROCODE_HEADER **MicrocodeData > > - ) > > -{ > > - UINTN MicrocodeStart; > > - UINTN MicrocodeEnd; > > - UINTN TotalSize; > > - > > - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 > > (PcdFlashMicrocodeFvSize) == 0)) { > > - return EFI_NOT_FOUND; > > - } > > - > > - /// > > - /// Microcode binary in SEC > > - /// > > - MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > > - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 > > (PcdFlashMicrocodeFvBase))->HeaderLength + > > - sizeof (EFI_FFS_FILE_HEADER); > > - > > - MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > > (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); > > - > > - if (*MicrocodeData == NULL) { > > - *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) > > MicrocodeStart; > > - } else { > > - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) > > MicrocodeStart) { > > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart > > \n")); > > - return EFI_NOT_FOUND; > > - } > > - > > - TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); > > - if (TotalSize == 0) { > > - TotalSize = 2048; > > - } > > - > > - *MicrocodeData = (CPU_MICROCODE_HEADER *) > > ((UINTN)*MicrocodeData + TotalSize); > > - if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) > > (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { > > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd > > \n")); > > - return EFI_NOT_FOUND; > > - } > > - } > > - return EFI_SUCCESS; > > -} > > - > > -/** > > - Get the microcode patch pointer. > > - > > - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL > > if not found. > > -**/ > > -EFI_PHYSICAL_ADDRESS > > -PlatformCpuLocateMicrocodePatch ( > > - VOID > > - ) > > -{ > > - EFI_STATUS Status; > > - CPU_MICROCODE_HEADER *MicrocodeData; > > - EFI_CPUID_REGISTER Cpuid; > > - UINT32 UcodeRevision; > > - UINTN MicrocodeBufferSize; > > - VOID *MicrocodeBuffer = NULL; > > - > > - AsmCpuid ( > > - CPUID_VERSION_INFO, > > - &Cpuid.RegEax, > > - &Cpuid.RegEbx, > > - &Cpuid.RegEcx, > > - &Cpuid.RegEdx > > - ); > > - > > - UcodeRevision = GetCpuUcodeRevision (); > > - MicrocodeData = NULL; > > - while (TRUE) { > > - /// > > - /// Find the next patch address > > - /// > > - Status = RetrieveMicrocode (&MicrocodeData); > > - DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); > > - > > - if (Status != EFI_SUCCESS) { > > - break; > > - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, > > &UcodeRevision)) { > > - break; > > - } > > - } > > - > > - if (EFI_ERROR (Status)) { > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; > > - } > > - > > - /// > > - /// Check that microcode patch size is <= 128K max size, > > - /// then copy the patch from FV to temp buffer for faster access. > > - /// > > - MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; > > - > > - if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { > > - MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES > > (MicrocodeBufferSize)); > > - if (MicrocodeBuffer != NULL) { > > - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); > > - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); > > - > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; > > - } else { > > - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for > > Microcode Patch.\n")); > > - } > > - } else { > > - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max > > allowed size of 128K.\n")); > > - } > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif > > > > /** > > Load Config block default > > @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( > > CpuConfig->AesEnable = CPU_FEATURE_ENABLE; > > CpuConfig->EnableRsr = CPU_FEATURE_ENABLE; > > CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 > > (PcdSmmbaseSwSmi); > > -#ifndef FSP_FLAG > > - CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch > > (); -#endif > > + // > > + // This function is shared by both non-FSP and FSP scenarios and always > > executed unconditionally. > > + // Since FSP/silicon code should not unconditionally access any > > + hardcoding flash regions (that region might not be accessible // in > > unknown platforms), the microcode location searching code should be > > moved to outside silicon code scope. > > + // > > + CpuConfig->MicrocodePatchAddress = 0; > > } > > > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > > index 813b868fcf..c3a8bbf539 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > > +++ yLib.c > > @@ -2,7 +2,7 @@ > > This file is PeiSiPolicyLib library creates default settings of RC > > Policy and installs RC Policy PPI. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -196,8 +196,6 @@ DumpSiPolicy ( > > > > /** > > SiInstallPolicyPpi installs SiPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So please > > update and override > > - any setting before calling this function. > > > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > > > > @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( > > Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) > > &SiConfig); > > ASSERT_EFI_ERROR (Status); > > > > + // > > + // Install Silicon Policy PPI > > + // > > + Status = PeiServicesInstallPpi (SiPolicyPpiDesc); > > + ASSERT_EFI_ERROR (Status); > > + return Status; > > +} > > + > > +/** > > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > +please update and override > > + any setting before calling this function. > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiInstallPolicyReadyPpi ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; > > + SI_POLICY_PPI *SiPolicy; > > + > > + SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof > > + (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPpiDesc == NULL) { > > + ASSERT (FALSE); > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | > > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > > + SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid; > > + SiPolicyPpiDesc->Ppi = NULL; > > + > > + SiPolicy = NULL; > > + Status = PeiServicesLocatePpi ( > > + &gSiPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **)&SiPolicy > > + ); > > + ASSERT_EFI_ERROR(Status); > > + > > DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); > > - DumpSiPolicy (SiPolicyPpi); > > + DumpSiPolicy (SiPolicy); > > > > // > > - // Install Silicon Policy PPI > > + // Install Silicon Policy Ready PPI > > // > > Status = PeiServicesInstallPpi (SiPolicyPpiDesc); > > ASSERT_EFI_ERROR (Status); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > > m.c > > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > > m.c > > index e0d83cb467..e6506a0445 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe > > m.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > > +++ yLibPreMem.c > > @@ -2,7 +2,7 @@ > > This file is PeiSiPolicyLib library creates default settings of RC > > Policy and installs RC Policy PPI. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( > > > > /** > > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So please > > update and override > > - any setting before calling this function. > > > > @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance > > > > @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( > > SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi; > > > > // > > + // Install Silicon Policy PPI > > + // > > + Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > > + ASSERT_EFI_ERROR (Status); > > + return Status; > > +} > > + > > +/** > > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > +please update and override > > + any setting before calling this function. > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiPreMemInstallPolicyReadyPpi ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; > > + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; > > + > > + SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool > > + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPreMemPpiDesc == NULL) { > > + ASSERT (FALSE); > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | > > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > > + SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid; > > + SiPolicyPreMemPpiDesc->Ppi = NULL; > > + > > + Status = PeiServicesLocatePpi ( > > + &gSiPreMemPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **)&SiPolicyPreMemPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + > > + // > > // Print whole PCH_POLICY_PPI and serial out. > > // > > PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ > > SiPreMemInstallPolicyPpi ( > > CpuPreMemPrintPolicy (SiPolicyPreMemPpi); > > > > // > > - // Install Silicon Policy PPI > > + // Install PreMem Silicon Policy Ready PPI > > // > > Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > > ASSERT_EFI_ERROR (Status); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .c > > index 0de415ad19..6cbc39c29e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > > +++ eiPolicyInit.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is SampleCode for Intel PEI Platform Policy initialization. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( > > IN OUT VOID *Policy > > ) > > { > > - EFI_STATUS Status; > > - SI_POLICY_PPI *SiPolicyPpi; > > + EFI_STATUS Status; > > + SI_POLICY_PPI *SiPolicyPpi; > > + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post- > > Memory...\n")); > > > > ASSERT (Policy == NULL); > > > > // > > - // Call SiCreateConfigBlocks to initialize Silicon Policy structure > > - // and get all Intel default policy settings. > > + // Locate Policy init PPI to install default silicon policy > > // > > - Status = SiCreateConfigBlocks (&SiPolicyPpi); > > + Status = PeiServicesLocatePpi ( > > + &gSiDefaultPolicyInitPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &PeiSiDefaultPolicyInitPpi > > + ); > > ASSERT_EFI_ERROR (Status); > > + if (PeiSiDefaultPolicyInitPpi != NULL) { > > + Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); > > + ASSERT_EFI_ERROR (Status); > > + if (Status == EFI_SUCCESS) { > > + Status = PeiServicesLocatePpi ( > > + &gSiPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &SiPolicyPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + } > > + } > > > > return SiPolicyPpi; > > } > > @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( > > // While installed, RC assumes the Policy is ready and finalized. So please > > // update and override any setting before calling this function. > > // > > - Status = SiInstallPolicyPpi (SiPolicyPpi); > > + Status = SiInstallPolicyReadyPpi (); > > ASSERT_EFI_ERROR (Status); > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post- > > Memory\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > PreMem.c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > PreMem.c > > index fd76b4fac3..8e138b1eb2 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > PreMem.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > > +++ eiPolicyInitPreMem.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is SampleCode for Intel PEI Platform Policy initialization. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( > > IN OUT VOID *Policy > > ) > > { > > - EFI_STATUS Status; > > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > + EFI_STATUS Status; > > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > > + *PeiPreMemSiDefaultPolicyInitPpi; > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre- > > Memory...\n")); > > > > ASSERT (Policy == NULL); > > + SiPreMemPolicyPpi = NULL; > > > > // > > - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure > > - // and get all intel default policy settings. > > + // Locate Policy init PPI to install default silicon policy > > // > > - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); > > + Status = PeiServicesLocatePpi ( > > + &gSiPreMemDefaultPolicyInitPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi > > + ); > > ASSERT_EFI_ERROR (Status); > > - > > + if (PeiPreMemSiDefaultPolicyInitPpi != NULL) { > > + Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); > > + ASSERT_EFI_ERROR (Status); > > + if (Status == EFI_SUCCESS) { > > + Status = PeiServicesLocatePpi ( > > + &gSiPreMemPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &SiPreMemPolicyPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + } > > + } > > return SiPreMemPolicyPpi; > > } > > > > @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( > > ) > > { > > EFI_STATUS Status; > > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > - > > - SiPreMemPolicyPpi = Policy; > > > > // > > - // Install SiPreMemPolicyPpi. > > + // Install Policy Ready PPI > > // While installed, RC assumes the Policy is ready and finalized. So please > > // update and override any setting before calling this function. > > // > > - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); > > + Status = SiPreMemInstallPolicyReadyPpi (); > > ASSERT_EFI_ERROR (Status); > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre- > > Memory\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > > b.c > > b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > > b.c > > index 31c7d59d1d..803de0999e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi > > b.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePo > > +++ licyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is PeiMePolicy library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( > > DEBUG_CODE_BEGIN (); > > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -- > > ---------------\n")); > > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", > > MePeiPreMemConfig->Header.Revision)); > > - ASSERT (MePeiPreMemConfig->Header.Revision == > > ME_PEI_PREMEM_CONFIG_REVISION); > > + ASSERT (MePeiPreMemConfig->Header.Revision >= > > + ME_PEI_PREMEM_CONFIG_REVISION); > > > > DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", > > MePeiPreMemConfig->HeciTimeouts)); > > DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", > > MePeiPreMemConfig->DidInitStat)); > > @@ -129,7 +129,7 @@ PrintMePeiConfig ( > > DEBUG_CODE_BEGIN (); > > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG --------------- > > --\n")); > > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig- > > >Header.Revision)); > > - ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION); > > + ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION); > > > > DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", > MePeiConfig- > > >EndOfPostMessage)); > > DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig- > > >Heci3Enabled)); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > > SaPolicyLib.c > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > > SaPolicyLib.c > > index 67fe214d0e..be36468b1e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dxe > > SaPolicyLib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLi > > +++ b/DxeSaPolicyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file provide services for DXE phase policy default initialization > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN > > -----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy- > > >TableHeader.Header.Revision)); > > - ASSERT (SaPolicy->TableHeader.Header.Revision == > > SA_POLICY_PROTOCOL_REVISION); > > + ASSERT (SaPolicy->TableHeader.Header.Revision >= > > + SA_POLICY_PROTOCOL_REVISION); > > DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -- > > ---------------\n")); > > DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig- > > >EnableAbove4GBMmio)); > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END --- > > --------------\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > > ntPolicy.c > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > > ntPolicy.c > > index 8b3a81a1c4..5c80fca88e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPri > > ntPolicy.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi > > +++ b/SaPrintPolicy.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file provides service for PEI phase policy printing > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) > > Print BEGIN -----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi- > > >TableHeader.Header.Revision)); > > - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == > > SI_PREMEM_POLICY_REVISION); > > + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= > > + SI_PREMEM_POLICY_REVISION); > > > > DEBUG ((DEBUG_INFO, "------------------------ > > SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig- > > >Header.Revision)); > > - ASSERT (MiscPeiPreMemConfig->Header.Revision == > > SA_MISC_PEI_PREMEM_CONFIG_REVISION); > > + ASSERT (MiscPeiPreMemConfig->Header.Revision >= > > + SA_MISC_PEI_PREMEM_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", > > SA_MC_MAX_SOCKETS)); > > for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) { > > DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig- > > >SpdAddressTable[Index])); > > @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( > > DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------- > > -----------------\n")); > > DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig- > > >Header.GuidHob.Name)); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig- > > >Header.Revision)); > > - ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION); > > + ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig- > > >Header.GuidHob.Header.HobLength)); > > DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig- > > >HobBufferSize)); > > DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig- > > >EccSupport)); > > @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN - > > ----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi- > > >TableHeader.Header.Revision)); > > - ASSERT (SiPolicyPpi->TableHeader.Header.Revision == > > SI_POLICY_REVISION); > > + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= > > + SI_POLICY_REVISION); > > DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG ------- > > ----------\n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); > > - ASSERT (GtConfig->Header.Revision == > > GRAPHICS_PEI_CONFIG_REVISION); > > + ASSERT (GtConfig->Header.Revision >= > > GRAPHICS_PEI_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig- > > >PeiGraphicsPeimInit)); > > DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); > > DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); > > DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig- > > >GraphicsConfigPtr)); > > DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG ----------------- > > \n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); > > - ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION); > > + ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); > > DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); > > DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", > > SA_VTD_ENGINE_NUMBER)); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > index 2dc7be45d2..aa88e761b8 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > @@ -1,7 +1,7 @@ > > /** @file > > This file declares various data structures used in CPU reference code. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define CPU_CAUSE_BY_ASSOCIATION 0x0100 > > #define CPU_CAUSE_UNSPECIFIED 0x8000 > > > > +#define MAX_MICROCODE_PATCH_SIZE 0x20000 > > + > > typedef UINT32 CPU_STATE_CHANGE_CAUSE; > > > > /// > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Library.h > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Library.h > > index d2a475591d..23321d6432 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy > > Library.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp > > +++ uPolicyLibrary.h > > @@ -1,7 +1,7 @@ > > /** @file > > Header file for the PeiCpuPolicyLib library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include > > <Register/Cpuid.h> #include <Library/PcdLib.h> > > > > -#define MAX_MICROCODE_PATCH_SIZE 0x20000 > > - > > #endif // _PEI_CPU_POLICY_LIBRARY_H_ > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > index 7bd26863b5..2c0387f678 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > @@ -1,7 +1,7 @@ > > /** @file > > Prototype of the SiPolicyLib library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( > > > > /** > > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So please > > update and override > > - any setting before calling this function. > > > > @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI > > instance > > > > @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( > > ); > > > > /** > > - SiInstallPolicyPpi installs SiPolicyPpi. > > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > > While installed, RC assumes the Policy is ready and finalized. So please > > update and override > > any setting before calling this function. > > > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiPreMemInstallPolicyReadyPpi ( > > + VOID > > + ); > > + > > +/** > > + SiInstallPolicyPpi installs SiPolicyPpi. > > + > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > > > > @retval EFI_SUCCESS The policy is installed. > > @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( > > ); > > > > /** > > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > + please update and override any setting before calling this function. > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiInstallPolicyReadyPpi ( > > + VOID > > + ); > > + > > +/** > > Print out all silicon policy information. > > > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyIni > > t.h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyIni > > t.h > > new file mode 100644 > > index 0000000000..b8a526b9b7 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPol > > +++ icyInit.h > > @@ -0,0 +1,36 @@ > > +/** @file > > + This file defines the PPI function for installing PreMem silicon > > +policy > > + PPI with default settings. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > + > > +// > > +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. > > +// > > +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > > +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; > > + > > +/** > > + Initialize and install default silicon policy PPI **/ typedef > > +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) ( > > + VOID > > + ); > > + > > +/// > > +/// This PPI provides function to install default silicon policy /// > > +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { > > + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; > > +}; > > + > > +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; > > + > > +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > > new file mode 100644 > > index 0000000000..d620cf29d4 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyIni > > +++ t.h > > @@ -0,0 +1,36 @@ > > +/** @file > > + This file defines the PPI function for installing PostMem silicon > > +policy > > + PPI with default settings. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > + > > +// > > +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. > > +// > > +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI > > +PEI_SI_DEFAULT_POLICY_INIT_PPI; > > + > > +/** > > + Initialize and install default silicon policy PPI **/ typedef > > +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) ( > > + VOID > > + ); > > + > > +/// > > +/// This PPI provides function to install default silicon policy /// > > +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { > > + PEI_POLICY_INIT PeiPolicyInit; > > +}; > > + > > +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; > > + > > +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > > index 1d992cfbbd..47f58d16e9 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic > > +++ yLib.inf > > @@ -1,7 +1,7 @@ > > ## @file > > # Component description file for the PeiSiPolicyLib library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # > > @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES > > > > > > [Ppis] > > -gSiPolicyPpiGuid ## PRODUCES > > -gSiPreMemPolicyPpiGuid ## PRODUCES > > +gSiPolicyPpiGuid ## PRODUCES > > +gSiPreMemPolicyPpiGuid ## PRODUCES > > +gSiPreMemPolicyReadyPpiGuid ## PRODUCES > > +gSiPolicyReadyPpiGuid ## PRODUCES > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .h > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .h > > index c38294cfbe..f2fecee8c6 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit > > .h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > > +++ eiPolicyInit.h > > @@ -1,7 +1,7 @@ > > /** @file > > Header file for the PolicyInitPei PEIM. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include > > <PiPei.h> #include <Library/DebugLib.h> #include > > <Library/MemoryAllocationLib.h> > > +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h> > > +#include <Ppi/PeiSiDefaultPolicyInit.h> > > > > #include "PeiSiPolicyInit.h" > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMe > > mSiliconPolicyInitLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMe > > mSiliconPolicyInitLib.inf > > new file mode 100644 > > index 0000000000..83c909e681 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > > +++ eiPostMemSiliconPolicyInitLib.inf > > @@ -0,0 +1,75 @@ > > +## @file > > +# Library functions for Policy Initialization Library. > > +# > > +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # > > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Defines Section - statements that will be processed to create a Makefile. > > +# > > +######################################################### > > ############## > > +######### > > +[Defines] > > + INF_VERSION = 0x00010005 > > + BASE_NAME = PeiPostMemSiliconPolicyInitLib > > + FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4 > > + MODULE_TYPE = BASE > > + VERSION_STRING = 1.0 > > + LIBRARY_CLASS = SiliconPolicyInitLib > > + > > +# > > +# The following information is for reference only and not required by the > > build tools. > > +# > > +# VALID_ARCHITECTURES = IA32 > > +# > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Sources Section - list of files that are required for the build to succeed. > > +# > > +######################################################### > > ############## > > +######### > > + > > +[Sources] > > + PeiPolicyInit.c > > + PeiPolicyInit.h > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Package Dependency Section - list of Package files that are required for > > +# this module. > > +# > > +######################################################### > > ############## > > +######### > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + KabylakeSiliconPkg/SiPkg.dec > > + UefiCpuPkg/UefiCpuPkg.dec > > + > > +[LibraryClasses] > > + SiPolicyLib > > + DebugLib > > + PeiServicesLib > > + > > +[Ppis] > > + gSiDefaultPolicyInitPpiGuid ## CONSUMES > > + > > +[Pcd] > > + # > > + # Below PCD may not be consumed by this library but still adding them > > +here > > + # to make sure all of them can be built into PcdDataBase. > > + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type. > > + # > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > > + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > > + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate > > + > > +[Depex] > > + gSiDefaultPolicyInitPpiGuid > > diff --git > > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPol > > icyInitLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMem > > SiliconPolicyInitLib.inf > > similarity index 83% > > rename from > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolic > > yInitLib.inf > > rename to > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSili > > conPolicyInitLib.inf > > index 7982a5d87f..782e04a476 100644 > > --- > > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPol > > icyInitLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P > > +++ eiPreMemSiliconPolicyInitLib.inf > > @@ -1,7 +1,7 @@ > > ### @file > > # Library functions for Policy Initialization Library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ > > ########################################################## > > ###################### > > [Defines] > > INF_VERSION = 0x00010005 > > - BASE_NAME = PeiSiliconPolicyInitLib > > + BASE_NAME = PeiPreMemSiliconPolicyInitLib > > FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 > > MODULE_TYPE = BASE > > VERSION_STRING = 1.0 > > @@ -34,7 +34,6 @@ > > > > [Sources] > > PeiPolicyInitPreMem.c > > - PeiPolicyInit.c > > PeiPolicyInit.h > > > > > > ########################################################## > > ###################### > > @@ -53,3 +52,9 @@ > > SiPolicyLib > > DebugLib > > PeiServicesLib > > + > > +[Ppis] > > + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES > > + > > +[Depex] > > + gSiPreMemDefaultPolicyInitPpiGuid > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFsp.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFsp.inf > > index 9ffb84fa1e..c11680656d 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFsp.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs > > +++ p/PeiSiliconPolicyInitLibFsp.inf > > @@ -1,7 +1,7 @@ > > ### @file > > # Library functions for Fsp Policy Initialization Library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ > > MemoryAllocationLib > > DebugPrintErrorLevelLib > > FspWrapperApiLib > > + SiPolicyLib > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > > @@ -84,7 +85,7 @@ > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## > > CONSUMES > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > CONSUMES > > - > > + > > [Ppis] > > gSiPolicyPpiGuid ## CONSUMES > > gSiPreMemPolicyPpiGuid ## CONSUMES > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFspAml.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFspAml.inf > > index aebd3583bc..1ace9aeb52 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSilico > > nPolicyInitLibFspAml.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs > > +++ p/PeiSiliconPolicyInitLibFspAml.inf > > @@ -72,6 +72,7 @@ > > MemoryAllocationLib > > DebugPrintErrorLevelLib > > FspWrapperApiLib > > + SiPolicyLib > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > index a613079dd4..e9d3e5f918 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, > > 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01, > 0x7edc, > > 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} > > gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, > > 0xc1, 0x89, 0xd0, 0xab, 0x8d}} > > +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, > > 0x82, 0x7c, 0xe3, 0x17, 0x79}} > > +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, > > +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGuid > > += {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, > > +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, > > +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} > > ## > > ## SystemAgent > > ## > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > > csPeiConfig.h > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > > csPeiConfig.h > > index 4063f800e8..b835155c68 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphi > > csPeiConfig.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/G > > +++ raphicsPeiConfig.h > > @@ -1,7 +1,7 @@ > > /** @file > > Policy definition for Internal Graphics Config Block (PostMem) > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ > > typedef struct { > > CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config > Block > > Header > > + UINT32 RenderStandby : 1; ///< Offset > 28:0 :<b>(Test)</b> This > > field is used to enable or disable RC6 (Render Standby): 0=FALSE, > > <b>1=TRUE</b> > > + UINT32 PmSupport : 1; ///< Offset > 28:1 :<b>(Test)</b> IGD > > PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> > > + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP > > TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> > > + /** > > + Offset 28:3 > > + CdClock Frequency select\n > > + 0 = 337.5 Mhz, 1 = 450 Mhz,\n > > + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n > > + **/ > > + UINT32 CdClock : 3; > > UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is > used > > to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable > > - UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for > future > > use > > + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This > policy is > > used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, > > 0- Disable > > + UINT32 GtFreqMax : 8; ///< Offset 28:8 : > <b>(Test)</b> Max > > GT frequency limited by user in multiples of 50MHz: Default value which > > indicates normal frequency is <b>0xFF</b> > > + UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for > future > > use > > VOID* LogoPtr; ///< Offset 32 Address of Logo > to be > > displayed in PEI > > UINT32 LogoSize; ///< Offset 36 Logo Size > > VOID* GraphicsConfigPtr; ///< Offset 40 Address of the > > Graphics Configuration Table > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > > aPolicyLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > > aPolicyLib.inf > > index 8fae4cee61..c7454bd4a5 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS > > aPolicyLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi > > +++ b/PeiSaPolicyLib.inf > > @@ -1,7 +1,7 @@ > > ## @file > > # Component description file for the PeiSaPolicy library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ > > CpuMailboxLib SiConfigBlockLib RngLib SmbusLib > > +PchCycleDecodingLib > > > > [Packages] > > MdePkg/MdePkg.dec > > -- > > 2.13.3.windows.1 > > > > > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone @ 2019-06-11 0:37 ` Chaganty, Rangasai V 1 sibling, 0 replies; 9+ messages in thread From: Chaganty, Rangasai V @ 2019-06-11 0:37 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Desimone, Nathaniel L Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Monday, June 03, 2019 9:47 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to consume and install policy with default settings built-in by FSP. Boot loader then may patch policy with per-board settings and then install PolicyReady PPI to start silicon initialization (policy consumer code) Since different version FSP has different version policy structure, the policy revision check code has been extended to support newer revision policy and the policy structure boot loader consuming has been aligned with the same structure inside FSP. (FSP will maintain policy structure backward compatibility) Also removed microcode location searching code from silicon scope because silicon code should not access hard-coded flash region unconditionally. This should be done by platform/boot loader side. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 133 +++++++------------------------------------------------------------------------------------------------------------------------------ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c | 32 +++++++++++++++++++++++++------- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 39 +++++++++++++++++++++++++++------------ Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c | 6 +++--- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 4 ++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c | 14 +++++++------- Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h | 4 +--- Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h | 32 ++++++++++++++++++++++++++++---- Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 8 +++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h | 4 +++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf => PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 1 + Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 4 ++++ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h | 16 ++++++++++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 ++- 22 files changed, 384 insertions(+), 186 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c index cb7f379e0f..eb83cd4918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp +++ uPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/ConfigBlockLib.h> #include <Library/PostCodeLib.h> -#ifndef FSP_FLAG -/** - Get the next microcode patch pointer. - - @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, - and output points to the next patch address found. - - @retval EFI_SUCCESS - Patch found. - @retval EFI_NOT_FOUND - Patch not found. -**/ -EFI_STATUS -EFIAPI -RetrieveMicrocode ( - IN OUT CPU_MICROCODE_HEADER **MicrocodeData - ) -{ - UINTN MicrocodeStart; - UINTN MicrocodeEnd; - UINTN TotalSize; - - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { - return EFI_NOT_FOUND; - } - - /// - /// Microcode binary in SEC - /// - MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + - sizeof (EFI_FFS_FILE_HEADER); - - MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); - - if (*MicrocodeData == NULL) { - *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; - } else { - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); - return EFI_NOT_FOUND; - } - - TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); - if (TotalSize == 0) { - TotalSize = 2048; - } - - *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); - if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); - return EFI_NOT_FOUND; - } - } - return EFI_SUCCESS; -} - -/** - Get the microcode patch pointer. - - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. -**/ -EFI_PHYSICAL_ADDRESS -PlatformCpuLocateMicrocodePatch ( - VOID - ) -{ - EFI_STATUS Status; - CPU_MICROCODE_HEADER *MicrocodeData; - EFI_CPUID_REGISTER Cpuid; - UINT32 UcodeRevision; - UINTN MicrocodeBufferSize; - VOID *MicrocodeBuffer = NULL; - - AsmCpuid ( - CPUID_VERSION_INFO, - &Cpuid.RegEax, - &Cpuid.RegEbx, - &Cpuid.RegEcx, - &Cpuid.RegEdx - ); - - UcodeRevision = GetCpuUcodeRevision (); - MicrocodeData = NULL; - while (TRUE) { - /// - /// Find the next patch address - /// - Status = RetrieveMicrocode (&MicrocodeData); - DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); - - if (Status != EFI_SUCCESS) { - break; - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { - break; - } - } - - if (EFI_ERROR (Status)) { - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; - } - - /// - /// Check that microcode patch size is <= 128K max size, - /// then copy the patch from FV to temp buffer for faster access. - /// - MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; - - if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { - MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); - if (MicrocodeBuffer != NULL) { - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); - - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; - } else { - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); - } - } else { - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n")); - } - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif /** Load Config block default @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( CpuConfig->AesEnable = CPU_FEATURE_ENABLE; CpuConfig->EnableRsr = CPU_FEATURE_ENABLE; CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 (PcdSmmbaseSwSmi); -#ifndef FSP_FLAG - CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch (); -#endif + // + // This function is shared by both non-FSP and FSP scenarios and always executed unconditionally. + // Since FSP/silicon code should not unconditionally access any + hardcoding flash regions (that region might not be accessible // in unknown platforms), the microcode location searching code should be moved to outside silicon code scope. + // + CpuConfig->MicrocodePatchAddress = 0; } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c index 813b868fcf..c3a8bbf539 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLib.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -196,8 +196,6 @@ DumpSiPolicy ( /** SiInstallPolicyPpi installs SiPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig); ASSERT_EFI_ERROR (Status); + // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So +please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; + SI_POLICY_PPI *SiPolicy; + + SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof + (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPpiDesc->Guid = &gSiPolicyReadyPpiGuid; + SiPolicyPpiDesc->Ppi = NULL; + + SiPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicy + ); + ASSERT_EFI_ERROR(Status); + DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); - DumpSiPolicy (SiPolicyPpi); + DumpSiPolicy (SiPolicy); // - // Install Silicon Policy PPI + // Install Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c index e0d83cb467..e6506a0445 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLibPreMem.c @@ -2,7 +2,7 @@ This file is PeiSiPolicyLib library creates default settings of RC Policy and installs RC Policy PPI. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi; // + // Install Silicon Policy PPI + // + Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So +please update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; + + SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPreMemPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid; + SiPolicyPreMemPpiDesc->Ppi = NULL; + + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPreMemPpi + ); + ASSERT_EFI_ERROR (Status); + + // // Print whole PCH_POLICY_PPI and serial out. // PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ SiPreMemInstallPolicyPpi ( CpuPreMemPrintPolicy (SiPolicyPreMemPpi); // - // Install Silicon Policy PPI + // Install PreMem Silicon Policy Ready PPI // Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c index 0de415ad19..6cbc39c29e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInit.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n")); ASSERT (Policy == NULL); // - // Call SiCreateConfigBlocks to initialize Silicon Policy structure - // and get all Intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreateConfigBlocks (&SiPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); + if (PeiSiDefaultPolicyInitPpi != NULL) { + Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPolicyPpi; } @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiInstallPolicyPpi (SiPolicyPpi); + Status = SiInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c index fd76b4fac3..8e138b1eb2 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInitPreMem.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode for Intel PEI Platform Policy initialization. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( IN OUT VOID *Policy ) { - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI + *PeiPreMemSiDefaultPolicyInitPpi; DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); ASSERT (Policy == NULL); + SiPreMemPolicyPpi = NULL; // - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure - // and get all intel default policy settings. + // Locate Policy init PPI to install default silicon policy // - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + Status = PeiServicesLocatePpi ( + &gSiPreMemDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi + ); ASSERT_EFI_ERROR (Status); - + if (PeiPreMemSiDefaultPolicyInitPpi != NULL) { + Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status == EFI_SUCCESS) { + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } return SiPreMemPolicyPpi; } @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( ) { EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - SiPreMemPolicyPpi = Policy; // - // Install SiPreMemPolicyPpi. + // Install Policy Ready PPI // While installed, RC assumes the Policy is ready and finalized. So please // update and override any setting before calling this function. // - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + Status = SiPreMemInstallPolicyReadyPpi (); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c index 31c7d59d1d..803de0999e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePo +++ licyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiMePolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiPreMemConfig->Header.Revision)); - ASSERT (MePeiPreMemConfig->Header.Revision == ME_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MePeiPreMemConfig->Header.Revision >= + ME_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", MePeiPreMemConfig->HeciTimeouts)); DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", MePeiPreMemConfig->DidInitStat)); @@ -129,7 +129,7 @@ PrintMePeiConfig ( DEBUG_CODE_BEGIN (); DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig->Header.Revision)); - ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION); + ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig->EndOfPostMessage)); DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig->Heci3Enabled)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c index 67fe214d0e..be36468b1e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLi +++ b/DxeSaPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file provide services for DXE phase policy default initialization -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision)); - ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION); + ASSERT (SaPolicy->TableHeader.Header.Revision >= + SA_POLICY_PROTOCOL_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n")); DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio)); DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n")); diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c index 8b3a81a1c4..5c80fca88e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/SaPrintPolicy.c @@ -1,7 +1,7 @@ /** @file This file provides service for PEI phase policy printing -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION); + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= + SI_PREMEM_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision)); - ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION); + ASSERT (MiscPeiPreMemConfig->Header.Revision >= + SA_MISC_PEI_PREMEM_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS)); for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) { DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index])); @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n")); DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Header.Revision)); - ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION); + ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength)); DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBufferSize)); DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSupport)); @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision)); - ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION); + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= + SI_POLICY_REVISION); DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); - ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION); + ASSERT (GtConfig->Header.Revision >= GRAPHICS_PEI_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit)); DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr)); DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n")); DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); - ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION); + ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION); DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER)); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h index 2dc7be45d2..aa88e761b8 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -1,7 +1,7 @@ /** @file This file declares various data structures used in CPU reference code. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define CPU_CAUSE_BY_ASSOCIATION 0x0100 #define CPU_CAUSE_UNSPECIFIED 0x8000 +#define MAX_MICROCODE_PATCH_SIZE 0x20000 + typedef UINT32 CPU_STATE_CHANGE_CAUSE; /// diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h index d2a475591d..23321d6432 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp +++ uPolicyLibrary.h @@ -1,7 +1,7 @@ /** @file Header file for the PeiCpuPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Register/Cpuid.h> #include <Library/PcdLib.h> -#define MAX_MICROCODE_PATCH_SIZE 0x20000 - #endif // _PEI_CPU_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h index 7bd26863b5..2c0387f678 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -1,7 +1,7 @@ /** @file Prototype of the SiPolicyLib library. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( /** SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. - While installed, RC assumes the Policy is ready and finalized. So please update and override - any setting before calling this function. @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( ); /** - SiInstallPolicyPpi installs SiPolicyPpi. + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function. + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ); + +/** + SiInstallPolicyPpi installs SiPolicyPpi. + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance @retval EFI_SUCCESS The policy is installed. @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( ); /** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So + please update and override any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ); + +/** Print out all silicon policy information. @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h new file mode 100644 index 0000000000..b8a526b9b7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPol +++ icyInit.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PreMem silicon +policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI **/ typedef +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy /// +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; +}; + +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; + +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h new file mode 100644 index 0000000000..d620cf29d4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyIni +++ t.h @@ -0,0 +1,36 @@ +/** @file + This file defines the PPI function for installing PostMem silicon +policy + PPI with default settings. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI +PEI_SI_DEFAULT_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI **/ typedef +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy /// +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { + PEI_POLICY_INIT PeiPolicyInit; +}; + +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; + +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf index 1d992cfbbd..47f58d16e9 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic +++ yLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSiPolicyLib library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES [Ppis] -gSiPolicyPpiGuid ## PRODUCES -gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyReadyPpiGuid ## PRODUCES +gSiPolicyReadyPpiGuid ## PRODUCES [Pcd] gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h index c38294cfbe..f2fecee8c6 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPolicyInit.h @@ -1,7 +1,7 @@ /** @file Header file for the PolicyInitPei PEIM. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <PiPei.h> #include <Library/DebugLib.h> #include <Library/MemoryAllocationLib.h> +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h> +#include <Ppi/PeiSiDefaultPolicyInit.h> #include "PeiSiPolicyInit.h" diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf new file mode 100644 index 0000000000..83c909e681 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPostMemSiliconPolicyInitLib.inf @@ -0,0 +1,75 @@ +## @file +# Library functions for Policy Initialization Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +####################################################################### +######### +# +# Defines Section - statements that will be processed to create a Makefile. +# +####################################################################### +######### +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPostMemSiliconPolicyInitLib + FILE_GUID = FA0795E2-BCB3-4627-9FB3-A325548658B4 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +####################################################################### +######### +# +# Sources Section - list of files that are required for the build to succeed. +# +####################################################################### +######### + +[Sources] + PeiPolicyInit.c + PeiPolicyInit.h + +####################################################################### +######### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +####################################################################### +######### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + SiPolicyLib + DebugLib + PeiServicesLib + +[Ppis] + gSiDefaultPolicyInitPpiGuid ## CONSUMES + +[Pcd] + # + # Below PCD may not be consumed by this library but still adding them +here + # to make sure all of them can be built into PcdDataBase. + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type. + # + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate + +[Depex] + gSiDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf similarity index 83% rename from Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf index 7982a5d87f..782e04a476 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P +++ eiPreMemSiliconPolicyInitLib.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ ################################################################################ [Defines] INF_VERSION = 0x00010005 - BASE_NAME = PeiSiliconPolicyInitLib + BASE_NAME = PeiPreMemSiliconPolicyInitLib FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 MODULE_TYPE = BASE VERSION_STRING = 1.0 @@ -34,7 +34,6 @@ [Sources] PeiPolicyInitPreMem.c - PeiPolicyInit.c PeiPolicyInit.h ################################################################################ @@ -53,3 +52,9 @@ SiPolicyLib DebugLib PeiServicesLib + +[Ppis] + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES + +[Depex] + gSiPreMemDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf index 9ffb84fa1e..c11680656d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs +++ p/PeiSiliconPolicyInitLibFsp.inf @@ -1,7 +1,7 @@ ### @file # Library functions for Fsp Policy Initialization Library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES @@ -84,7 +85,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES - + [Ppis] gSiPolicyPpiGuid ## CONSUMES gSiPreMemPolicyPpiGuid ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf index aebd3583bc..1ace9aeb52 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs +++ p/PeiSiliconPolicyInitLibFspAml.inf @@ -72,6 +72,7 @@ MemoryAllocationLib DebugPrintErrorLevelLib FspWrapperApiLib + SiPolicyLib [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec index a613079dd4..e9d3e5f918 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}} +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGuid += {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} ## ## SystemAgent ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h index 4063f800e8..b835155c68 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/G +++ raphicsPeiConfig.h @@ -1,7 +1,7 @@ /** @file Policy definition for Internal Graphics Config Block (PostMem) -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ typedef struct { CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b> + UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b> + /** + Offset 28:3 + CdClock Frequency select\n + 0 = 337.5 Mhz, 1 = 450 Mhz,\n + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n + **/ + UINT32 CdClock : 3; UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable - UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future use + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable + UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b> + UINT32 RsvdBits0 : 16; ///< Offser 28:16 :Reserved for future use VOID* LogoPtr; ///< Offset 32 Address of Logo to be displayed in PEI UINT32 LogoSize; ///< Offset 36 Logo Size VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..c7454bd4a5 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ CpuMailboxLib SiConfigBlockLib RngLib SmbusLib +PchCycleDecodingLib [Packages] MdePkg/MdePkg.dec -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI Chiu, Chasel 2019-06-03 16:46 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel @ 2019-06-03 16:46 ` Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 0:43 ` Chaganty, Rangasai V 1 sibling, 2 replies; 9+ messages in thread From: Chiu, Chasel @ 2019-06-03 16:46 UTC (permalink / raw) To: devel; +Cc: Chasel, Chiu, Michael A Kubacki, Sai Chaganty, Nate DeSimone From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 Basing on FSP modes the Fsp*WrapperPeim may not have dependency on PolicyPpi, instead it should report FSP-M or FPS-S FV to dispatcher so FSP can produce DefaultPolicyInit PPIs. A PEI policy update library was created to update policy PPI basing on board configuration. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 564 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 700 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..5cc7c03c61 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,564 @@ +/** @file + Provides silicon policy update library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <ConfigBlock.h> +#include <SaPolicyCommon.h> +#include <CpuPolicyCommon.h> +#include <PchPreMemPolicyCommon.h> +#include <Pi/PiFirmwareFile.h> +#include <Register/Cpuid.h> +#include <PchHsioPtssTables.h> +#include <Library/PchInfoLib.h> +#include <Library/SiliconPolicyUpdateLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/ConfigBlockLib.h> +#include <Library/PeiLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/CpuPlatformLib.h> +#include <Library/PchHsioLib.h> +#include <Library/PchPcieRpLib.h> +#include <Library/MmPciLib.h> +#include <Library/IoLib.h> + +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, + and output points to the next patch address found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData == NULL) { + *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); + return EFI_NOT_FOUND; + } + + TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize == 0) { + TotalSize = 2048; + } + + *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); + if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer = NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision = GetCpuUcodeRevision (); + MicrocodeData = NULL; + while (TRUE) { + /// + /// Find the next patch address + /// + Status = RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); + + if (Status != EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; + } + + /// + /// Check that microcode patch size is <= 128K max size, + /// then copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); + if (MicrocodeBuffer != NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; +} + +/** + Update HSIO policy per board. + + @param[in] Policy - Policy PPI pointer (caller should ensure it is valid pointer) + +**/ +VOID +InstallPlatformHsioPtssTable ( + IN VOID *Policy + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); + MaxPciePorts = GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + // + //Populate PCIe topology based on lane configuration + // + for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); + } + for (Index = 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); + } + // + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + // + PtssTables = SpecificPtssTables; + TableSize = SpecificTableSize; + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 1b: PCIe + // + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 2: BoardId is unknown, Topology is known/unknown + // + if (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Update PreMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VOID *Buffer; + UINT8 SpdAddressTable[4]; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); + + if (Policy != NULL) { + SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0); + SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1); + SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2); + SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3); + + MiscPeiPreMemConfig = NULL; + Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + if (MiscPeiPreMemConfig != NULL) { + // + // Pass board specific SpdAddressTable to policy + // + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4)); + } + MemConfigNoCrc = NULL; + Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc != NULL) { + MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize); + + // + // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer. + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy. + // + if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12); + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10); + } + } + // + // Update PCD policy + // + InstallPlatformHsioPtssTable (Policy); + } + + return Policy; +} + +/** + Update PostMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + + GtConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig); + ASSERT_EFI_ERROR (Status); + + if (GtConfig != NULL) { + // + // Always enable PEI graphics initialization. + // + GtConfig->PeiGraphicsPeimInit = 1; + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr = MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr = MemBuffer; + GtConfig->LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr = 0; + GtConfig->LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize)); + } + + CpuConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&CpuConfig); + ASSERT_EFI_ERROR (Status); + + if (CpuConfig != NULL) { + CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch (); + } + return Policy; +} + +/** + Update late phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..1b0611e57a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -233,6 +233,12 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf !endif } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf @@ -244,6 +250,26 @@ # NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf } +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-M dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspmWrapper report FSP-M FV to dispatcher. + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + <LibraryClasses> + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf { + <LibraryClasses> + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf + } +!endif + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { <LibraryClasses> !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE @@ -253,11 +279,35 @@ !endif } +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-S dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspsWrapper report FSP-S FV to dispatcher. + # + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + <LibraryClasses> + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf { + <LibraryClasses> + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf + } +!endif # # Security diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..aa163ebf08 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,86 @@ +### @file +# Component information file for silicon policy update library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyUpdateLib + FILE_GUID = 14F5D83D-76A5-4241-BEC5-987E70E233D5 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + BaseMemoryLib + MemoryAllocationLib + PeiLib + CpuPlatformLib + PchPcieRpLib + PchInfoLib + MmPciLib + IoLib + PchHsioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSiliconPolicyUpdateLib.c + +[Guids] + gMemoryConfigNoCrcGuid + gTianoLogoGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel @ 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 0:43 ` Chaganty, Rangasai V 1 sibling, 0 replies; 9+ messages in thread From: Nate DeSimone @ 2019-06-06 9:43 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Chaganty, Rangasai V Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Monday, June 3, 2019 9:47 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 Basing on FSP modes the Fsp*WrapperPeim may not have dependency on PolicyPpi, instead it should report FSP-M or FPS-S FV to dispatcher so FSP can produce DefaultPolicyInit PPIs. A PEI policy update library was created to update policy PPI basing on board configuration. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 564 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 700 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..5cc7c03c61 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,564 @@ +/** @file + Provides silicon policy update library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <ConfigBlock.h> +#include <SaPolicyCommon.h> +#include <CpuPolicyCommon.h> +#include <PchPreMemPolicyCommon.h> +#include <Pi/PiFirmwareFile.h> +#include <Register/Cpuid.h> +#include <PchHsioPtssTables.h> +#include <Library/PchInfoLib.h> +#include <Library/SiliconPolicyUpdateLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/ConfigBlockLib.h> +#include <Library/PeiLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> #include +<Library/CpuPlatformLib.h> #include <Library/PchHsioLib.h> #include +<Library/PchPcieRpLib.h> #include <Library/MmPciLib.h> #include +<Library/IoLib.h> + +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, + and output points to the next patch address found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData == NULL) { + *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); + return EFI_NOT_FOUND; + } + + TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize == 0) { + TotalSize = 2048; + } + + *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); + if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer = NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision = GetCpuUcodeRevision (); MicrocodeData = NULL; while + (TRUE) { + /// + /// Find the next patch address + /// + Status = RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); + + if (Status != EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + + /// + /// Check that microcode patch size is <= 128K max size, /// then + copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); + if (MicrocodeBuffer != NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max +allowed size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + +/** + Update HSIO policy per board. + + @param[in] Policy - Policy PPI pointer (caller should ensure it is + valid pointer) + +**/ +VOID +InstallPlatformHsioPtssTable ( + IN VOID *Policy + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) + &HsioPciePreMemConfig); ASSERT_EFI_ERROR (Status); Status = + GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) + &HsioSataPreMemConfig); ASSERT_EFI_ERROR (Status); + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); MaxPciePorts = + GetPchMaxPciePortNum (); ZeroMem (PcieTopologyReal, sizeof + (PcieTopologyReal)); // //Populate PCIe topology based on lane + configuration // for (PciePort = 0; PciePort < MaxPciePorts; + PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", + PciePort, PcieControllerCfg)); } for (Index = 0; Index < + MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", + Index, PcieTopologyReal[Index])); } // //Case 1: BoardId is known, + Topology is known/unknown //Case 1a: SATA // PtssTables = + SpecificPtssTables; TableSize = SpecificTableSize; for (Index = 0; + Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 1b: PCIe + // + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 2: BoardId is unknown, Topology is known/unknown // if + (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be + applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Update PreMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VOID *Buffer; + UINT8 SpdAddressTable[4]; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); + + if (Policy != NULL) { + SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0); + SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1); + SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2); + SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3); + + MiscPeiPreMemConfig = NULL; + Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + if (MiscPeiPreMemConfig != NULL) { + // + // Pass board specific SpdAddressTable to policy + // + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4)); + } + MemConfigNoCrc = NULL; + Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc != NULL) { + MemConfigNoCrc->PlatformMemorySize = PcdGet32 + (PcdPeiMinMemorySize); + + // + // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer. + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy. + // + if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12); + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10); + } + } + // + // Update PCD policy + // + InstallPlatformHsioPtssTable (Policy); } + + return Policy; +} + +/** + Update PostMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + + GtConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, + (VOID *)&GtConfig); ASSERT_EFI_ERROR (Status); + + if (GtConfig != NULL) { + // + // Always enable PEI graphics initialization. + // + GtConfig->PeiGraphicsPeimInit = 1; + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr = MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr = MemBuffer; + GtConfig->LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr = 0; + GtConfig->LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", + GtConfig->LogoSize)); } + + CpuConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID + *)&CpuConfig); ASSERT_EFI_ERROR (Status); + + if (CpuConfig != NULL) { + CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch +(); + } + return Policy; +} + +/** + Update late phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..1b0611e57a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -233,6 +233,12 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf !endif } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf @@ -244,6 +250,26 @@ # NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf } +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-M +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspmWrapper report FSP-M FV to dispatcher. + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + <LibraryClasses> + +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf { + <LibraryClasses> + +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPreMemSiliconPolicyInitLib.inf + } +!endif + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { <LibraryClasses> !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE @@ -253,11 +279,35 @@ !endif } +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-S +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspsWrapper report FSP-S FV to dispatcher. + # + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + <LibraryClasses> + +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf { + <LibraryClasses> + +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPostMemSiliconPolicyInitLib.inf + } +!endif # # Security diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..aa163ebf08 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,86 @@ +### @file +# Component information file for silicon policy update library # # +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyUpdateLib + FILE_GUID = 14F5D83D-76A5-4241-BEC5-987E70E233D5 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + BaseMemoryLib + MemoryAllocationLib + PeiLib + CpuPlatformLib + PchPcieRpLib + PchInfoLib + MmPciLib + IoLib + PchHsioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSiliconPolicyUpdateLib.c + +[Guids] + gMemoryConfigNoCrcGuid + gTianoLogoGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. 2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone @ 2019-06-11 0:43 ` Chaganty, Rangasai V 1 sibling, 0 replies; 9+ messages in thread From: Chaganty, Rangasai V @ 2019-06-11 0:43 UTC (permalink / raw) To: Chiu, Chasel, devel@edk2.groups.io Cc: Kubacki, Michael A, Desimone, Nathaniel L Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Monday, June 03, 2019 9:47 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. From: "Chasel, Chiu" <chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 Basing on FSP modes the Fsp*WrapperPeim may not have dependency on PolicyPpi, instead it should report FSP-M or FPS-S FV to dispatcher so FSP can produce DefaultPolicyInit PPIs. A PEI policy update library was created to update policy PPI basing on board configuration. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 564 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 700 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..5cc7c03c61 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,564 @@ +/** @file + Provides silicon policy update library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <ConfigBlock.h> +#include <SaPolicyCommon.h> +#include <CpuPolicyCommon.h> +#include <PchPreMemPolicyCommon.h> +#include <Pi/PiFirmwareFile.h> +#include <Register/Cpuid.h> +#include <PchHsioPtssTables.h> +#include <Library/PchInfoLib.h> +#include <Library/SiliconPolicyUpdateLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/ConfigBlockLib.h> +#include <Library/PeiLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> #include +<Library/CpuPlatformLib.h> #include <Library/PchHsioLib.h> #include +<Library/PchPcieRpLib.h> #include <Library/MmPciLib.h> #include +<Library/IoLib.h> + +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, + and output points to the next patch address found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData == NULL) { + *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); + return EFI_NOT_FOUND; + } + + TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize == 0) { + TotalSize = 2048; + } + + *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); + if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer = NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision = GetCpuUcodeRevision (); MicrocodeData = NULL; while + (TRUE) { + /// + /// Find the next patch address + /// + Status = RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); + + if (Status != EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + + /// + /// Check that microcode patch size is <= 128K max size, /// then + copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); + if (MicrocodeBuffer != NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max +allowed size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + +/** + Update HSIO policy per board. + + @param[in] Policy - Policy PPI pointer (caller should ensure it is + valid pointer) + +**/ +VOID +InstallPlatformHsioPtssTable ( + IN VOID *Policy + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) + &HsioPciePreMemConfig); ASSERT_EFI_ERROR (Status); Status = + GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) + &HsioSataPreMemConfig); ASSERT_EFI_ERROR (Status); + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); MaxPciePorts = + GetPchMaxPciePortNum (); ZeroMem (PcieTopologyReal, sizeof + (PcieTopologyReal)); // //Populate PCIe topology based on lane + configuration // for (PciePort = 0; PciePort < MaxPciePorts; + PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", + PciePort, PcieControllerCfg)); } for (Index = 0; Index < + MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", + Index, PcieTopologyReal[Index])); } // //Case 1: BoardId is known, + Topology is known/unknown //Case 1a: SATA // PtssTables = + SpecificPtssTables; TableSize = SpecificTableSize; for (Index = 0; + Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 1b: PCIe + // + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 2: BoardId is unknown, Topology is known/unknown // if + (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be + applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Update PreMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VOID *Buffer; + UINT8 SpdAddressTable[4]; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); + + if (Policy != NULL) { + SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0); + SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1); + SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2); + SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3); + + MiscPeiPreMemConfig = NULL; + Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + if (MiscPeiPreMemConfig != NULL) { + // + // Pass board specific SpdAddressTable to policy + // + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4)); + } + MemConfigNoCrc = NULL; + Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc != NULL) { + MemConfigNoCrc->PlatformMemorySize = PcdGet32 + (PcdPeiMinMemorySize); + + // + // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer. + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy. + // + if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12); + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10); + } + } + // + // Update PCD policy + // + InstallPlatformHsioPtssTable (Policy); } + + return Policy; +} + +/** + Update PostMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + + GtConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, + (VOID *)&GtConfig); ASSERT_EFI_ERROR (Status); + + if (GtConfig != NULL) { + // + // Always enable PEI graphics initialization. + // + GtConfig->PeiGraphicsPeimInit = 1; + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr = MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr = MemBuffer; + GtConfig->LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr = 0; + GtConfig->LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", + GtConfig->LogoSize)); } + + CpuConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID + *)&CpuConfig); ASSERT_EFI_ERROR (Status); + + if (CpuConfig != NULL) { + CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch +(); + } + return Policy; +} + +/** + Update late phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..1b0611e57a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -233,6 +233,12 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf !endif } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf @@ -244,6 +250,26 @@ # NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf } +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-M +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspmWrapper report FSP-M FV to dispatcher. + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + <LibraryClasses> + +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf { + <LibraryClasses> + +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPreMemSiliconPolicyInitLib.inf + } +!endif + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { <LibraryClasses> !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE @@ -253,11 +279,35 @@ !endif } +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { <LibraryClasses> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-S +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspsWrapper report FSP-S FV to dispatcher. + # + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + <LibraryClasses> + +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf { + <LibraryClasses> + +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPostMemSiliconPolicyInitLib.inf + } +!endif # # Security diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..aa163ebf08 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,86 @@ +### @file +# Component information file for silicon policy update library # # +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyUpdateLib + FILE_GUID = 14F5D83D-76A5-4241-BEC5-987E70E233D5 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + BaseMemoryLib + MemoryAllocationLib + PeiLib + CpuPlatformLib + PchPcieRpLib + PchInfoLib + MmPciLib + IoLib + PchHsioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSiliconPolicyUpdateLib.c + +[Guids] + gMemoryConfigNoCrcGuid + gTianoLogoGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 -- 2.13.3.windows.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-06-11 5:13 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-06-03 16:46 [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI Chiu, Chasel 2019-06-03 16:46 ` [PATCH 1/2] KabylakeSiliconPkg: " Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 2:11 ` [edk2-devel] " Ni, Ray 2019-06-11 5:13 ` Chiu, Chasel 2019-06-11 0:37 ` Chaganty, Rangasai V 2019-06-03 16:46 ` [PATCH 2/2] KabylakeOpenBoardPkg: " Chiu, Chasel 2019-06-06 9:43 ` Nate DeSimone 2019-06-11 0:43 ` Chaganty, Rangasai V
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox