From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: mateusz.albecki@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Wed, 26 Jun 2019 06:10:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2019 06:10:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,420,1557212400"; d="scan'208";a="155862718" Received: from gklab-27-32.ger.corp.intel.com ([10.102.10.44]) by orsmga008.jf.intel.com with ESMTP; 26 Jun 2019 06:10:34 -0700 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu Subject: [PATCH v4 1/2] MdeModulePkg/SdMmcOverride: Add GetOperatingParam notify phase Date: Wed, 26 Jun 2019 15:10:02 +0200 Message-Id: <20190626131003.3088-2-mateusz.albecki@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20190626131003.3088-1-mateusz.albecki@intel.com> References: <20190626131003.3088-1-mateusz.albecki@intel.com> https://bugzilla.tianocore.org/show_bug.cgi?id=1882 The new notify phase allows platform to configure additional bus paramters in addition to parameters that can already be configured with capability override. Specifically we allow to configure bus width, clock frequency and driver strength. If platform doesn't wish to configure some of the parameters it can left it on default values and driver will assume it's standard behavior with respect to those parameters. The definition of the SD_MMC_BUS_MODE has been extended to incorporate SD card default speed and high speed. Cc: Hao A Wu Signed-off-by: Mateusz Albecki --- MdeModulePkg/Include/Protocol/SdMmcOverride.h | 60 +++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h index 9c8bf37efd..d44027260a 100644 --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h @@ -16,19 +16,66 @@ #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \ { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } } -#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x2 +#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3 typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE; -// -// Bus timing modes -// +#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8 +#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32 +#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8 + +typedef enum { + SdDriverStrengthTypeB = 0, + SdDriverStrengthTypeA, + SdDriverStrengthTypeC, + SdDriverStrengthTypeD, + SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE +} SD_DRIVER_STRENGTH_TYPE; + typedef enum { + EmmcDriverStrengthType0 = 0, + EmmcDriverStrengthType1, + EmmcDriverStrengthType2, + EmmcDriverStrengthType3, + EmmcDriverStrengthType4, + EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE +} EMMC_DRIVER_STRENGTH_TYPE; + +typedef union { + SD_DRIVER_STRENGTH_TYPE Sd; + EMMC_DRIVER_STRENGTH_TYPE Emmc; +} EDKII_SD_MMC_DRIVER_STRENGTH; + +typedef struct { + // + // The target width of the bus. If user tells driver to ignore it + // or specifies unsupported width driver will choose highest supported + // bus width for a given mode. + // + UINT8 BusWidth; + // + // The target clock frequency of the bus in MHz. If user tells driver to ignore + // it or specifies unsupported frequency driver will choose highest supported + // clock frequency for a given mode. + // + UINT32 ClockFreq; + // + // The target driver strength of the bus. If user tells driver to + // ignore it or specifies unsupported driver strength, driver will + // default to Type0 for eMMC cards and TypeB for SD cards. Driver strength + // setting is only considered if chosen bus timing supports them. + // + EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength; +} EDKII_SD_MMC_OPERATING_PARAMETERS; + +typedef enum { + SdMmcSdDs, + SdMmcSdHs, SdMmcUhsSdr12, SdMmcUhsSdr25, SdMmcUhsSdr50, - SdMmcUhsSdr104, SdMmcUhsDdr50, + SdMmcUhsSdr104, SdMmcMmcLegacy, SdMmcMmcHsSdr, SdMmcMmcHsDdr, @@ -43,10 +90,10 @@ typedef enum { EdkiiSdMmcInitHostPost, EdkiiSdMmcUhsSignaling, EdkiiSdMmcSwitchClockFreqPost, + EdkiiSdMmcGetOperatingParam } EDKII_SD_MMC_PHASE_TYPE; /** - Override function for SDHCI capability bits @param[in] ControllerHandle The EFI_HANDLE of the controller. @@ -70,7 +117,6 @@ EFI_STATUS ); /** - Override function for SDHCI controller operations @param[in] ControllerHandle The EFI_HANDLE of the controller. -- 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.