From: "Ni, Ray" <ray.ni@intel.com>
To: devel@edk2.groups.io
Subject: [PATCH 0/3] Enable 5 level paging when CPU supports
Date: Fri, 28 Jun 2019 14:46:57 +0800 [thread overview]
Message-ID: <20190628064700.549472-1-ray.ni@intel.com> (raw)
Ray Ni (3):
UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM
MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
MdePkg/Include/Library/BaseLib.h | 3 +-
.../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 20 +-
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 300 ++++++-----
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 483 ++++++++++++------
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 12 +
.../PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 72 ++-
6 files changed, 575 insertions(+), 315 deletions(-)
--
2.21.0.windows.1
next reply other threads:[~2019-06-28 6:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 6:46 Ni, Ray [this message]
2019-06-28 6:46 ` [PATCH 1/3] UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM Ni, Ray
2019-06-28 6:46 ` [PATCH 2/3] MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging Ni, Ray
2019-06-28 6:47 ` [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports Ni, Ray
2019-06-28 7:18 ` [edk2-devel] " Yao, Jiewen
2019-06-28 7:27 ` Ni, Ray
2019-06-28 15:32 ` Laszlo Ersek
2019-06-28 15:36 ` Laszlo Ersek
2019-07-01 12:44 ` Laszlo Ersek
2019-07-02 14:44 ` Ni, Ray
2019-07-02 15:18 ` Laszlo Ersek
2019-07-02 15:20 ` Laszlo Ersek
2019-07-03 10:08 ` Laszlo Ersek
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