From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: ray.ni@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Thu, 27 Jun 2019 23:47:26 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2019 23:47:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,426,1557212400"; d="scan'208";a="189342985" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by fmsmga002.fm.intel.com with ESMTP; 27 Jun 2019 23:47:25 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Subject: [PATCH 0/3] Enable 5 level paging when CPU supports Date: Fri, 28 Jun 2019 14:46:57 +0800 Message-Id: <20190628064700.549472-1-ray.ni@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Ray Ni (3): UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports MdePkg/Include/Library/BaseLib.h | 3 +- .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 20 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 300 ++++++----- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 483 ++++++++++++------ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 12 + .../PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 72 ++- 6 files changed, 575 insertions(+), 315 deletions(-) -- 2.21.0.windows.1