Add the initial version of the binaries required to build Vlv2TbltDevicePkg in the edk2-platform repository Cc: Zailiang Sun Cc: Yi Qian Signed-off-by: Michael D Kinney --- .../RELEASE_VS2008x86/IA32/IntelGopDriver.efi | Bin 0 -> 60192 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../RELEASE_VS2008x86/X64/IntelGopDriver.efi | Bin 0 -> 75008 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../GOP/7.2.1011/VBT/MNW2/Vbt.bin | Bin 0 -> 4096 bytes .../GOP/7.2.1011/VBT/MNW2/vbt.bsf | 9216 +++++++++++ .../IA32DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf | 137 + .../IA32DEBUG/IA32/DigitalThermalSensor.depex | 1 + .../IA32DEBUG/IA32/DigitalThermalSensor.efi | Bin 0 -> 14848 bytes .../IA32DEBUG/IA32/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.efi | Bin 0 -> 12704 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.inf | 219 + .../IA32DEBUG/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 25088 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.inf | 265 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.efi | Bin 0 -> 17984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf | 247 + .../IA32DEBUG/IA32/MemoryInit.depex | 1 + .../IA32DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../IA32DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32DEBUG/IA32/PchBiosWriteProtect.depex | 1 + .../IA32DEBUG/IA32/PchBiosWriteProtect.efi | Bin 0 -> 11264 bytes .../IA32DEBUG/IA32/PchBiosWriteProtect.inf | 130 + .../IA32DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../IA32DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../IA32DEBUG/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/PchInitDxe.efi | Bin 0 -> 102496 bytes .../IA32DEBUG/IA32/PchInitDxe.inf | 278 + .../IA32DEBUG/IA32/PchInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../IA32DEBUG/IA32/PchInitPeim.inf | 150 + .../IA32DEBUG/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/PchInitSmm.efi | Bin 0 -> 35840 bytes .../IA32DEBUG/IA32/PchInitSmm.inf | 290 + .../IA32DEBUG/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32DEBUG/IA32/PchPcieSmm.efi | Bin 0 -> 26112 bytes .../IA32DEBUG/IA32/PchPcieSmm.inf | 251 + .../IA32DEBUG/IA32/PchPolicyInitDxe.depex | 1 + .../IA32DEBUG/IA32/PchPolicyInitDxe.efi | Bin 0 -> 9440 bytes .../IA32DEBUG/IA32/PchPolicyInitDxe.inf | 123 + .../IA32DEBUG/IA32/PchReset.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.efi | Bin 0 -> 12288 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.inf | 137 + .../IA32DEBUG/IA32/PchS3SupportDxe.depex | 1 + .../IA32DEBUG/IA32/PchS3SupportDxe.efi | Bin 0 -> 25760 bytes .../IA32DEBUG/IA32/PchS3SupportDxe.inf | 257 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../IA32DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../IA32DEBUG/IA32/PchSmbusDxe.depex | 1 + .../IA32DEBUG/IA32/PchSmbusDxe.efi | Bin 0 -> 15552 bytes .../IA32DEBUG/IA32/PchSmbusDxe.inf | 214 + .../IA32DEBUG/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.efi | Bin 0 -> 24576 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.inf | 181 + .../IA32DEBUG/IA32/PchSpiPeim.depex | 1 + .../IA32DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../IA32DEBUG/IA32/PchSpiPeim.inf | 139 + .../IA32DEBUG/IA32/PchSpiRuntime.depex | 1 + .../IA32DEBUG/IA32/PchSpiRuntime.efi | Bin 0 -> 23552 bytes .../IA32DEBUG/IA32/PchSpiRuntime.inf | 258 + .../IA32DEBUG/IA32/PchSpiSmm.depex | 1 + .../IA32DEBUG/IA32/PchSpiSmm.efi | Bin 0 -> 24064 bytes .../IA32DEBUG/IA32/PchSpiSmm.inf | 251 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.inf | 137 + .../IA32DEBUG/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32DEBUG/IA32/PciHostBridge.efi | Bin 0 -> 22336 bytes .../IA32DEBUG/IA32/PciHostBridge.inf | 254 + .../IA32DEBUG/IA32/PeiSmmAccess.depex | 1 + .../IA32DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../IA32DEBUG/IA32/PeiSmmAccess.inf | 132 + .../IA32DEBUG/IA32/PeiSmmControl.depex | 1 + .../IA32DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../IA32DEBUG/IA32/PeiSmmControl.inf | 110 + .../IA32DEBUG/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.efi | Bin 0 -> 17632 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.inf | 227 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.efi | Bin 0 -> 17472 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.inf | 207 + .../IA32DEBUG/IA32/PowerManagement2.depex | 1 + .../IA32DEBUG/IA32/PowerManagement2.efi | Bin 0 -> 36352 bytes .../IA32DEBUG/IA32/PowerManagement2.inf | 270 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32DEBUG/IA32/SataController.efi | Bin 0 -> 12128 bytes .../IA32DEBUG/IA32/SataController.inf | 204 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.inf | 130 + .../IA32DEBUG/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32DEBUG/IA32/SmmAccess.efi | Bin 0 -> 10336 bytes .../IA32DEBUG/IA32/SmmAccess.inf | 210 + .../IA32DEBUG/IA32/SmmControl.depex | 1 + .../IA32DEBUG/IA32/SmmControl.efi | Bin 0 -> 11776 bytes .../IA32DEBUG/IA32/SmmControl.inf | 129 + .../IA32DEBUG/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/VlvInitDxe.efi | Bin 0 -> 26656 bytes .../IA32DEBUG/IA32/VlvInitDxe.inf | 259 + .../IA32DEBUG/IA32/VlvInitPeim.depex | 1 + .../IA32DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../IA32DEBUG/IA32/VlvInitPeim.inf | 116 + .../IA32RELEASE/IA32/CpuPeim.depex | 1 + .../IA32RELEASE/IA32/CpuPeim.efi | Bin 0 -> 6080 bytes .../IA32RELEASE/IA32/CpuPeim.inf | 123 + .../IA32/DigitalThermalSensor.depex | 1 + .../IA32RELEASE/IA32/DigitalThermalSensor.efi | Bin 0 -> 6144 bytes .../IA32RELEASE/IA32/DigitalThermalSensor.inf | 182 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.efi | Bin 0 -> 3872 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf | 213 + .../IA32RELEASE/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 9216 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.inf | 259 + .../IA32RELEASE/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.efi | Bin 0 -> 6144 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf | 241 + .../IA32RELEASE/IA32/MemoryInit.depex | 1 + .../IA32RELEASE/IA32/MemoryInit.efi | Bin 0 -> 93888 bytes .../IA32RELEASE/IA32/MemoryInit.inf | 196 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32/PchBiosWriteProtect.depex | 1 + .../IA32RELEASE/IA32/PchBiosWriteProtect.efi | Bin 0 -> 2560 bytes .../IA32RELEASE/IA32/PchBiosWriteProtect.inf | 121 + .../IA32RELEASE/IA32/PchEarlyInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchEarlyInitPeim.efi | Bin 0 -> 14752 bytes .../IA32RELEASE/IA32/PchEarlyInitPeim.inf | 97 + .../IA32RELEASE/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/PchInitDxe.efi | Bin 0 -> 61536 bytes .../IA32RELEASE/IA32/PchInitDxe.inf | 272 + .../IA32RELEASE/IA32/PchInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchInitPeim.efi | Bin 0 -> 11776 bytes .../IA32RELEASE/IA32/PchInitPeim.inf | 136 + .../IA32RELEASE/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/PchInitSmm.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PchInitSmm.inf | 284 + .../IA32RELEASE/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32RELEASE/IA32/PchPcieSmm.efi | Bin 0 -> 11264 bytes .../IA32RELEASE/IA32/PchPcieSmm.inf | 245 + .../IA32RELEASE/IA32/PchPolicyInitDxe.depex | 1 + .../IA32RELEASE/IA32/PchPolicyInitDxe.efi | Bin 0 -> 2368 bytes .../IA32RELEASE/IA32/PchPolicyInitDxe.inf | 109 + .../IA32RELEASE/IA32/PchReset.depex | 1 + .../IA32RELEASE/IA32/PchReset.efi | Bin 0 -> 3584 bytes .../IA32RELEASE/IA32/PchReset.inf | 130 + .../IA32RELEASE/IA32/PchS3SupportDxe.depex | 1 + .../IA32RELEASE/IA32/PchS3SupportDxe.efi | Bin 0 -> 13472 bytes .../IA32RELEASE/IA32/PchS3SupportDxe.inf | 251 + .../IA32/PchSmbusArpDisabled.depex | 1 + .../IA32RELEASE/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 3136 bytes .../IA32RELEASE/IA32/PchSmbusArpDisabled.inf | 130 + .../IA32RELEASE/IA32/PchSmbusDxe.depex | 1 + .../IA32RELEASE/IA32/PchSmbusDxe.efi | Bin 0 -> 4832 bytes .../IA32RELEASE/IA32/PchSmbusDxe.inf | 206 + .../IA32RELEASE/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.efi | Bin 0 -> 12288 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.inf | 175 + .../IA32RELEASE/IA32/PchSpiPeim.depex | 1 + .../IA32RELEASE/IA32/PchSpiPeim.efi | Bin 0 -> 4384 bytes .../IA32RELEASE/IA32/PchSpiPeim.inf | 125 + .../IA32RELEASE/IA32/PchSpiRuntime.depex | 1 + .../IA32RELEASE/IA32/PchSpiRuntime.efi | Bin 0 -> 10240 bytes .../IA32RELEASE/IA32/PchSpiRuntime.inf | 252 + .../IA32RELEASE/IA32/PchSpiSmm.depex | 1 + .../IA32RELEASE/IA32/PchSpiSmm.efi | Bin 0 -> 9728 bytes .../IA32RELEASE/IA32/PchSpiSmm.inf | 245 + .../IA32RELEASE/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.efi | Bin 0 -> 1344 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.inf | 124 + .../IA32RELEASE/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32RELEASE/IA32/PciHostBridge.efi | Bin 0 -> 9792 bytes .../IA32RELEASE/IA32/PciHostBridge.inf | 248 + .../IA32RELEASE/IA32/PeiSmmAccess.depex | 1 + .../IA32RELEASE/IA32/PeiSmmAccess.efi | Bin 0 -> 1664 bytes .../IA32RELEASE/IA32/PeiSmmAccess.inf | 119 + .../IA32RELEASE/IA32/PeiSmmControl.depex | 1 + .../IA32RELEASE/IA32/PeiSmmControl.efi | Bin 0 -> 960 bytes .../IA32RELEASE/IA32/PeiSmmControl.inf | 95 + .../IA32RELEASE/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.efi | Bin 0 -> 8064 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.inf | 216 + .../IA32RELEASE/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.efi | Bin 0 -> 9664 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.inf | 200 + .../IA32RELEASE/IA32/PowerManagement2.depex | 1 + .../IA32RELEASE/IA32/PowerManagement2.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PowerManagement2.inf | 264 + .../IA32RELEASE/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/SataController.efi | Bin 0 -> 3264 bytes .../IA32RELEASE/IA32/SataController.inf | 195 + .../IA32RELEASE/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi | Bin 0 -> 1856 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf | 101 + .../IA32RELEASE/IA32/SecCore.efi | Bin 0 -> 8000 bytes .../IA32RELEASE/IA32/SecCore.inf | 152 + .../IA32RELEASE/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32RELEASE/IA32/SmmAccess.efi | Bin 0 -> 1984 bytes .../IA32RELEASE/IA32/SmmAccess.inf | 198 + .../IA32RELEASE/IA32/SmmControl.depex | 1 + .../IA32RELEASE/IA32/SmmControl.efi | Bin 0 -> 3072 bytes .../IA32RELEASE/IA32/SmmControl.inf | 122 + .../IA32RELEASE/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/VlvInitDxe.efi | Bin 0 -> 16640 bytes .../IA32RELEASE/IA32/VlvInitDxe.inf | 253 + .../IA32RELEASE/IA32/VlvInitPeim.depex | 1 + .../IA32RELEASE/IA32/VlvInitPeim.efi | Bin 0 -> 3104 bytes .../IA32RELEASE/IA32/VlvInitPeim.inf | 101 + .../Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h | 72 + .../Vlv2SocBinPkg/Microcode/M0130673321.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130678806.inc | 12800 +++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679901.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679906.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679907.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M023067221D.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0F30679909.inc | 13056 ++++++++++++++++ .../Microcode/MicrocodeUpdates.inf | 51 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/I211PcieUndiDxe/X64/E7006X3.EFI | Bin 0 -> 341536 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/IA32/RtkUndiDxe.efi | Bin 0 -> 78368 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/X64/RtkUndiDxe.efi | Bin 0 -> 92064 bytes Silicon/Intel/Vlv2SocBinPkg/Vlv2SocBinPkg.dec | 36 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.inf | 137 + .../X64DEBUG/IA32/MemoryInit.depex | 1 + .../X64DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../X64DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../X64DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../X64DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../X64DEBUG/IA32/PchInitPeim.depex | 1 + .../X64DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../X64DEBUG/IA32/PchInitPeim.inf | 150 + .../X64DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../X64DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../X64DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../X64DEBUG/IA32/PchSpiPeim.depex | 1 + .../X64DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../X64DEBUG/IA32/PchSpiPeim.inf | 139 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.inf | 137 + .../X64DEBUG/IA32/PeiSmmAccess.depex | 1 + .../X64DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../X64DEBUG/IA32/PeiSmmAccess.inf | 132 + .../X64DEBUG/IA32/PeiSmmControl.depex | 1 + .../X64DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../X64DEBUG/IA32/PeiSmmControl.inf | 110 + .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.inf | 130 + .../X64DEBUG/IA32/VlvInitPeim.depex | 1 + .../X64DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../X64DEBUG/IA32/VlvInitPeim.inf | 116 + .../X64DEBUG/X64/DigitalThermalSensor.depex | 1 + .../X64DEBUG/X64/DigitalThermalSensor.efi | Bin 0 -> 32768 bytes .../X64DEBUG/X64/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/X64DEBUG/X64/Dptf.depex | Bin 0 -> 108 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.efi | Bin 0 -> 29120 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.inf | 219 + .../X64DEBUG/X64/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../X64DEBUG/X64/GraphicDxeInitSmm.efi | Bin 0 -> 54272 bytes .../X64DEBUG/X64/GraphicDxeInitSmm.inf | 265 + .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.efi | Bin 0 -> 39328 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.inf | 247 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64DEBUG/X64/PchBiosWriteProtect.depex | 1 + .../X64DEBUG/X64/PchBiosWriteProtect.efi | Bin 0 -> 26624 bytes .../X64DEBUG/X64/PchBiosWriteProtect.inf | 130 + .../X64DEBUG/X64/PchInitDxe.depex | Bin 0 -> 126 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.efi | Bin 0 -> 176256 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf | 278 + .../X64DEBUG/X64/PchInitSmm.depex | Bin 0 -> 162 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.efi | Bin 0 -> 67072 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.inf | 290 + .../X64DEBUG/X64/PchPcieSmm.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.efi | Bin 0 -> 55808 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.inf | 251 + .../X64DEBUG/X64/PchPolicyInitDxe.depex | 1 + .../X64DEBUG/X64/PchPolicyInitDxe.efi | Bin 0 -> 23616 bytes .../X64DEBUG/X64/PchPolicyInitDxe.inf | 123 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.efi | Bin 0 -> 29184 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf | 137 + .../X64DEBUG/X64/PchS3SupportDxe.depex | 1 + .../X64DEBUG/X64/PchS3SupportDxe.efi | Bin 0 -> 58368 bytes .../X64DEBUG/X64/PchS3SupportDxe.inf | 257 + .../X64DEBUG/X64/PchSmbusDxe.depex | 1 + .../X64DEBUG/X64/PchSmbusDxe.efi | Bin 0 -> 35328 bytes .../X64DEBUG/X64/PchSmbusDxe.inf | 214 + .../X64DEBUG/X64/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../X64DEBUG/X64/PchSmiDispatcher.efi | Bin 0 -> 53760 bytes .../X64DEBUG/X64/PchSmiDispatcher.inf | 181 + .../X64DEBUG/X64/PchSpiRuntime.depex | 1 + .../X64DEBUG/X64/PchSpiRuntime.efi | Bin 0 -> 50688 bytes .../X64DEBUG/X64/PchSpiRuntime.inf | 258 + .../X64DEBUG/X64/PchSpiSmm.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.efi | Bin 0 -> 54272 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf | 251 + .../X64DEBUG/X64/PciHostBridge.depex | Bin 0 -> 54 bytes .../X64DEBUG/X64/PciHostBridge.efi | Bin 0 -> 49856 bytes .../X64DEBUG/X64/PciHostBridge.inf | 254 + .../X64DEBUG/X64/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../X64DEBUG/X64/PlatformCpuPolicy.efi | Bin 0 -> 35392 bytes .../X64DEBUG/X64/PlatformCpuPolicy.inf | 227 + .../Vlv2SocBinPkg/X64DEBUG/X64/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PnpDxe.efi | Bin 0 -> 33664 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PnpDxe.inf | 207 + .../X64DEBUG/X64/PowerManagement2.depex | 1 + .../X64DEBUG/X64/PowerManagement2.efi | Bin 0 -> 75776 bytes .../X64DEBUG/X64/PowerManagement2.inf | 270 + .../X64DEBUG/X64/SataController.efi | Bin 0 -> 30208 bytes .../X64DEBUG/X64/SataController.inf | 204 + .../X64DEBUG/X64/SmmAccess.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.efi | Bin 0 -> 25600 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf | 210 + .../X64DEBUG/X64/SmmControl.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/SmmControl.efi | Bin 0 -> 27136 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/SmmControl.inf | 129 + .../X64DEBUG/X64/VlvInitDxe.depex | Bin 0 -> 126 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.efi | Bin 0 -> 55168 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf | 259 + .../X64RELEASE/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.efi | Bin 0 -> 6080 bytes .../Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.inf | 123 + .../X64RELEASE/IA32/MemoryInit.depex | 1 + .../X64RELEASE/IA32/MemoryInit.efi | Bin 0 -> 93888 bytes .../X64RELEASE/IA32/MemoryInit.inf | 196 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64RELEASE/IA32/PchEarlyInitPeim.depex | 1 + .../X64RELEASE/IA32/PchEarlyInitPeim.efi | Bin 0 -> 14752 bytes .../X64RELEASE/IA32/PchEarlyInitPeim.inf | 97 + .../X64RELEASE/IA32/PchInitPeim.depex | 1 + .../X64RELEASE/IA32/PchInitPeim.efi | Bin 0 -> 11776 bytes .../X64RELEASE/IA32/PchInitPeim.inf | 136 + .../X64RELEASE/IA32/PchSmbusArpDisabled.depex | 1 + .../X64RELEASE/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 3136 bytes .../X64RELEASE/IA32/PchSmbusArpDisabled.inf | 130 + .../X64RELEASE/IA32/PchSpiPeim.depex | 1 + .../X64RELEASE/IA32/PchSpiPeim.efi | Bin 0 -> 4384 bytes .../X64RELEASE/IA32/PchSpiPeim.inf | 125 + .../X64RELEASE/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/X64RELEASE/IA32/PchUsb.efi | Bin 0 -> 1344 bytes .../Vlv2SocBinPkg/X64RELEASE/IA32/PchUsb.inf | 124 + .../X64RELEASE/IA32/PeiSmmAccess.depex | 1 + .../X64RELEASE/IA32/PeiSmmAccess.efi | Bin 0 -> 1664 bytes .../X64RELEASE/IA32/PeiSmmAccess.inf | 119 + .../X64RELEASE/IA32/PeiSmmControl.depex | 1 + .../X64RELEASE/IA32/PeiSmmControl.efi | Bin 0 -> 960 bytes .../X64RELEASE/IA32/PeiSmmControl.inf | 95 + .../X64RELEASE/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../X64RELEASE/IA32/ResetVec.com | Bin 0 -> 64 bytes .../X64RELEASE/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/X64RELEASE/IA32/SeCUma.efi | Bin 0 -> 1856 bytes .../Vlv2SocBinPkg/X64RELEASE/IA32/SeCUma.inf | 101 + .../Vlv2SocBinPkg/X64RELEASE/IA32/SecCore.efi | Bin 0 -> 8000 bytes .../Vlv2SocBinPkg/X64RELEASE/IA32/SecCore.inf | 152 + .../X64RELEASE/IA32/VlvInitPeim.depex | 1 + .../X64RELEASE/IA32/VlvInitPeim.efi | Bin 0 -> 3104 bytes .../X64RELEASE/IA32/VlvInitPeim.inf | 101 + .../X64RELEASE/X64/DigitalThermalSensor.depex | 1 + .../X64RELEASE/X64/DigitalThermalSensor.efi | Bin 0 -> 8192 bytes .../X64RELEASE/X64/DigitalThermalSensor.inf | 182 + .../Vlv2SocBinPkg/X64RELEASE/X64/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/Dptf.efi | Bin 0 -> 4384 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/Dptf.inf | 213 + .../X64RELEASE/X64/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../X64RELEASE/X64/GraphicDxeInitSmm.efi | Bin 0 -> 11264 bytes .../X64RELEASE/X64/GraphicDxeInitSmm.inf | 259 + .../Vlv2SocBinPkg/X64RELEASE/X64/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/X64RELEASE/X64/ISPDxe.efi | Bin 0 -> 6880 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/ISPDxe.inf | 241 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64RELEASE/X64/PchBiosWriteProtect.depex | 1 + .../X64RELEASE/X64/PchBiosWriteProtect.efi | Bin 0 -> 4096 bytes .../X64RELEASE/X64/PchBiosWriteProtect.inf | 121 + .../X64RELEASE/X64/PchInitDxe.depex | Bin 0 -> 126 bytes .../X64RELEASE/X64/PchInitDxe.efi | Bin 0 -> 59648 bytes .../X64RELEASE/X64/PchInitDxe.inf | 272 + .../X64RELEASE/X64/PchInitSmm.depex | Bin 0 -> 162 bytes .../X64RELEASE/X64/PchInitSmm.efi | Bin 0 -> 18432 bytes .../X64RELEASE/X64/PchInitSmm.inf | 284 + .../X64RELEASE/X64/PchPcieSmm.depex | Bin 0 -> 108 bytes .../X64RELEASE/X64/PchPcieSmm.efi | Bin 0 -> 13312 bytes .../X64RELEASE/X64/PchPcieSmm.inf | 245 + .../X64RELEASE/X64/PchPolicyInitDxe.depex | 1 + .../X64RELEASE/X64/PchPolicyInitDxe.efi | Bin 0 -> 2528 bytes .../X64RELEASE/X64/PchPolicyInitDxe.inf | 109 + .../X64RELEASE/X64/PchReset.depex | 1 + .../Vlv2SocBinPkg/X64RELEASE/X64/PchReset.efi | Bin 0 -> 4608 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/PchReset.inf | 130 + .../X64RELEASE/X64/PchS3SupportDxe.depex | 1 + .../X64RELEASE/X64/PchS3SupportDxe.efi | Bin 0 -> 16224 bytes .../X64RELEASE/X64/PchS3SupportDxe.inf | 251 + .../X64RELEASE/X64/PchSmbusDxe.depex | 1 + .../X64RELEASE/X64/PchSmbusDxe.efi | Bin 0 -> 6848 bytes .../X64RELEASE/X64/PchSmbusDxe.inf | 206 + .../X64RELEASE/X64/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../X64RELEASE/X64/PchSmiDispatcher.efi | Bin 0 -> 17920 bytes .../X64RELEASE/X64/PchSmiDispatcher.inf | 175 + .../X64RELEASE/X64/PchSpiRuntime.depex | 1 + .../X64RELEASE/X64/PchSpiRuntime.efi | Bin 0 -> 13312 bytes .../X64RELEASE/X64/PchSpiRuntime.inf | 252 + .../X64RELEASE/X64/PchSpiSmm.depex | 1 + .../X64RELEASE/X64/PchSpiSmm.efi | Bin 0 -> 11776 bytes .../X64RELEASE/X64/PchSpiSmm.inf | 245 + .../X64RELEASE/X64/PciHostBridge.depex | Bin 0 -> 54 bytes .../X64RELEASE/X64/PciHostBridge.efi | Bin 0 -> 21152 bytes .../X64RELEASE/X64/PciHostBridge.inf | 248 + .../X64RELEASE/X64/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../X64RELEASE/X64/PlatformCpuPolicy.efi | Bin 0 -> 9344 bytes .../X64RELEASE/X64/PlatformCpuPolicy.inf | 216 + .../Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.efi | Bin 0 -> 10080 bytes .../Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.inf | 200 + .../X64RELEASE/X64/PowerManagement2.depex | 1 + .../X64RELEASE/X64/PowerManagement2.efi | Bin 0 -> 21504 bytes .../X64RELEASE/X64/PowerManagement2.inf | 264 + .../X64RELEASE/X64/SataController.efi | Bin 0 -> 4064 bytes .../X64RELEASE/X64/SataController.inf | 195 + .../X64RELEASE/X64/SmmAccess.depex | Bin 0 -> 36 bytes .../X64RELEASE/X64/SmmAccess.efi | Bin 0 -> 2208 bytes .../X64RELEASE/X64/SmmAccess.inf | 198 + .../X64RELEASE/X64/SmmControl.depex | 1 + .../X64RELEASE/X64/SmmControl.efi | Bin 0 -> 3584 bytes .../X64RELEASE/X64/SmmControl.inf | 122 + .../X64RELEASE/X64/VlvInitDxe.depex | Bin 0 -> 126 bytes .../X64RELEASE/X64/VlvInitDxe.efi | Bin 0 -> 19328 bytes .../X64RELEASE/X64/VlvInitDxe.inf | 253 + 451 files changed, 128555 insertions(+) create mode 100644 Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/IA32/IntelGopDriver.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt create 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create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitPeim.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitSmm.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitSmm.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitSmm.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPcieSmm.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPcieSmm.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPcieSmm.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPolicyInitDxe.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPolicyInitDxe.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchPolicyInitDxe.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.efi create mode 100644 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Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiRuntime.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiRuntime.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiRuntime.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PciHostBridge.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PciHostBridge.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PciHostBridge.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmAccess.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmAccess.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmAccess.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmControl.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmControl.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmControl.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf create mode 100644 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100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmAccess.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmAccess.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmAccess.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.efi create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.inf create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.depex create mode 100644 Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.efi create 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b/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. 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=A$|AIE;~o)0A2Vih;f9w|9hH_i|y zyi6}2eD-YNsw;-24_i+F+57>-9Cej?n~o`%PcMxHUE^ntjl7dlGIK1Y@a{}>4^mN? zJe%#T;`hDk^NAX+>4L69+SUD^hWhgPl}_PL%2Dt;x>sO1$IJ#&3zd zpc>bN=Q<;}Y)-qEX9L1X#ZRq@+{!Sa)#J4w6vHh<)#Gjx+$yX1b7Oy%IM}{m8`GF)F<%@d(wZhBiPs} zG+bnnLl(MtE-iF( z%DlEvoX6i(n8&lK(92UV%;D>`g~NGP6=pD{4vLZ);$QZ{x}4*xfI-A45vr)i;kihO zhY_f%w;@~#*~lz}f<}l_m+CBBP7K>n3UTgXl|)KJYAVuqDL&`0Bpph+R0o!NRFeEU zslhHXTPC%N9#)syRHwA^T!nh`94A6)%KE^gH_wtrb$jYk?I?zWAayjNWtKx9zgvqT z{!b-DnJ#kB>u+9`sgK`M*M7*QH{a|=U(QR$q)Q+FMqvE**tXavVkjDX2}`kAdUIfK zqRUm+{!wQ37KAO4_Y!2F0;&a>O6u@3#loazACA16+dM1VpZ)jdKyGs&&!2s?IWVL- z;B5{d*9qr{{|;yV>PX1xnKe{vswx~D&XS*@p>rd%hK`B_tjLf%H?!Fa4`of5HPj{J z&k}Ms6vDuz`ld~md@;YW<=gn0UgVQAy`qrW_p9Pl&O%z}U5k6O34V2WL;C0mIytXT zoeDv0+}(3=z?k1tgih67*v4k*F3^pXRFV)7+Ek zEOlb#CR+$>u*`vCc=_@0IC+&tK44V!T-=`!*P`tn^KQwTvsXF>c8gM{W%@}mmf@=0 z)TE{$=CO z)*e3@I_m)LJVqU@Pg2(xd-z>t``_+iiHsoQss<6yK31MDj^Tf$Go7xF7o0MNQm-md zx(HqV?~?g{=%huq?cfG0EHLAfN@L5>e}mMTmf~@JDp1rb*Si(d*Nr^Reu`IbsA4v~u6kN$>|D)GJ)Y)7hdah-R$UO4Kg_dA2? zyzgfPqaE1C>&!p+k@t^>>%8CLQ*v;nailW7v@G?xG~qX&S=HLD+p&Y@ouDSr->M54 z6~?E_w;{mW7A)R#^mjpg=N`0b8(QZ*l(6cdj$_neY&-fpcm#4Fvj4o7V?D_i%-Lv1 zN%>kVA&Qm#`g2MJ!E_B@i*>0U<=1)dP5j+kpKy3b4y;l2id*MWZ#(r$`2z~4Ic)lP zuj*IF?^P$95*r#RMb}Bur}pIcR*C7JSieE!2rIW8+vusQBwr}Iszq*8a~#_m+|wP( zx0(mldyNHp7GRSo!LT{ZMt$>7?RMmCcx4|Q70*lNC|XTG+{ZQY*7M2g3^iu zK|+cv<&d860nx$%7I6T=C5RK^z=2BMD1W8d zKjZ(O|9}6_jPIHmKM~A~O-&trdS>$IQvnLhK?n~NPvO`t?N4m4(GTGU6yUp-TDYYBbP(Erpn*n^8w}7(n-YA5MzGM#RT!iAyLlt~1{lI?Ns?P# z^Ga|Gd9>)EXh7#O4UnAgvtR+3zXU!gR?}+APOks{Ptk=!fr7-*z=DI!N{ToZHGmd? zN-zpwNGNnbl~<1!^>>;JfP0{OA&a0CKrwBno*`|27o1AZr<>qGMJ2GaY^)ImYvd1O zxwJX8{8S}Le5X} zLqzgqF?c9ypI+UI2*WxFP_>BlJ?FLUr5ye6&QN=;v9u?wzrEusf~CGJG?RG{!eM!_ zwKNx&8yW2wgN5y=5dLFNYJ|QN!47g{ak&ERdaxt(!XwHH6c1K>o6@|99L&)VmmiMG zXAX|Y=15g}r3g?|nuiylZY?$GB}pzY!GvU?7JP#O<-t~_@y@ub^NH_XS@ZMto^G1%U9)=Q192L YKuUAXxZw`yuE*BO76V%hY)S_H0_g|%5C8xG literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/VBT/MNW2/vbt.bsf b/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/VBT/MNW2/vbt.bsf new file mode 100644 index 0000000..c8d2daf --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/VBT/MNW2/vbt.bsf @@ -0,0 +1,9216 @@ +; TITLE BMP.bsf - BMP Scrip File for Video BIOS +;============================================================================== +; Advance Graphics ROM BIOS +;------------------------------------------------------------------------------ +; Copyright (c) Intel Corporation (2000 - 2011). +; +; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS +; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, +; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. +; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. +; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, +; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER +; WARRANTY. +; +; Intel disclaims all liability, including liability for infringement of +; any proprietary rights, relating to use of the code. No license, express +; or implied, by estoppel or otherwise, to any intellectual property rights +; is granted herein. +; +; File Description: +; This file is the script file use by the BMP utility which will allow +; OEM's to edit data and select features on a binary file. +; +;------------------------------------------------------------------------------ + + +;============================================================================== +; Header - Start of BMP Structure Definition +;------------------------------------------------------------------------------ + +StructDef + +Find "BIOS_DATA_BLOCK " + + ; The following block will determine the reference + ; pointer for all table pointer variables. + +Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data + +$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) +$BDB_Header_Size 2 bytes ; BIOS Data Block Header size +$BDB_Size 2 bytes ; BIOS Data Block size + +;============================================================================== +; Block 1 - General Bit Definitions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + + ; + ; bmp_Bits_1 + ; + +$Enable_Panel_Fitting 2 bits ; Enable / Disable panel fitting +$Flexaim_Support 1 bit ; Enable / Disable Flex-aim support +$Msg_Enable 1 bit ; Disable signon and copyright +$Cls_After_Signon 3 bits ; Clear screen after display message and pause +$bmp_DVO_A_Color_Flip 1 bit ; Flat color flip +ALIGN + + ; + ; bmp_Bits_2 + ; +$Download_Ext_VBT 1 bit ; Download external VBT flag +$Enable_SSC 1 bit ; Enable/Disable SSC +$SSC_Freq 1 bit ; SSC Frequency +$Enable_LFPOn_Override 1 bit ; Enable/Disable LFP ON Override +$Disable_SSC_DDT 1 bit ; Disable SSC in Dual Display Twin +$Override_VGA_720p 1 bit ; Enable/Disable Override 720p for VGA modes +$Enable_Dynamic_CDClock 1 bit ; Enables Dynamic CD clock feature +$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS + +ALIGN + ; + ; bmp_Bits_3 + ; +SKIP 2 bits +$180_Deg_Rotation_Enable 1 bit ; 180 Degree Rotation Enable bit +SKIP 5 bits +ALIGN + +$bmp_Legacy_Monitor_Detect 1 bit ; Use legacy monitor detect algorithm +SKIP 7 bits +ALIGN + + ; + ; Int_Displays_Support + ; +$Int_CRT_Support 1 bit ; Integrated CRT support +$Int_TV_Support 1 bit ; Integrated TV support +$Int_EFP_Support 1 bit ; Integrated EFP support +$DP_SSC_Enb 1 bit ; DP SSC Enable bit +$DP_SSC_Freq 1 bit ; DP SSC Frequency bit +$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable +SKIP 2 bits + +ALIGN + + +;============================================================================== +; Block 253 - PRD Boot Algorithm Table +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 1 byte +$ChildDevice1Primary 1 byte +$ChildDevice1Secondary 1 byte +SKIP 1 byte +$ChildDevice2Primary 1 byte +$ChildDevice2Secondary 1 byte +SKIP 1 byte +$ChildDevice3Primary 1 byte +$ChildDevice3Secondary 1 byte +SKIP 1 byte +$ChildDevice4Primary 1 byte +$ChildDevice4Secondary 1 byte +SKIP 1 byte +$ChildDevice5Primary 1 byte +$ChildDevice5Secondary 1 byte +SKIP 1 byte +$ChildDevice6Primary 1 byte +$ChildDevice6Secondary 1 byte +SKIP 1 byte +$ChildDevice7Primary 1 byte +$ChildDevice7Secondary 1 byte +SKIP 1 byte +$ChildDevice8Primary 1 byte +$ChildDevice8Secondary 1 byte +SKIP 1 byte +$ChildDevice9Primary 1 byte +$ChildDevice9Secondary 1 byte +SKIP 1 byte +$ChildDevice10Primary 1 byte +$ChildDevice10Secondary 1 byte +SKIP 1 byte +$ChildDevice11Primary 1 byte +$ChildDevice11Secondary 1 byte +SKIP 1 byte +$ChildDevice12Primary 1 byte +$ChildDevice12Secondary 1 byte +SKIP 1 byte +$ChildDevice13Primary 1 byte +$ChildDevice13Secondary 1 byte +SKIP 1 byte +$ChildDevice14Primary 1 byte +$ChildDevice14Secondary 1 byte +SKIP 1 byte +$ChildDevice15Primary 1 byte +$ChildDevice15Secondary 1 byte +SKIP 1 byte +$ChildDevice16Primary 1 byte +$ChildDevice16Secondary 1 byte + +SKIP 2 bytes ; No of entries + +;============================================================================== +; Block 2 - General Data Definitions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$CRT_DDC_GMBUS_Pin 1 byte ; CRT DDC GMBUS pin pair + +$DPMS_ACPI_Bit 1 bit ; Apply ACPI DPMS CRT Power States +$Skip_Boot_CRT_Detect 1 bit ; Disable/Enable skip boot CRT detect +$DPMS_AIM_Bit 1 bit ; Apply DPMS to AIM devices +SKIP 5 bits +ALIGN + + +$Boot_Display 2 bytes ; Boot display type +$size_ChildStruc 1 byte + + +$Int_LFP1_DID 2 bytes ; Skip Device Handle +$Int_LFP1_Type 2 bytes ; Device type +SKIP 7 bytes ; Skip +SKIP 1 byte ; Skip +$Int_LFP1_Priority 1 byte ; primary/secondary panel select +ALIGN +SKIP 3 bytes ; Skip +$Int_LFP1_Port 1 byte ; eDP port select +SKIP 2 bytes ; Skip remaining Data structure +$Int_LFP1_DDC_Pin 1 byte ; LFP DDC GMBUS pin pair +SKIP 5 bytes +$Int_LFP1_AUX_Channel 1 byte ; DP AUX channel +SKIP 7 bytes + + +$Int_LFP2_DID 2 bytes ; Skip Device Handle +$Int_LFP2_Type 2 bytes ; Device type +SKIP 7 bytes ; Skip +SKIP 1 byte ; Skip +$Int_LFP2_Priority 8 bits ; primary/secondary panel select +ALIGN +SKIP 3 bytes ; Skip +$Int_LFP2_Port 1 byte ; eDP port select +SKIP 2 bytes ; Skip remaining Data structure +$Int_LFP2_DDC_Pin 1 byte ; LFP DDC GMBUS pin pair +SKIP 5 bytes +$Int_LFP2_AUX_Channel 1 byte ; DP AUX channel +SKIP 7 bytes + + +$Int_EFP1_DID 2 bytes ; Skip Device Handle +$Int_EFP1_Type 2 bytes ; Device type +SKIP 1 byte ; Skip I2C Speed +$EFP1_OnBoard_PreEmph_Level 3 bits ; EFP1 On Board Dp Redriver PreEmphasis Level +$EFP1_OnBoard_VSwing_Level 3 bits ; EFP1 On Board Dp Redriver VSwing Level +$EFP1_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP1 +SKIP 1 bit ; Reserved +$EFP1_OnDock_PreEmph_Level 3 bits ; EFP1 On Dock Dp Redriver PreEmphasis Level +$EFP1_OnDock_VSwing_Level 3 bits ; EFP1 On Dock Dp Redriver VSwing Level +$EFP1_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP1 +SKIP 1 bit ; Reserved +$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration +SKIP 3 bits ; Reserved +ALIGN +SKIP 2 bytes ; Skip EDIDless DTD offset +$EFP1_EDIDless_en 1 bit ; EDIDless enable bit +SKIP 7 bits ; Skip remaining bits +SKIP 3 bytes ; Skip Reserved_1 +SKIP 2 bytes ; skip Addin module table offset +$Int_EFP1_Port 1 byte ; EFP1 port +SKIP 2 bytes ; Skip +$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin +SKIP 3 bytes +$Int_EFP1_Docked_Port 1 bit ; HDMI/DP Docked Port +SKIP 1 bit ; Skip Enabling Lane Reversal Bit +SKIP 6 bits ; Reserved +$Int_EFP1_HDMI_Compat 1 bit ; HDMI combatibility +$Int_EFP1_Conn_Info 3 bits ; Connector information +SKIP 4 bits +$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel +$Int_EFP1_Dongle_Detect 1 byte ; Dongle Detect +SKIP 6 bytes ; Skip + +$Int_EFP2_DID 2 bytes ; Skip Device Handle +$Int_EFP2_Type 2 bytes ; Device type +SKIP 1 byte ; Skip I2C Speed +$EFP2_OnBoard_PreEmph_Level 3 bits ; EFP2 On Board Dp Redriver PreEmphasis Level +$EFP2_OnBoard_VSwing_Level 3 bits ; EFP2 On Board Dp Redriver VSwing Level +$EFP2_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 +SKIP 1 bit ; Reserved +$EFP2_OnDock_PreEmph_Level 3 bits ; EFP2 On Dock Dp Redriver PreEmphasis Level +$EFP2_OnDock_VSwing_Level 3 bits ; EFP2 On Dock Dp Redriver VSwing Level +$EFP2_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP2 +SKIP 1 bit ; Reserved +$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration +SKIP 3 bits ; Reserved +ALIGN +SKIP 2 bytes ; Skip EDIDless DTD offset +$EFP2_EDIDless_en 1 bit ; EDIDless enable bit +SKIP 7 bits ; Skip remaining bits +SKIP 3 bytes ; Skip Reserved_1 +SKIP 2 bytes ; skip Addin module table offset +$Int_EFP2_Port 1 byte ; EFP1 port +SKIP 2 bytes ; Skip +$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin +SKIP 3 bytes +$Int_EFP2_Docked_Port 1 bit ; HDMI/DP Docked Port +SKIP 1 bit ; Skip Enabling Lane Reversal Bit +SKIP 6 bits ; Reserved +$Int_EFP2_HDMI_Compat 1 bit ; HDMI combatibility +$Int_EFP2_Conn_Info 3 bits ; Connector information +SKIP 4 bits +$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel +$Int_EFP2_Dongle_Detect 1 byte ; Dongle Detect +SKIP 6 bytes ; Skip + +;============================================================================== +; Block 3 - Original Display Toggle List +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$bmp_Display_Detect 1 byte ; Display must be attached or not + +;============================================================================== +; Block 9 - PSR Feature Table +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 96 bytes ; PSR Table data + +;============================================================================== + + +;============================================================================== +; Block 10 - Modes Removal Table. +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 1 byte ; Skip EntrySize +$Mode_Rem_Table 200 bytes ; Mode Removal Table +SKIP 2 bytes ; Skip Terminator + +;============================================================================== +; Block 12 - Driver default boot display +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Driver_Boot_Device 1 bit +$Block_Disp_Switch 1 bit +$Allow_FDOS_Disp_Switch 1 bit ; Allow FS DOS display switching +$Hot_Plug_DVO 1 bit +$Dual_View_Zoom 1 bit +$Drv_Int15_hook 1 bit +$DVD_Sprite_Clone 1 bit +$Use_110h_for_LFP 1 bit +ALIGN + +$Driver_Boot_Mode_X 2 bytes ; X resolution +$Driver_Boot_Mode_Y 2 bytes ; Y resolution +$Driver_Boot_Mode_BPP 1 byte ; Pixel depth +$Driver_Boot_Mode_RR 1 byte ; Refresh rate +; bmp_Ext_Driver_Bits + +$Enable_LFP_Primary 1 bit +$GTF_Mode_Pruning 1 bit +SKIP 1 bit ; DISABLE_DFGT +SKIP 1 bit ; DISABLE_DFGT +$NT4_Dual_Dsp_Clone_Spt 1 bit ; Dual display clone support for NT4 +$Default_Power_Scheme 1 bit +$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode +$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI +$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio +$SDVO_Device_Power_Down 1 bit ; SDVO device power down +$Hot_Plug_CRT 1 bit ; CRT hot plug +$LVDS_Config 2 bits ; LVDS configuration +$Hot_Plug_TV 1 bit ; Hot plug TV enable/disable +$INT_HDMI_Config 2 bits ; Integrated HDMI Configuration +ALIGN + + ; bmp_Driver_Flags_1 + +$CUIHotK_Static_Display 1 bit +SKIP 7 bits +$Legacy_Monitor_Max_X 2 bytes +$Legacy_Monitor_Max_Y 2 bytes +$Legacy_Monitor_Max_RR 1 bytes +ALIGN + +; bmp_Ext2_Driver_Bits + +$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI +SKIP 7 bits +ALIGN + +$VBT_Customization_Version 1 byte ; Customization VBT version number +ALIGN + + ; bmp_Driver_Feature_Flags + +SKIP 5 bits +$PM_DRRS_Enable 1 bit ; Intel ® Display Refresh Rate Switching (DRRS) Enable/Disable Flag. +SKIP 3 bits +$Panel_Self_Refresh 1 bit ; Panel Self refresh feature (PSR) +SKIP 2 bits +$DMRRS 1 bit ; Dynamic Media Refresh Rate Enable/Disable +SKIP 3 bits + +;============================================================================== +; Block 13 - Driver Persistence Algorithm +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$Driver_Persist_Hotkey 1 bit +$Driver_Persist_Lid_Switch 1 bit +$Driver_Persist_PM 1 bit +$PersistHotkeyRestoreCloneMDS 1 bit +$PersistHotkeyRestoreRefreshrate 1 bit +$PersistHotkeyRestorePipe 1 bit +$PersistHotkeyRestoreMode 1 bit +$PersistEDIDRestoreMode 1 bit +$PersistHotPlugRestoreMode 1 bit +$Driver_Persist_Docking 1 bit +SKIP 6 bits +ALIGN +$PersistMaxConfig 1 byte + +;============================================================================== +; Block 16 - VBIOS/Driver Toggle list, capabilities tables +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List1 48 bytes ; Toggle list 1 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List2 24 bytes ; Toggle list 2 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List3 24 bytes ; Toggle list 3 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List4 24 bytes ; Toggle list 4 +ALIGN + +;============================================================================== +; Block 17 - Test Feature +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$SV_Dis_Arbiter 1 bit ; Disable VGA fast arbiter +$SV_Setmode_No_DVO 1 bit ; Do Setmode without reprogramming DVO +$SV_Special_GMBus 1 bit ; Special GMBus support +$SV_Wait_Timeout_Hang 1 bit +SKIP 4 bits +ALIGN +SKIP 7 bytes ; Skip reserved space + + +;============================================================================== +; Block 18 - Driver Rotation Configuration +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Rotation_Support_Enable 1 bit ; Driver Rotation Feature Support bit +SKIP 7 bits +$Rot_Flags 1 byte +SKIP 10 bytes + + +;============================================================================== +; Block 19 - Removed Display Configurations +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 2 bytes ; Table Row/Size Data +$Dev_Removed_Table 30 bytes ; Removed displays table + +;============================================================================== +; Block 20 - OEM Customizable Modes +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip ID +SKIP 2 bytes ; Table Row/Size Data + +$OEM_Mode_Flags1 1 byte +$OEM_Display_Flags1 1 byte +$OEM_Mode_X1 2 bytes +$OEM_Mode_Y1 2 bytes +$OEM_Mode_Color1 1 byte +$OEM_Mode_RRate1 1 byte +$OEM_Mode_DTD1 18 bytes + +$OEM_Mode_Flags2 1 byte +$OEM_Display_Flags2 1 byte +$OEM_Mode_X2 2 bytes +$OEM_Mode_Y2 2 bytes +$OEM_Mode_Color2 1 byte +$OEM_Mode_RRate2 1 byte +$OEM_Mode_DTD2 18 bytes + +$OEM_Mode_Flags3 1 byte +$OEM_Display_Flags3 1 byte +$OEM_Mode_X3 2 bytes +$OEM_Mode_Y3 2 bytes +$OEM_Mode_Color3 1 byte +$OEM_Mode_RRate3 1 byte +$OEM_Mode_DTD3 18 bytes + +$OEM_Mode_Flags4 1 byte +$OEM_Display_Flags4 1 byte +$OEM_Mode_X4 2 bytes +$OEM_Mode_Y4 2 bytes +$OEM_Mode_Color4 1 byte +$OEM_Mode_RRate4 1 byte +$OEM_Mode_DTD4 18 bytes + +$OEM_Mode_Flags5 1 byte +$OEM_Display_Flags5 1 byte +$OEM_Mode_X5 2 bytes +$OEM_Mode_Y5 2 bytes +$OEM_Mode_Color5 1 byte +$OEM_Mode_RRate5 1 byte +$OEM_Mode_DTD5 18 bytes + +$OEM_Mode_Flags6 1 byte +$OEM_Display_Flags6 1 byte +$OEM_Mode_X6 2 bytes +$OEM_Mode_Y6 2 bytes +$OEM_Mode_Color6 1 byte +$OEM_Mode_RRate6 1 byte +$OEM_Mode_DTD6 18 bytes + +;============================================================================== +; Block 26 - TV Options +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip ID and size +$Under_Over_Scan_Via_YPrPb 2 bits ; Underscan/overscan for HDTV via YPrPb +SKIP 10 bits +$Under_Over_Scan_Via_DVI 2 bits ; Underscan/overscan for HDTV via DVI +$Add_Overscan_Mode 1 bit ; Add modes to avoid overscan issue +$D_Connector 1 bit ; D-Connector Support +ALIGN + +;============================================================================== +; Block #27 - eDP Power Sequencing +;------------------------------------------------------------------------------ +SKIP 3 bytes ; Skip block ID and size + + ; Panel#1 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_01 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes +$eDP_DataOff_To_PowerOff_Delay_01 2 bytes +$eDP_PowerCycle_Delay_01 2 bytes + + ; Panel#2 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_02 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes +$eDP_DataOff_To_PowerOff_Delay_02 2 bytes +$eDP_PowerCycle_Delay_02 2 bytes + + ; Panel#3 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_03 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes +$eDP_DataOff_To_PowerOff_Delay_03 2 bytes +$eDP_PowerCycle_Delay_03 2 bytes + + ; Panel#4 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_04 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes +$eDP_DataOff_To_PowerOff_Delay_04 2 bytes +$eDP_PowerCycle_Delay_04 2 bytes + + ; Panel#5 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_05 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes +$eDP_DataOff_To_PowerOff_Delay_05 2 bytes +$eDP_PowerCycle_Delay_05 2 bytes + + ; Panel#6 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_06 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes +$eDP_DataOff_To_PowerOff_Delay_06 2 bytes +$eDP_PowerCycle_Delay_06 2 bytes + + ; Panel#7 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_07 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes +$eDP_DataOff_To_PowerOff_Delay_07 2 bytes +$eDP_PowerCycle_Delay_07 2 bytes + + ; Panel#8 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_08 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes +$eDP_DataOff_To_PowerOff_Delay_08 2 bytes +$eDP_PowerCycle_Delay_08 2 bytes + + ; Panel#9 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_09 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes +$eDP_DataOff_To_PowerOff_Delay_09 2 bytes +$eDP_PowerCycle_Delay_09 2 bytes + + ; Panel#10 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_10 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes +$eDP_DataOff_To_PowerOff_Delay_10 2 bytes +$eDP_PowerCycle_Delay_10 2 bytes + + ; Panel#11 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_11 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes +$eDP_DataOff_To_PowerOff_Delay_11 2 bytes +$eDP_PowerCycle_Delay_11 2 bytes + + ; Panel#12 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_12 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes +$eDP_DataOff_To_PowerOff_Delay_12 2 bytes +$eDP_PowerCycle_Delay_12 2 bytes + + ; Panel#13 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_13 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes +$eDP_DataOff_To_PowerOff_Delay_13 2 bytes +$eDP_PowerCycle_Delay_13 2 bytes + + ; Panel#14 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_14 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes +$eDP_DataOff_To_PowerOff_Delay_14 2 bytes +$eDP_PowerCycle_Delay_14 2 bytes + + ; Panel#15 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_15 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes +$eDP_DataOff_To_PowerOff_Delay_15 2 bytes +$eDP_PowerCycle_Delay_15 2 bytes + + ; Panel#16 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_16 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes +$eDP_DataOff_To_PowerOff_Delay_16 2 bytes +$eDP_PowerCycle_Delay_16 2 bytes + +$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp + +$eDP_Link_DataRate_01 4 bits ; Panel #1 Link Data Rate +$eDP_Link_LaneCount_01 4 bits ; Panel #1 Link Lane Count +$eDP_Link_PreEmp_Level_01 4 bits ; Panel #1 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_01 4 bits ; Panel #1 Link Voltage Swing Level + +$eDP_Link_DataRate_02 4 bits ; Panel #2 Link Data Rate +$eDP_Link_LaneCount_02 4 bits ; Panel #2 Link Lane Count +$eDP_Link_PreEmp_Level_02 4 bits ; Panel #2 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_02 4 bits ; Panel #2 Link Voltage Swing Level + +$eDP_Link_DataRate_03 4 bits ; Panel #3 Link Data Rate +$eDP_Link_LaneCount_03 4 bits ; Panel #3 Link Lane Count +$eDP_Link_PreEmp_Level_03 4 bits ; Panel #3 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_03 4 bits ; Panel #3 Link Voltage Swing Level + +$eDP_Link_DataRate_04 4 bits ; Panel #4 Link Data Rate +$eDP_Link_LaneCount_04 4 bits ; Panel #4 Link Lane Count +$eDP_Link_PreEmp_Level_04 4 bits ; Panel #4 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_04 4 bits ; Panel #4 Link Voltage Swing Level + +$eDP_Link_DataRate_05 4 bits ; Panel #5 Link Data Rate +$eDP_Link_LaneCount_05 4 bits ; Panel #5 Link Lane Count +$eDP_Link_PreEmp_Level_05 4 bits ; Panel #5 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_05 4 bits ; Panel #5 Link Voltage Swing Level + +$eDP_Link_DataRate_06 4 bits ; Panel #6 Link Data Rate +$eDP_Link_LaneCount_06 4 bits ; Panel #6 Link Lane Count +$eDP_Link_PreEmp_Level_06 4 bits ; Panel #6 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_06 4 bits ; Panel #6 Link Voltage Swing Level + +$eDP_Link_DataRate_07 4 bits ; Panel #7 Link Data Rate +$eDP_Link_LaneCount_07 4 bits ; Panel #7 Link Lane Count +$eDP_Link_PreEmp_Level_07 4 bits ; Panel #7 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_07 4 bits ; Panel #7 Link Voltage Swing Level + +$eDP_Link_DataRate_08 4 bits ; Panel #8 Link Data Rate +$eDP_Link_LaneCount_08 4 bits ; Panel #8 Link Lane Count +$eDP_Link_PreEmp_Level_08 4 bits ; Panel #8 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_08 4 bits ; Panel #8 Link Voltage Swing Level + +$eDP_Link_DataRate_09 4 bits ; Panel #9 Link Data Rate +$eDP_Link_LaneCount_09 4 bits ; Panel #9 Link Lane Count +$eDP_Link_PreEmp_Level_09 4 bits ; Panel #9 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_09 4 bits ; Panel #9 Link Voltage Swing Level + +$eDP_Link_DataRate_10 4 bits ; Panel #10 Link Data Rate +$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count +$eDP_Link_PreEmp_Level_10 4 bits ; Panel #10 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_10 4 bits ; Panel #10 Link Voltage Swing Level + +$eDP_Link_DataRate_11 4 bits ; Panel #11 Link Data Rate +$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count +$eDP_Link_PreEmp_Level_11 4 bits ; Panel #11 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_11 4 bits ; Panel #11 Link Voltage Swing Level + +$eDP_Link_DataRate_12 4 bits ; Panel #12 Link Data Rate +$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count +$eDP_Link_PreEmp_Level_12 4 bits ; Panel #12 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_12 4 bits ; Panel #12 Link Voltage Swing Level + +$eDP_Link_DataRate_13 4 bits ; Panel #13 Link Data Rate +$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count +$eDP_Link_PreEmp_Level_13 4 bits ; Panel #13 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_13 4 bits ; Panel #13 Link Voltage Swing Level + +$eDP_Link_DataRate_14 4 bits ; Panel #14 Link Data Rate +$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count +$eDP_Link_PreEmp_Level_14 4 bits ; Panel #14 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_14 4 bits ; Panel #14 Link Voltage Swing Level + +$eDP_Link_DataRate_15 4 bits ; Panel #15 Link Data Rate +$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count +$eDP_Link_PreEmp_Level_15 4 bits ; Panel #15 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_15 4 bits ; Panel #15 Link Voltage Swing Level + +$eDP_Link_DataRate_16 4 bits ; Panel #16 Link Data Rate +$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count +$eDP_Link_PreEmp_Level_16 4 bits ; Panel #16 Link Pre-emphasis Level +$eDP_Link_Vswing_Level_16 4 bits ; Panel #16 Link Voltage Swing Level + +$eDP_sDRRS_MSA_Delay_01 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_02 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_03 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_04 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_05 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_06 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_07 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_08 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_09 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_10 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_11 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_12 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_13 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_14 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_15 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_16 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 + +SKIP 2 bytes ; S3D Feature +$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 +$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 +$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 +$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 +$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 +$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 +$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 +$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 +$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 +$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 +$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 +$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 +$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 +$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 +$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 +$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 + +$eDP_VswingPreEmph_1 4 bits; eDp selects Vswing Preemph table for panel #1 +$eDP_VswingPreEmph_2 4 bits; eDp selects Vswing Preemph table for panel #2 +$eDP_VswingPreEmph_3 4 bits; eDp selects Vswing Preemph table for panel #3 +$eDP_VswingPreEmph_4 4 bits; eDp selects Vswing Preemph table for panel #4 +$eDP_VswingPreEmph_5 4 bits; eDp selects Vswing Preemph table for panel #5 +$eDP_VswingPreEmph_6 4 bits; eDp selects Vswing Preemph table for panel #6 +$eDP_VswingPreEmph_7 4 bits; eDp selects Vswing Preemph table for panel #7 +$eDP_VswingPreEmph_8 4 bits; eDp selects Vswing Preemph table for panel #8 +$eDP_VswingPreEmph_9 4 bits; eDp selects Vswing Preemph table for panel #9 +$eDP_VswingPreEmph_10 4 bits; eDp selects Vswing Preemph table for panel #10 +$eDP_VswingPreEmph_11 4 bits; eDp selects Vswing Preemph table for panel #11 +$eDP_VswingPreEmph_12 4 bits; eDp selects Vswing Preemph table for panel #12 +$eDP_VswingPreEmph_13 4 bits; eDp selects Vswing Preemph table for panel #13 +$eDP_VswingPreEmph_14 4 bits; eDp selects Vswing Preemph table for panel #14 +$eDP_VswingPreEmph_15 4 bits; eDp selects Vswing Preemph table for panel #15 +$eDP_VswingPreEmph_16 4 bits; eDp selects Vswing Preemph table for panel #16 + +$Fast_Link_Training_Supported_01 1 bit ; eDP Selects Fast Link Training if supported for Panel #1 +$Fast_Link_Training_Supported_02 1 bit ; eDP Selects Fast Link Training if supported for Panel #2 +$Fast_Link_Training_Supported_03 1 bit ; eDP Selects Fast Link Training if supported for Panel #3 +$Fast_Link_Training_Supported_04 1 bit ; eDP Selects Fast Link Training if supported for Panel #4 +$Fast_Link_Training_Supported_05 1 bit ; eDP Selects Fast Link Training if supported for Panel #5 +$Fast_Link_Training_Supported_06 1 bit ; eDP Selects Fast Link Training if supported for Panel #6 +$Fast_Link_Training_Supported_07 1 bit ; eDP Selects Fast Link Training if supported for Panel #7 +$Fast_Link_Training_Supported_08 1 bit ; eDP Selects Fast Link Training if supported for Panel #8 +$Fast_Link_Training_Supported_09 1 bit ; eDP Selects Fast Link Training if supported for Panel #9 +$Fast_Link_Training_Supported_10 1 bit ; eDP Selects Fast Link Training if supported for Panel #10 +$Fast_Link_Training_Supported_11 1 bit ; eDP Selects Fast Link Training if supported for Panel #11 +$Fast_Link_Training_Supported_12 1 bit ; eDP Selects Fast Link Training if supported for Panel #12 +$Fast_Link_Training_Supported_13 1 bit ; eDP Selects Fast Link Training if supported for Panel #13 +$Fast_Link_Training_Supported_14 1 bit ; eDP Selects Fast Link Training if supported for Panel #14 +$Fast_Link_Training_Supported_15 1 bit ; eDP Selects Fast Link Training if supported for Panel #15 +$Fast_Link_Training_Supported_16 1 bit ; eDP Selects Fast Link Training if supported for Panel #16 + +SKIP 2 bytes ;Skip Enable Power State at DPCD 600h + +$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 +$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 + +$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 +$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 + +$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 +$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 + +$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 +$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 + +$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 +$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 + +$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 +$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 + +$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#7 +$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#7 + +$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#8 +$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#8 + +$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#9 +$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#9 + +$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#10 +$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#10 + +$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#11 +$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#11 + +$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#12 +$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#12 + +$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#13 +$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#13 + +$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#14 +$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#14 + +$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#15 +$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#15 + +$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#16 +$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#16 + +;============================================================================== +; Block 28 - EDID-less EFP support - Panel data +;------------------------------------------------------------------------------ +SKIP 3 bytes ; Skip block ID and size + + ; Panel for Device 1 +$EFP1_DTD 18 bytes ; DTD for Device 1 DP/DVI panel + ; Panel for Device 2 +$EFP2_DTD 18 bytes ; DTD for Device 2 DP/DVI panel + ; Panel for Device 3 +$EFP3_DTD 18 bytes ; DTD for Device 3 DP/DVI panel + + +;============================================================================== +; Block 40 - Start of LVDS BMP Structure Definition +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$bmp_Panel_type 1 byte ; Flat panel type +SKIP 1 byte ; Obsoleted +SKIP 6 bits +$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit +SKIP 1 bit +SKIP 1 byte + + ; INT_LVDS_Panel_Channel_Bits + +$Int_LVDS_Panel_1_Channel_Type 2 bits ; Bits [2:3] = Panel #1 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_2_Channel_Type 2 bits ; Bits [2:3] = Panel #2 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_3_Channel_Type 2 bits ; Bits [2:3] = Panel #3 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_4_Channel_Type 2 bits ; Bits [2:3] = Panel #4 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_5_Channel_Type 2 bits ; Bits [2:3] = Panel #5 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_6_Channel_Type 2 bits ; Bits [2:3] = Panel #6 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_7_Channel_Type 2 bits ; Bits [2:3] = Panel #7 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_8_Channel_Type 2 bits ; Bits [2:3] = Panel #8 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_9_Channel_Type 2 bits ; Bits [2:3] = Panel #9 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_10_Channel_Type 2 bits ; Bits [2:3] = Panel #10 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_11_Channel_Type 2 bits ; Bits [2:3] = Panel #11 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_12_Channel_Type 2 bits ; Bits [2:3] = Panel #12 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_13_Channel_Type 2 bits ; Bits [2:3] = Panel #13 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_14_Channel_Type 2 bits ; Bits [2:3] = Panel #14 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_15_Channel_Type 2 bits ; Bits [2:3] = Panel #15 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_16_Channel_Type 2 bits ; Bits [2:3] = Panel #16 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved + + ; LVDS Spread Spectrum Clock + ; Enabel/Disable SSC +$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes +$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes +$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes +$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes +$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes +$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes +$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes +$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes +$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes +$Enable_SSC10 1 bit ; Panel #10, 0=No, 1=Yes +$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes +$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes +$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes +$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes +$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes +$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes + + ; LVDS Spread Spectrum Clock Frequency + ; SSC Frequency +$SSC_Freq01 1 bit ; Panel #01, 0=48MHz, 1=66MHz +$SSC_Freq02 1 bit ; Panel #02, 0=48MHz, 1=66MHz +$SSC_Freq03 1 bit ; Panel #03, 0=48MHz, 1=66MHz +$SSC_Freq04 1 bit ; Panel #04, 0=48MHz, 1=66MHz +$SSC_Freq05 1 bit ; Panel #05, 0=48MHz, 1=66MHz +$SSC_Freq06 1 bit ; Panel #06, 0=48MHz, 1=66MHz +$SSC_Freq07 1 bit ; Panel #07, 0=48MHz, 1=66MHz +$SSC_Freq08 1 bit ; Panel #08, 0=48MHz, 1=66MHz +$SSC_Freq09 1 bit ; Panel #09, 0=48MHz, 1=66MHz +$SSC_Freq10 1 bit ; Panel #10, 0=48MHz, 1=66MHz +$SSC_Freq11 1 bit ; Panel #11, 0=48MHz, 1=66MHz +$SSC_Freq12 1 bit ; Panel #12, 0=48MHz, 1=66MHz +$SSC_Freq13 1 bit ; Panel #13, 0=48MHz, 1=66MHz +$SSC_Freq14 1 bit ; Panel #14, 0=48MHz, 1=66MHz +$SSC_Freq15 1 bit ; Panel #15, 0=48MHz, 1=66MHz +$SSC_Freq16 1 bit ; Panel #16, 0=48MHz, 1=66MHz + + ; Disable SSC in Dual Display Twin +$Disable_SSC_DDT01 1 bit ; panel #01, 0=Disable, 1=Enable +$Disable_SSC_DDT02 1 bit ; panel #02, 0=Disable, 1=Enable +$Disable_SSC_DDT03 1 bit ; panel #03, 0=Disable, 1=Enable +$Disable_SSC_DDT04 1 bit ; panel #04, 0=Disable, 1=Enable +$Disable_SSC_DDT05 1 bit ; panel #05, 0=Disable, 1=Enable +$Disable_SSC_DDT06 1 bit ; panel #06, 0=Disable, 1=Enable +$Disable_SSC_DDT07 1 bit ; panel #07, 0=Disable, 1=Enable +$Disable_SSC_DDT08 1 bit ; panel #08, 0=Disable, 1=Enable +$Disable_SSC_DDT09 1 bit ; panel #09, 0=Disable, 1=Enable +$Disable_SSC_DDT10 1 bit ; panel #10, 0=Disable, 1=Enable +$Disable_SSC_DDT11 1 bit ; panel #11, 0=Disable, 1=Enable +$Disable_SSC_DDT12 1 bit ; panel #12, 0=Disable, 1=Enable +$Disable_SSC_DDT13 1 bit ; panel #13, 0=Disable, 1=Enable +$Disable_SSC_DDT14 1 bit ; panel #14, 0=Disable, 1=Enable +$Disable_SSC_DDT15 1 bit ; panel #15, 0=Disable, 1=Enable +$Disable_SSC_DDT16 1 bit ; panel #16, 0=Disable, 1=Enable + +$INT_Panel_Color_Depth01 1 bit ; Panel #01, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth02 1 bit ; Panel #02, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth03 1 bit ; Panel #03, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth04 1 bit ; Panel #04, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth05 1 bit ; Panel #05, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth06 1 bit ; Panel #06, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth07 1 bit ; Panel #07, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth08 1 bit ; Panel #08, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth09 1 bit ; Panel #09, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth10 1 bit ; Panel #10, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth11 1 bit ; Panel #11, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth12 1 bit ; Panel #12, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth13 1 bit ; Panel #13, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth14 1 bit ; Panel #14, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth15 1 bit ; Panel #15, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth16 1 bit ; Panel #16, 0 = 18bpps, 1 = 24bpps + +$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless + +$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight + + +;============================================================================== +; Block 41 - Flat Panel Data Tables Pointers +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; SKIP block ID and size +SKIP 1 byte ; Skip entries number byte + +$LVDS_Tbl_Ptr_01 2 bytes +$LVDS_Tbl_Size_01 1 byte +$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes +$DVO_Tbl_Ptr_01 2 bytes +$DVO_Tbl_Size_01 1 byte +$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte +$LVDS_PnP_ID_Ptr_01 2 bytes +$LVDS_PnP_ID_Size_01 1 byte +$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte + +$LVDS_Tbl_Ptr_02 2 bytes +$LVDS_Tbl_Size_02 1 byte +$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes +$DVO_Tbl_Ptr_02 2 bytes +$DVO_Tbl_Size_02 1 byte +$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte +$LVDS_PnP_ID_Ptr_02 2 bytes +$LVDS_PnP_ID_Size_02 1 byte +$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte + +$LVDS_Tbl_Ptr_03 2 bytes +$LVDS_Tbl_Size_03 1 byte +$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes +$DVO_Tbl_Ptr_03 2 bytes +$DVO_Tbl_Size_03 1 byte +$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte +$LVDS_PnP_ID_Ptr_03 2 bytes +$LVDS_PnP_ID_Size_03 1 byte +$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte + +$LVDS_Tbl_Ptr_04 2 bytes +$LVDS_Tbl_Size_04 1 byte +$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes +$DVO_Tbl_Ptr_04 2 bytes +$DVO_Tbl_Size_04 1 byte +$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte +$LVDS_PnP_ID_Ptr_04 2 bytes +$LVDS_PnP_ID_Size_04 1 byte +$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte + +$LVDS_Tbl_Ptr_05 2 bytes +$LVDS_Tbl_Size_05 1 byte +$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes +$DVO_Tbl_Ptr_05 2 bytes +$DVO_Tbl_Size_05 1 byte +$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte +$LVDS_PnP_ID_Ptr_05 2 bytes +$LVDS_PnP_ID_Size_05 1 byte +$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte + +$LVDS_Tbl_Ptr_06 2 bytes +$LVDS_Tbl_Size_06 1 byte +$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes +$DVO_Tbl_Ptr_06 2 bytes +$DVO_Tbl_Size_06 1 byte +$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte +$LVDS_PnP_ID_Ptr_06 2 bytes +$LVDS_PnP_ID_Size_06 1 byte +$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte + +$LVDS_Tbl_Ptr_07 2 bytes +$LVDS_Tbl_Size_07 1 byte +$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes +$DVO_Tbl_Ptr_07 2 bytes +$DVO_Tbl_Size_07 1 byte +$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte +$LVDS_PnP_ID_Ptr_07 2 bytes +$LVDS_PnP_ID_Size_07 1 byte +$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte + +$LVDS_Tbl_Ptr_08 2 bytes +$LVDS_Tbl_Size_08 1 byte +$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes +$DVO_Tbl_Ptr_08 2 bytes +$DVO_Tbl_Size_08 1 byte +$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte +$LVDS_PnP_ID_Ptr_08 2 bytes +$LVDS_PnP_ID_Size_08 1 byte +$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte + +$LVDS_Tbl_Ptr_09 2 bytes +$LVDS_Tbl_Size_09 1 byte +$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes +$DVO_Tbl_Ptr_09 2 bytes +$DVO_Tbl_Size_09 1 byte +$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte +$LVDS_PnP_ID_Ptr_09 2 bytes +$LVDS_PnP_ID_Size_09 1 byte +$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte + +$LVDS_Tbl_Ptr_10 2 bytes +$LVDS_Tbl_Size_10 1 byte +$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes +$DVO_Tbl_Ptr_10 2 bytes +$DVO_Tbl_Size_10 1 byte +$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte +$LVDS_PnP_ID_Ptr_10 2 bytes +$LVDS_PnP_ID_Size_10 1 byte +$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte + +$LVDS_Tbl_Ptr_11 2 bytes +$LVDS_Tbl_Size_11 1 byte +$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes +$DVO_Tbl_Ptr_11 2 bytes +$DVO_Tbl_Size_11 1 byte +$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte +$LVDS_PnP_ID_Ptr_11 2 bytes +$LVDS_PnP_ID_Size_11 1 byte +$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte + +$LVDS_Tbl_Ptr_12 2 bytes +$LVDS_Tbl_Size_12 1 byte +$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes +$DVO_Tbl_Ptr_12 2 bytes +$DVO_Tbl_Size_12 1 byte +$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte +$LVDS_PnP_ID_Ptr_12 2 bytes +$LVDS_PnP_ID_Size_12 1 byte +$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte + +$LVDS_Tbl_Ptr_13 2 bytes +$LVDS_Tbl_Size_13 1 byte +$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes +$DVO_Tbl_Ptr_13 2 bytes +$DVO_Tbl_Size_13 1 byte +$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte +$LVDS_PnP_ID_Ptr_13 2 bytes +$LVDS_PnP_ID_Size_13 1 byte +$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte + +$LVDS_Tbl_Ptr_14 2 bytes +$LVDS_Tbl_Size_14 1 byte +$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes +$DVO_Tbl_Ptr_14 2 bytes +$DVO_Tbl_Size_14 1 byte +$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte +$LVDS_PnP_ID_Ptr_14 2 bytes +$LVDS_PnP_ID_Size_14 1 byte +$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte + +$LVDS_Tbl_Ptr_15 2 bytes +$LVDS_Tbl_Size_15 1 byte +$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes +$DVO_Tbl_Ptr_15 2 bytes +$DVO_Tbl_Size_15 1 byte +$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte +$LVDS_PnP_ID_Ptr_15 2 bytes +$LVDS_PnP_ID_Size_15 1 byte +$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte + +$LVDS_Tbl_Ptr_16 2 bytes +$LVDS_Tbl_Size_16 1 byte +$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes +$DVO_Tbl_Ptr_16 2 bytes +$DVO_Tbl_Size_16 1 byte +$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte +$LVDS_PnP_ID_Ptr_16 2 bytes +$LVDS_PnP_ID_Size_16 1 byte +$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte + +SKIP 2 bytes ;LfpPanelNameTable Offset +SKIP 1 byte ;LfpPanelName Length + + + +;============================================================================== +; Block 42 - Flat Panel Data Tables +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + + ; Flat Panel #1 + +$Panel_Width_01 2 bytes ; Panel Width +$Panel_Height_01 2 bytes ; Panel Height + +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither01 1 bit ; Panel #01, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ; address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_01 13 bits ; Power on Backlight Enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_01 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ; address-0x6120C or 0x0C720C (for ILM) -Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_01 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_01 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM) -Panel power cycle delay and reference divider +$PowerCycleDelay_01 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +ALIGN +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end + +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #2 + +$Panel_Width_02 2 bytes ; Panel Width +$Panel_Height_02 2 bytes ; Panel Height + +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither02 1 bit ; Panel #02, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_02 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_02 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_02 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_02 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_02 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #3 + +$Panel_Width_03 2 bytes ; Panel Width +$Panel_Height_03 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither03 1 bit ; Panel #03, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_03 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_03 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_03 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_03 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;aaddress-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_03 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #4 + +$Panel_Width_04 2 bytes ; Panel Width +$Panel_Height_04 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither04 1 bit ; Panel #04, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_04 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_04 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_04 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_04 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_04 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #5 + +$Panel_Width_05 2 bytes ; Panel Width +$Panel_Height_05 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither05 1 bit ; Panel #05, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_05 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_05 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_05 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_05 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_05 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #6 + +$Panel_Width_06 2 bytes ; Panel Width +$Panel_Height_06 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither06 1 bit ; Panel #06, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_06 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_06 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_06 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_06 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_06 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #7 + +$Panel_Width_07 2 bytes ; Panel Width +$Panel_Height_07 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither07 1 bit ; Panel #07, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_07 13 bits ; Power on Backlight enable delay delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_07 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_07 13 bits ; Backlight off delay power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_07 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_07 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #8 + +$Panel_Width_08 2 bytes ; Panel Width +$Panel_Height_08 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither08 1 bit ; Panel #08, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_08 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_08 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_08 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_08 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_08 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #9 + +$Panel_Width_09 2 bytes ; Panel Width +$Panel_Height_09 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither09 1 bit ; Panel #09, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_09 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_09 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_09 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_09 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_09 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #10 + +$Panel_Width_10 2 bytes ; Panel Width +$Panel_Height_10 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither10 1 bit ; Panel #10, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_10 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_10 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_10 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_10 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_10 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #11 + +$Panel_Width_11 2 bytes ; Panel Width +$Panel_Height_11 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither11 1 bit ; Panel #11, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_11 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_11 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_11 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_11 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_11 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #12 + +$Panel_Width_12 2 bytes ; Panel Width +$Panel_Height_12 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither12 1 bit ; Panel #12, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_12 13 bits ; Powen on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_12 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_12 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_12 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_12 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #13 + +$Panel_Width_13 2 bytes ; Panel Width +$Panel_Height_13 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither13 1 bit ; Panel #13, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_13 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_13 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_13 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_13 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_13 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #14 + +$Panel_Width_14 2 bytes ; Panel Width +$Panel_Height_14 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither14 1 bit ; Panel #14, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_14 13 bits ; Power on baklight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_14 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_14 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_14 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_14 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #15 + +$Panel_Width_15 2 bytes ; Panel Width +$Panel_Height_15 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither15 1 bit ; Panel #15, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_15 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_15 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_15 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_15 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_15 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #16 + +$Panel_Width_16 2 bytes ; Panel Width +$Panel_Height_16 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither16 1 bit ; Panel #16, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_16 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_16 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_16 13 bits ; backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_16 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_16 5 bits ; Power cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + +$Panel_Name_01 13 bytes ; LFP Panel Name +$Panel_Name_02 13 bytes ; LFP Panel Name +$Panel_Name_03 13 bytes ; LFP Panel Name +$Panel_Name_04 13 bytes ; LFP Panel Name +$Panel_Name_05 13 bytes ; LFP Panel Name +$Panel_Name_06 13 bytes ; LFP Panel Name +$Panel_Name_07 13 bytes ; LFP Panel Name +$Panel_Name_08 13 bytes ; LFP Panel Name +$Panel_Name_09 13 bytes ; LFP Panel Name +$Panel_Name_10 13 bytes ; LFP Panel Name +$Panel_Name_11 13 bytes ; LFP Panel Name +$Panel_Name_12 13 bytes ; LFP Panel Name +$Panel_Name_13 13 bytes ; LFP Panel Name +$Panel_Name_14 13 bytes ; LFP Panel Name +$Panel_Name_15 13 bytes ; LFP Panel Name +$Panel_Name_16 13 bytes ; LFP Panel Name + +$Enable_Scaling_01 1 bit ; Scaling Enable bit for Panel#1 +$Enable_Scaling_02 1 bit ; Scaling Enable bit for Panel#2 +$Enable_Scaling_03 1 bit ; Scaling Enable bit for Panel#3 +$Enable_Scaling_04 1 bit ; Scaling Enable bit for Panel#4 +$Enable_Scaling_05 1 bit ; Scaling Enable bit for Panel#5 +$Enable_Scaling_06 1 bit ; Scaling Enable bit for Panel#6 +$Enable_Scaling_07 1 bit ; Scaling Enable bit for Panel#7 +$Enable_Scaling_08 1 bit ; Scaling Enable bit for Panel#8 +$Enable_Scaling_09 1 bit ; Scaling Enable bit for Panel#9 +$Enable_Scaling_10 1 bit ; Scaling Enable bit for Panel#10 +$Enable_Scaling_11 1 bit ; Scaling Enable bit for Panel#11 +$Enable_Scaling_12 1 bit ; Scaling Enable bit for Panel#12 +$Enable_Scaling_13 1 bit ; Scaling Enable bit for Panel#13 +$Enable_Scaling_14 1 bit ; Scaling Enable bit for Panel#14 +$Enable_Scaling_15 1 bit ; Scaling Enable bit for Panel#15 +$Enable_Scaling_16 1 bit ; Scaling Enable bit for Panel#16 + +$Seamless_DRRS_Min_RR_01 1 byte ; Seamless DRRS Min Refresh Rate for Panel#1 +$Seamless_DRRS_Min_RR_02 1 byte ; Seamless DRRS Min Refresh Rate for Panel#2 +$Seamless_DRRS_Min_RR_03 1 byte ; Seamless DRRS Min Refresh Rate for Panel#3 +$Seamless_DRRS_Min_RR_04 1 byte ; Seamless DRRS Min Refresh Rate for Panel#4 +$Seamless_DRRS_Min_RR_05 1 byte ; Seamless DRRS Min Refresh Rate for Panel#5 +$Seamless_DRRS_Min_RR_06 1 byte ; Seamless DRRS Min Refresh Rate for Panel#6 +$Seamless_DRRS_Min_RR_07 1 byte ; Seamless DRRS Min Refresh Rate for Panel#7 +$Seamless_DRRS_Min_RR_08 1 byte ; Seamless DRRS Min Refresh Rate for Panel#8 +$Seamless_DRRS_Min_RR_09 1 byte ; Seamless DRRS Min Refresh Rate for Panel#9 +$Seamless_DRRS_Min_RR_10 1 byte ; Seamless DRRS Min Refresh Rate for Panel#10 +$Seamless_DRRS_Min_RR_11 1 byte ; Seamless DRRS Min Refresh Rate for Panel#11 +$Seamless_DRRS_Min_RR_12 1 byte ; Seamless DRRS Min Refresh Rate for Panel#12 +$Seamless_DRRS_Min_RR_13 1 byte ; Seamless DRRS Min Refresh Rate for Panel#13 +$Seamless_DRRS_Min_RR_14 1 byte ; Seamless DRRS Min Refresh Rate for Panel#14 +$Seamless_DRRS_Min_RR_15 1 byte ; Seamless DRRS Min Refresh Rate for Panel#15 +$Seamless_DRRS_Min_RR_16 1 byte ; Seamless DRRS Min Refresh Rate for Panel#16 + +;============================================================================== +; Block 43 - BLC (Backlight Control) Support +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 1 byte ; Skip row size + + ; Flat Panel #1 +$BLC_Inv_Type_1 2 bits ; BLC inverter type +$BLC_Inv_Polarity_1 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_1 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_1 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_1 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_1 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_1 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_1 1 byte ; I2C inverter command code + + + ; Flat Panel #2 +$BLC_Inv_Type_2 2 bits ; BLC inverter type +$BLC_Inv_Polarity_2 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_2 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_2 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_2 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_2 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_2 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_2 1 byte ; I2C inverter command code + + ; Flat Panel #3 +$BLC_Inv_Type_3 2 bits ; BLC inverter type +$BLC_Inv_Polarity_3 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_3 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_3 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_3 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_3 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_3 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_3 1 byte ; I2C inverter command code + + + ; Flat Panel #4 +$BLC_Inv_Type_4 2 bits ; BLC inverter type +$BLC_Inv_Polarity_4 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_4 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_4 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_4 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_4 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_4 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_4 1 byte ; I2C inverter command code + + ; Flat Panel #5 +$BLC_Inv_Type_5 2 bits ; BLC inverter type +$BLC_Inv_Polarity_5 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_5 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_5 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_5 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_5 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_5 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_5 1 byte ; I2C inverter command code + + + ; Flat Panel #6 +$BLC_Inv_Type_6 2 bits ; BLC inverter type +$BLC_Inv_Polarity_6 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_6 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_6 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_6 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_6 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_6 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_6 1 byte ; I2C inverter command code + + ; Flat Panel #7 +$BLC_Inv_Type_7 2 bits ; BLC inverter type +$BLC_Inv_Polarity_7 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_7 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_7 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_7 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_7 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_7 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_7 1 byte ; I2C inverter command code + + + ; Flat Panel #8 +$BLC_Inv_Type_8 2 bits ; BLC inverter type +$BLC_Inv_Polarity_8 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_8 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_8 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_8 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_8 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_8 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_8 1 byte ; I2C inverter command code + + + ; Flat Panel #9 +$BLC_Inv_Type_9 2 bits ; BLC inverter type +$BLC_Inv_Polarity_9 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_9 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_9 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_9 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_9 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_9 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_9 1 byte ; I2C inverter command code + + ; Flat Panel #10 +$BLC_Inv_Type_10 2 bits ; BLC inverter type +$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_10 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code + + + ; Flat Panel #11 +$BLC_Inv_Type_11 2 bits ; BLC inverter type +$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_11 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code + + + ; Flat Panel #12 +$BLC_Inv_Type_12 2 bits ; BLC inverter type +$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_12 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code + + ; Flat Panel #13 +$BLC_Inv_Type_13 2 bits ; BLC inverter type +$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_13 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code + + + ; Flat Panel #14 +$BLC_Inv_Type_14 2 bits ; BLC inverter type +$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_14 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code + + + ; Flat Panel #15 +$BLC_Inv_Type_15 2 bits ; BLC inverter type +$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_15 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code + + + ; Flat Panel #16 +$BLC_Inv_Type_16 2 bits ; BLC inverter type +$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_16 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code + +$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #1 + $POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #2 + $POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #3 + $POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #4 + $POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #5 + $POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #6 + $POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #7 + $POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #8 + $POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #9 + $POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 + $POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 + $POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 + $POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 + $POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 + $POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 + $POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 + + $Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 + $Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 + + $Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 + $Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 + + $Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 + $Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 + + $Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 + $Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 + + $Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 + $Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 + + $Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 + $Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 + + $Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 + $Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 + + $Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 + $Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 + + $Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 + $Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 + + $Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 + $Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 + + $Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 + $Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 + + $Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 + $Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 + + $Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 + $Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 + + $Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 + $Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 + + $Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 + $Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 + + $Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 + $Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 + +;============================================================================== +; Block 44 - BIA (Backlight Image Adaption) Support +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$BIA_Enable 1 bit ; DPST support enable bit +$BIA_Aggress_Level 3 bits ; Power Conservation Preference level +SKIP 3 bits ; Reserved +$ALS_Enable 1 bit ; ALS enable bit +$ALS_Response_Data 20 bytes ; ALS Response Data + + ;============================================================================== + ; Block 46 - Chromaticity Support + ;------------------------------------------------------------------------------ + + SKIP 3 bytes ; Skip block ID and size + + + $Chromacity_Enable_1 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_1 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_1 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_1 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_1 1 byte ; Red x coordinate at 1Bh + $Red_y_1 1 byte ; Red y coordinate at 1Ch + $Green_x_1 1 byte ; Green x coordinate at 1Dh + $Green_y_1 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_1 1 byte ; Blue x coordinate at 1Fh + $Blue_y_1 1 byte ; Blue y coordinate at 20h + $White_x_1 1 byte ; White x coordiante at 21h + $White_y_1 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_2 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_2 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_2 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_2 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_2 1 byte ; Red x coordinate at 1Bh + $Red_y_2 1 byte ; Red y coordinate at 1Ch + $Green_x_2 1 byte ; Green x coordinate at 1Dh + $Green_y_2 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_2 1 byte ; Blue x coordinate at 1Fh + $Blue_y_2 1 byte ; Blue y coordinate at 20h + $White_x_2 1 byte ; White x coordiante at 21h + $White_y_2 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_3 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_3 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_3 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_3 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_3 1 byte ; Red x coordinate at 1Bh + $Red_y_3 1 byte ; Red y coordinate at 1Ch + $Green_x_3 1 byte ; Green x coordinate at 1Dh + $Green_y_3 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_3 1 byte ; Blue x coordinate at 1Fh + $Blue_y_3 1 byte ; Blue y coordinate at 20h + $White_x_3 1 byte ; White x coordiante at 21h + $White_y_3 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_4 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_4 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_4 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_4 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_4 1 byte ; Red x coordinate at 1Bh + $Red_y_4 1 byte ; Red y coordinate at 1Ch + $Green_x_4 1 byte ; Green x coordinate at 1Dh + $Green_y_4 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_4 1 byte ; Blue x coordinate at 1Fh + $Blue_y_4 1 byte ; Blue y coordinate at 20h + $White_x_4 1 byte ; White x coordiante at 21h + $White_y_4 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_5 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_5 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_5 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_5 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_5 1 byte ; Red x coordinate at 1Bh + $Red_y_5 1 byte ; Red y coordinate at 1Ch + $Green_x_5 1 byte ; Green x coordinate at 1Dh + $Green_y_5 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_5 1 byte ; Blue x coordinate at 1Fh + $Blue_y_5 1 byte ; Blue y coordinate at 20h + $White_x_5 1 byte ; White x coordiante at 21h + $White_y_5 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_6 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_6 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_6 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_6 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_6 1 byte ; Red x coordinate at 1Bh + $Red_y_6 1 byte ; Red y coordinate at 1Ch + $Green_x_6 1 byte ; Green x coordinate at 1Dh + $Green_y_6 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_6 1 byte ; Blue x coordinate at 1Fh + $Blue_y_6 1 byte ; Blue y coordinate at 20h + $White_x_6 1 byte ; White x coordiante at 21h + $White_y_6 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_7 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_7 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_7 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_7 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_7 1 byte ; Red x coordinate at 1Bh + $Red_y_7 1 byte ; Red y coordinate at 1Ch + $Green_x_7 1 byte ; Green x coordinate at 1Dh + $Green_y_7 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_7 1 byte ; Blue x coordinate at 1Fh + $Blue_y_7 1 byte ; Blue y coordinate at 20h + $White_x_7 1 byte ; White x coordiante at 21h + $White_y_7 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_8 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_8 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_8 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_8 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_8 1 byte ; Red x coordinate at 1Bh + $Red_y_8 1 byte ; Red y coordinate at 1Ch + $Green_x_8 1 byte ; Green x coordinate at 1Dh + $Green_y_8 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_8 1 byte ; Blue x coordinate at 1Fh + $Blue_y_8 1 byte ; Blue y coordinate at 20h + $White_x_8 1 byte ; White x coordiante at 21h + $White_y_8 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_9 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_9 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_9 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_9 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_9 1 byte ; Red x coordinate at 1Bh + $Red_y_9 1 byte ; Red y coordinate at 1Ch + $Green_x_9 1 byte ; Green x coordinate at 1Dh + $Green_y_9 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_9 1 byte ; Blue x coordinate at 1Fh + $Blue_y_9 1 byte ; Blue y coordinate at 20h + $White_x_9 1 byte ; White x coordiante at 21h + $White_y_9 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_10 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_10 1 byte ; Red x coordinate at 1Bh + $Red_y_10 1 byte ; Red y coordinate at 1Ch + $Green_x_10 1 byte ; Green x coordinate at 1Dh + $Green_y_10 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_10 1 byte ; Blue x coordinate at 1Fh + $Blue_y_10 1 byte ; Blue y coordinate at 20h + $White_x_10 1 byte ; White x coordiante at 21h + $White_y_10 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_11 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_11 1 byte ; Red x coordinate at 1Bh + $Red_y_11 1 byte ; Red y coordinate at 1Ch + $Green_x_11 1 byte ; Green x coordinate at 1Dh + $Green_y_11 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_11 1 byte ; Blue x coordinate at 1Fh + $Blue_y_11 1 byte ; Blue y coordinate at 20h + $White_x_11 1 byte ; White x coordiante at 21h + $White_y_11 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_12 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_12 1 byte ; Red x coordinate at 1Bh + $Red_y_12 1 byte ; Red y coordinate at 1Ch + $Green_x_12 1 byte ; Green x coordinate at 1Dh + $Green_y_12 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_12 1 byte ; Blue x coordinate at 1Fh + $Blue_y_12 1 byte ; Blue y coordinate at 20h + $White_x_12 1 byte ; White x coordiante at 21h + $White_y_12 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_13 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_13 1 byte ; Red x coordinate at 1Bh + $Red_y_13 1 byte ; Red y coordinate at 1Ch + $Green_x_13 1 byte ; Green x coordinate at 1Dh + $Green_y_13 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_13 1 byte ; Blue x coordinate at 1Fh + $Blue_y_13 1 byte ; Blue y coordinate at 20h + $White_x_13 1 byte ; White x coordiante at 21h + $White_y_13 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_14 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_14 1 byte ; Red x coordinate at 1Bh + $Red_y_14 1 byte ; Red y coordinate at 1Ch + $Green_x_14 1 byte ; Green x coordinate at 1Dh + $Green_y_14 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_14 1 byte ; Blue x coordinate at 1Fh + $Blue_y_14 1 byte ; Blue y coordinate at 20h + $White_x_14 1 byte ; White x coordiante at 21h + $White_y_14 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_15 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_15 1 byte ; Red x coordinate at 1Bh + $Red_y_15 1 byte ; Red y coordinate at 1Ch + $Green_x_15 1 byte ; Green x coordinate at 1Dh + $Green_y_15 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_15 1 byte ; Blue x coordinate at 1Fh + $Blue_y_15 1 byte ; Blue y coordinate at 20h + $White_x_15 1 byte ; White x coordiante at 21h + $White_y_15 1 byte ; White y coordinate at 22h + + + $Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_16 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_16 1 byte ; Red x coordinate at 1Bh + $Red_y_16 1 byte ; Red y coordinate at 1Ch + $Green_x_16 1 byte ; Green x coordinate at 1Dh + $Green_y_16 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_16 1 byte ; Blue x coordinate at 1Fh + $Blue_y_16 1 byte ; Blue y coordinate at 20h + $White_x_16 1 byte ; White x coordiante at 21h + $White_y_16 1 byte ; White y coordinate at 22h + +;============================================================================== +; Block 51 - Fixed Mode +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Feature_Enable 1 byte ; enable or disable the feature +$X_res 4 bytes ; X resolution +$Y_res 4 bytes ; Y resolution + +;============================================================================== +; Block 54 - RGB Palette enteries +;------------------------------------------------------------------------------ +SKIP 3 bytes ;block ID/size + +$Enable_Correction 1 bit +SKIP 7 bits + +$Red_Table 256 bytes +$Green_Table 256 bytes +$Blue_Table 256 bytes + +EndStruct + +;============================================================================== +; List Definitions +;------------------------------------------------------------------------------ + +List &Disabled_Enabled_List + Selection 0, "Disabled" + Selection 1, "Enabled" +EndList + +List &Pwr_Pref_List + Selection 0x01, "1 - Maximum Quality with No DPST" + Selection 0x02, "2" + Selection 0x03, "3" + Selection 0x04, "4" + Selection 0x05, "5" + Selection 0x06, "6 - Maximum Battery" +EndList + +List &Cls_After_Signon_List + Selection 0x00, "No CLS" + Selection 0x01, "0.5 Second Delay + CLS" + Selection 0x02, "1.0 Second Delay + CLS" + Selection 0x03, "1.5 Second Delay + CLS" + Selection 0x04, "2.0 Second Delay + CLS" + Selection 0x05, "2.5 Second Delay + CLS" + Selection 0x06, "3.0 Second Delay + CLS" + Selection 0x07, "3.5 Second Delay + CLS" +EndList + +List &Int_CRT_Device_Type_List + Selection 0x0000, "No Device" + Selection 0x0001, "CRT" + ;Selection 0x0011, "DVI with CRT" +EndList + +List &Int_EFP_Device_Type_List + Selection 0x0000, "No Device" + Selection 0x68C6, "DisplayPort" + Selection 0x60D2, "HDMI/DVI" + Selection 0x68D2, "Integrated DVI Only" + Selection 0x60D6, "DisplayPort with HDMI/DVI Compatible" + Selection 0x68D6, "DisplayPort with DVI Compatible" + ; Selection 0x68D3, "DVI with CRT" +EndList + +List &CRT_Device_Id_List + Selection 01h, "CRT" +EndList + +List &EFP1_Device_Id_List + Selection 04h, "EFP 1" + Selection 40h, "EFP 2" + Selection 08h, "LFP" + ;Selection 80h, "LFP 2" +EndList + +List &EFP2_Device_Id_List + Selection 04h, "EFP 1" + Selection 40h, "EFP 2" + Selection 08h, "LFP" + ;Selection 80h, "LFP 2" +EndList + +List &LVDS_Device_Id_List + Selection 08h, "LFP" +EndList + +List &DOS_Boot_Mode_List + Selection 0x03, "03h" + Selection 0x12, "12h" + Selection 0x13, "13h" + Selection 0x30, "30h" + Selection 0x32, "32h" + Selection 0x34, "34h" + Selection 0x40, "40h" + Selection 0x41, "41h" + Selection 0x42, "42h" + Selection 0x43, "43h" + Selection 0x44, "44h" + Selection 0x45, "45h" + Selection 0x50, "50h" + Selection 0x52, "52h" + Selection 0x54, "54h" +EndList + +List &LFP_Port_list + Selection 0x07, "eDP Port B" + Selection 0x08, "eDP Port C" + ;Selection 0x15, "MIPI Port A" + ;Selection 0x17, "MIPI Port C" + +EndList + +List &LVDS_eDP_Port_List + Selection 0x04, "LVDS" + Selection 0x07, "Port B" + Selection 0x08, "Port C" +EndList + + + +List &Int_EFP_Port_List + Selection 0x00, "N/A" + Selection 0x01, "Port B" + Selection 0x02, "Port C" + +EndList + +List &Int_eDP_AUX_Channel_List + Selection 0x00, "N/A" + Selection 0x10, "eDP-B AUX Channel" + Selection 0x20, "eDP-C AUX Channel" +EndList + +List &Int_DP_AUX_Channel_List + Selection 0x00, "N/A" + Selection 0x10, "DisplayPort-B AUX Channel" + Selection 0x20, "DisplayPort-C AUX Channel" +EndList + + + +List &GPIO_Pin_List + Selection 0x00, "N/A" + Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" + Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" + Selection 0x01, "I2C GPIO pins" + Selection 0x02, "Analog CRT DDC GPIO pins" +EndList + + +List &GMBus_Speed_List + Selection 0x01, "50 KHz" + Selection 0x00, "100 KHz" + Selection 0x02, "400 KHz" + Selection 0x03, "1 MHz" +EndList + + +List &Inv_Type_List + Selection 0x00, "None/External" + Selection 0x01, "I2C" + Selection 0x02, "PWM" +EndList + +List &Inv_Polarity_List + Selection 0x00, "Normal" + Selection 0x01, "Inverted" +EndList + +List &IntXXh_List + Selection 0x00, "Disabled" + Selection 0x01, "Use Interrupt 15h" +EndList + +List &LVDS_Channel_List + Selection 0x00, "Single Channel" + Selection 0x01, "Dual Channel" +EndList + +List &INT_LVDS_Channel_List + Selection 0x00, "Automatic Selection" + Selection 0x01, "Single Channel" + Selection 0x02, "Dual Channel" +EndList + +List &LVDS_Config_List + Selection 0x00, "No Device" + Selection 0x1020, "LVDS" +EndList + +List &eDP_Config_List + Selection 0x00, "No Device" + Selection 0x1806, "eDP" + ; Selection 0x1400, "MIPI" +EndList + +List &eDP_LVDS_Config_List + Selection 0x00, "No Device" + Selection 0x1020, "LVDS" + Selection 0x1806, "eDP" +EndList + + +List &No_Yes_List + Selection 0, "No" + Selection 1, "Yes" +EndList + +List &Off_On_List + Selection 0, "Off" + Selection 1, "On" +EndList + +List &OS_Driver_List + Selection 0, "OS Default Algorithm" + Selection 1, "Driver Algorithm" +EndList + +List &OS_DriverP_List + Selection 0, "OS Default Algorithm" + Selection 1, "Driver Persistence Algorithm" +EndList + +List &Panel_Color_Depth_List + Selection 0x00, "18-bit Color Depth" + Selection 0x01, "24-bit Color Depth" +EndList + +List &eDP_Panel_Color_Depth_List + Selection 0x00, "18-bit Color Depth" + Selection 0x01, "24-bit Color Depth" + Selection 0x02, "30-bit Color Depth" +EndList + +List &eDP_Vswing_Preemph_table_List + Selection 0x00, "Low power Swing Setting" + Selection 0x01, "Default Swing Setting" +EndList + +List &eDP_Link_DataRate_List + Selection 0x00, "1.62 Gbps" + Selection 0x01, "2.70 Gbps" +EndList + +List &eDP_Link_LaneCount_List + Selection 0x00, "x1" + Selection 0x01, "x2" + Selection 0x03, "x4" +EndList + +List &eDP_Link_PreEmp_List + Selection 0x00, "Level 0" + Selection 0x01, "Level 1" + Selection 0x02, "Level 2" + Selection 0x03, "Level 3" +EndList + +List &eDP_Link_VSwing_List + Selection 0x00, "Level 0" + Selection 0x01, "Level 1" + Selection 0x02, "Level 2" + Selection 0x03, "Level 3" +EndList + + +List &Panel_Connector_List + Selection 0x00, "SPGW" + Selection 0x01, "OpenLDI" +EndList + +List &Panel_List + Selection 0x00, "PANEL #01" + Selection 0x01, "PANEL #02" + Selection 0x02, "PANEL #03" + Selection 0x03, "PANEL #04" + Selection 0x04, "PANEL #05" + Selection 0x05, "PANEL #06" + Selection 0x06, "PANEL #07" + Selection 0x07, "PANEL #08" + Selection 0x08, "PANEL #09" + Selection 0x09, "PANEL #10" + Selection 0x0A, "PANEL #11" + Selection 0x0B, "PANEL #12" + Selection 0x0C, "PANEL #13" + Selection 0x0D, "PANEL #14" + Selection 0x0E, "PANEL #15" + Selection 0x0F, "PANEL #16" +EndList + + +List &Panel_Stretch_List + Selection 0x00, "Disable Panel Fitting" + Selection 0x01, "Enabled for Text Modes Only" + Selection 0x02, "Enabled for Graphics Modes Only" + Selection 0x03, "Enabled for Both Text and Graphics Modes" +EndList + +List &PCI_BIOS_Disabled_Enabled_List + Selection 0x00, "Disabled" + Selection 0x01, "Resize to 0.5K boundary" + Selection 0x20, "Resize to 16K boundary" +EndList + +List &RelStage + Selection 1, "Production" + Selection 254, "Evaluation" +EndList + +List &Power_Scheme_List + Selection 0, "CUI" + Selection 1, "3rd Party Application" +EndList + +List &Render_Freq_List + Selection 0, "High Frequency" + Selection 1, "Low Frequency" +EndList + +List &SSC_List + Selection 0, "96 MHz" + Selection 1, "100 MHz" +EndList + +List &SDVO_Panel_List + Selection 0x00, "PANEL #01" + Selection 0x01, "PANEL #02" + Selection 0x02, "PANEL #03" + Selection 0x03, "PANEL #04" +EndList + +List &Yes_No_List + Selection 0, "Yes" + Selection 1, "No" +EndList + +List &Sprite_Display_List + Selection 0, "Secondary Display" + Selection 1, "Primary Display" +EndList + +List &Under_Over_List + Selection 0x0, "Enable Underscan and Overscan modes" + Selection 0x1, "Enable only overscan modes" + Selection 0x2, "Enable only underscan modes" +EndList + +List &Inter_Exter_List + Selection 0, "External Termination" + Selection 1, "Internal Termination" +EndList + +List &DPS_Panel_Type_List + Selection 0x00, "Static DRRS" + Selection 0x02, "Seamless" +EndList + +List &MSA_TimingDelay_List + Selection 0x00, "Line 1" + Selection 0x01, "Line 2" + Selection 0x02, "Line 3" + Selection 0x03, "Line 4" +EndList + +List &Blt_Control_Type_List + ;Selection 0x00, "Default" + Selection 0x01, "CCFL Backlight" + Selection 0x02, "LED Backlight" +EndList + + +List &Mode_Preferred_List + Selection 0x00, "Mode Timing" + Selection 0x01, "Preferred Timing" +EndList + +List &DisplayList + Selection 0x08, "LFP" +; Selection 0x80, "LFP 2" + Selection 0x01, "CRT" + Selection 0x04, "EFP 1" + Selection 0x40, "EFP 2" +; Selection 0x20, "EFP 3" + Selection 0x00, "None" +EndList + +List &Dither_Select_Bit + Selection 0, "Dithering in Panel controller" + Selection 1, "Dithering in Display Controller" +EndList + +List &MIPI_Bridge_Ref_Clock_List + Selection 0, "19.2" + Selection 1, "26" +EndList + +List &Panel_Identifier_List + Selection 0x0, "Use Sequence Block" + Selection 0x1, "MIPI DSI Panel-1" + Selection 0x2, "MIPI DSI Panel-2" + Selection 0x3, "MIPI DSI Panel-3" + Selection 0x4, "MIPI DSI Panel-4" + Selection 0x5, "MIPI DSI Panel-5" + Selection 0x6, "MIPI DSI Panel-6" + Selection 0x7, "MIPI DSI Panel-7" + Selection 0x8, "MIPI DSI Panel-8" + ;Selection 0x9, "MIPI DSI Panel-9" + ;Selection 0xA, "MIPI DSI Panel-10" + ;Selection 0xB, "MIPI DSI Panel-11" + ;Selection 0xC, "MIPI DSI Panel-12" + ;Selection 0xD, "MIPI DSI Panel-13" + ;Selection 0xE, "MIPI DSI Panel-14" + ;Selection 0xF, "MIPI DSI Panel-15" + ;Selection 0x10, "MIPI DSI Panel-16" +EndList + +List &Panel_Type_List + Selection 0, "Native MIPI DSI" + Selection 1, "MIPI DSI to LVDS Bridge" +EndList + +List &MIPI_DSI_Panel_Architecture_Type_List + Selection 0x0, "Type 1" + Selection 0x1, "Type 2" + Selection 0x2, "Type 3" + Selection 0x3, "Type 4" +EndList + +List &Video_Command_Mode_List + Selection 0, "Video Mode" + Selection 1, "Command Mode" +EndList + +List &Packet_Sequence_Video_Mode_List + ;Selection 0x0, "Reserved" + Selection 0x1, "Non-burst with sync pulse" + Selection 0x2, "Non-burst with sync events" + Selection 0x3, "Burst Mode" +EndList + +List &Colour_Format_Video_Mode_List + Selection 0x1, "RGB565" + Selection 0x2, "RGB666" + Selection 0x3, "RGB 666(Loosely Packed Format)" + Selection 0x4, "RGB888" +EndList + +List &Panel_Rotation_List + Selection 0x0, "0 degree" + Selection 0x1, "90 degree" + Selection 0x2, "180 degree" + Selection 0x3, "270 degree" +EndList + +List &Enable_Disable_List + Selection 0, "Enable" + Selection 1, "Disable" +EndList + +List &EscapeClk_List + Selection 0x0, "20 MHz" + Selection 0x1, "10 MHz" + Selection 0x2, "5 MHz" + ;Selection 0x3, "Undefined" +EndList + +List &DPhyParamFlag_List + Selection 0, "Dphy Param is not valid" + Selection 1, "Dphy Param is valid" +EndList + +List &MIPI_DSI_Panel_Color_Depth_List + Selection 0x0, "18Bpp" + Selection 0x1, "24Bpp" +EndList + +List &Lane_Count_List + Selection 0x0, "1" + Selection 0x1, "2" + Selection 0x2, "3" + Selection 0x3, "4" +EndList + +List &Dual_Link_List + Selection 0x0, "Dual Link Not Supported" + Selection 0x1, "Dual Link Front Back Mode" + Selection 0x2, "Dual Link Pixel Alternative Mode" + ;Selection 0x3, "Reserved" +EndList + +List &Hdmi_LS_List_VLV + Selection 0x00, "1000mV -2.0dB" + Selection 0x01, "1000mV 0.0dB" + Selection 0x02, "800mV 0.0dB" + Selection 0x03, "600mV 2.0dB" + Selection 0x04, "600mV 0.0dB" +EndList + +List &Edp_Pwm_Source_List + Selection 0x1, "LPSS PWM" + Selection 0x2, "DISPLAY PWM" +EndList + +;============================================================================== +; Page Definitions +;------------------------------------------------------------------------------ + +BeginInfoBlock + PPVer "2.01" + Image EOF Thru EOF At EOF +EndInfoBlock + + +;============================================================================== +; Page - VBT version +;------------------------------------------------------------------------------ + +Page "VBT version" + + Title "PLATFORM : Valleyview" + Title "VBT version: 191" + +EndPage ; VBT version + + + +;============================================================================== +; Page - UEFI GOP Driver Configuration +;------------------------------------------------------------------------------ + +Page "UEFI GOP Driver Configuration" + + ;Combo $Hotplug_Support_Enb, " Hot Plug Support:", &Disabled_Enabled_List, + ;Help "This feature is to enable/disable Hot Plug Suppport for CRT/DP/HDMI displays " + + Title "Child Device Configuration" + Link "Child Device List", "Child Device List" + +Title "Fixed Mode" +Link "Fixed Mode Feature", "Fixed Mode Feature" + + ;============================================================================== + ; Page - Boot Display Algorithm + ;------------------------------------------------------------------------------ + + Page "Child Device List" + + Title "Select the child devices that the GOP driver should enumerate if detected." + Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify " + "the child device to start, then GOP driver selects the highest priority child device" + + Link "Close Window", ".." + + Title "Child Device 1" + Combo $ChildDevice1Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice1Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 2" + Combo $ChildDevice2Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice2Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 3" + Combo $ChildDevice3Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice3Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 4" + Combo $ChildDevice4Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice4Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 5" + Combo $ChildDevice5Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice5Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 6" + Combo $ChildDevice6Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice6Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 7" + Combo $ChildDevice7Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice7Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 8" + Combo $ChildDevice8Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice8Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 9" + Combo $ChildDevice9Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice9Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 10" + Combo $ChildDevice10Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice10Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 11" + Combo $ChildDevice11Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice11Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 12" + Combo $ChildDevice12Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice12Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 13" + Combo $ChildDevice13Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice13Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 14" + Combo $ChildDevice14Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice14Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 15" + Combo $ChildDevice15Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice15Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 16" + Combo $ChildDevice16Primary, " Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice16Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + EndPage ;"Child Device List" + +;============================================================================ +; Page - Fixed Mode Configuration +;---------------------------------------------------------------------------- + +Page "Fixed Mode Feature" + Link "Close Table", ".." + Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, + Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set.\r\n" +"This field specifies if user wants to enable/disable the feature.\r\n" +"When enabled user is expected to provide a valid input." + + EditNum $X_res, "Horizontal Pixels:", DEC, + Help "This value specifies the horizontal pixels of the mode. It should be always less than or equal to the native horizontal resolution.\r\n" + + EditNum $Y_res, "Vertical Pixels:", DEC, + Help "This value specifies the vertical pixels of the mode. It should be always less than or equal to the native vertical resolution.\r\n" + +EndPage +EndPage ; "UEFI GOP Driver Configuration" + + +;============================================================================ +; Page - Windows Graphics Driver Configuration +;---------------------------------------------------------------------------- + +Page "Windows Graphics Driver Configuration" + + Link "General Features" , "General Features" + Link "Display Features" , "Display Features" + Link "Power Conservation" , "Power Conservation" + + Page "General Features" + Link "Close Table" , ".." + + EditNum $VBT_Customization_Version, " VBT Customization Version:", DEC, + Help "This feature allows the OEM to have a customized VBT version " + "number. The permissible values for VBT Customization version " + "is from 0 to 255.\r\n" + + Combo $Driver_Boot_Device, " First Boot Display Device:", &OS_Driver_List, + Help "This feature allows the OEM to select which algorithm to " + "follow on the first boot after the driver has been " + "installed.\r\n" + "\r\n" + "OS Default - If this is selected, the operating system's " + "algorithm will be used.\r\n" + "\r\n" + "Driver Default - If this is selected, the boot device will " + "follow the driver algorithm. The expected behavior can be " + "found in the Driver PRD chapter: 'First Boot Default " + "Display Resolutions'." + + ;Combo $Allow_FDOS_Disp_Switch, " Allow Full Screen DOS Display Switching:", &No_Yes_List, + ;Help "This feature allows display switching when the system is in " + ; "full screen DOS. When set to yes, display switching will be " + ; "allowed while system is in full screen DOS. When set to no, " + ; "display switching will be blocked when system is in full " + ;"screen DOS." + + ;Combo $Hot_Plug_DVO, " DVO/SDVO Hot Plug:", &Disabled_Enabled_List, + ;Help "This feature allows the OEM to disable the DVO/SDVO Hot Plug " + ; "capability." + + Combo $Hot_Plug_CRT, " CRT Hot Plug:", &Disabled_Enabled_List, + Help "This feature allows the OEM to disable the CRT Hot Plug " + "capability. This is applicalbe only for driver hotplug in driver environment and not DOS (VBIOS mode)" + + Combo $Use_110h_for_LFP, " Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List, + Help "This feature when set to yes will use the legacy value " + "00000110h as the ID for primary LFP in the ACPI _DOD, _DGS " + "method. The ID is passed to the system BIOS through INT10h function 5F64h " + "The ID 00000110h is the backwards compatible ACPI ID " + "for LFP, which may be necessary in where Microsoft* WindowsXP " + "TabletPC*'s Graphical User Interface is required for Backlight " + "Control(hardcoded by some Windows OSes). In all other cases, " + "the default new ID is strongly preferred." + + + ;Combo $DVD_Sprite_Clone, " Disable Sprite (DVD) in Clone Mode:", &Yes_No_List, + ;Help "This feature when selected 'No', will allow the sprite to be " + ; "active during DVD playback when the platform is in a Dual " + ; "Display Clone configuration. Otherwise, when selected 'Yes', " + ; "the overlay sprite will be disabled during DVD playback when the " + ; "platform is in a Dual Display Clone configuration." + + Combo $GTF_Mode_Pruning, " Selective Mode Pruning:", &Disabled_Enabled_List, + Help "This feature when enabled will instruct driver software not " + "to enumerate or set specific display modes determined as " + "unsupported according to the EDID capabilities of the " + "display. If the display indicates support for all GTF/DMTS " + "timings in the display's EDID, then all modes supported by " + "the graphics host will be enumerated. If the display does " + "NOT indicate support for GTF/DMTS timings in the display's " + "EDID, then some modes/timings that may have been enumerated " + "by the display driver shall not be set." + "\r\n" + "\r\n" + "Note: This option applies for all display types. And in the " + "absence of other platform configuration information (e.g. " + "OEM Customizable Mode) requiring inclusion of that display " + "mode/timings." + + ;Combo $Sprite_Display_Assign, " Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_List, + ;Help "This feature when set to Primary Display, the driver will " + ; "assign the Sprite (2ndary overlay) to the primary display " + ; "defined in the current Dual Display Clone configuration, " + ; "otherwise when this feature is set to Secondary Display, the " + ;"driver will assign the Sprite (2ndary overlay) to the " + ;"secondary display defined in the current Dual Display Clone " + ;"configuration. Note: This bit will have no affect if an " + ;"application is using the VMR API. " + + + + Combo $CUIHotK_Static_Display, " Display must be attached for CUI/Hot Key:", &Yes_No_List, + Help "This feature allows a selectable option to determine whether " + "the display device must be attached for CUI Hot Key.\r\n" + "\r\n" + "With the 'No' option the display devices do not have to be " + "attached when enabling the displays via CUI Devices Pages, " + "CUI Hot Key. Note: This feature may cause the user to have " + "a blank display device due to switching to a display that is " + "not attached.\r\n" + "\r\n" + "With the 'Yes' option the display device must be attached or " + "the display switch attempt will be blocked." + EndPage + + Page "Display Features" + Link "Close Table" , ".." + + Combo $CUI_Maintain_Aspect, " Enable 'Maintain Aspect Ratio':", &No_Yes_List, + Help "This feature allows the OEM to enable or disable the 'Maintain " + "Aspect Ratio' feature. When the option is set to Yes, the " + "feature will be enabled and CUI will show for end user " + "selection 'Maintain Aspect Ratio'. When the option is set to " + "No, the complete 'Maintain Aspect Ratio' feature will be disabled." + + Combo $Preserve_Aspect_Ratio, " Preserve Aspect Ratio:", &Disabled_Enabled_List, + Help "This feature allows the OEM to configure the default option " + "for aspect ratio settings. When enabled, the CUI will reflect " + "preserve the aspect ratio as active setting. Otherwise, when " + "disabled, the CUI will use the setting 'Panel Fitting Initial " + "States' as default aspect ratio setting. This option will " + "only be available for initial boot value. Any subsequent " + "change in CUI will have higher priority." + + Title " " + TitleB "Legacy Monitor Mode Limit" + + EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum resolution is " + "specified by a maximum number of horizontal active pixels." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum resolution is " + "specified by a maximum number of vertical active pixels." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum refresh rate " + "is specified in Hz." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + + Title " " + TitleB "Rotation Support Configuration" + + + Combo $Rotation_Support_Enable, "Support Rotation Feature:", &No_Yes_List, + Help "This feature when set to yes, can cause the graphics driver to " + "support rotation feature, otherwise rotation feature support " + "will be disabled." + "\r\n" + "Note: Setting this field to Yes is a necessary condition for driver to " + "support rotation feature, but it is not sufficient." + + + Title " " + TitleB "Graphics Mode to Boot on Windows" + + + EditNum $Driver_Boot_Mode_X, " X Resolution (Pixels):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "X Resolution (Pixels)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_Y, " Y Resolution (Pixels):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Y Resolution (Pixels)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_BPP, " Color Depth (Bits/Pixel):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Color Depth (BPP)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_RR, " Refresh Rate (Hz):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Refresh Rate (Hz)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." +Title " " +TitleB "TV features" + + Combo $Under_Over_Scan_Via_DVI, " Enable underscanned modes for HDTV via HDMI:", &Under_Over_List, + Help "When 720p is found in the EDID structure of the active HDMI " + "display and enable underscan modes is selected, 1184x666 will " + "be available and be centered in 720p timings when enabled. " + "\r\n" + "When 1080i or 1080p is found in the EDID structure of the " + "active DVI display and enable underscan modes is selected, " + "1776x1000 will be centered in appropriate 1080 timings. " + + Title "\r\n" + Title " Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via HDMI:" + Combo $Add_Overscan_Mode, " ", &Disabled_Enabled_List, + Help "For 1080i format, 1776x1000 will be made available in CUI " + "along with native resolution 1920x1080. For 720p format, " + "1184x666 will be made available in CUI along with native " + "resolution 1280x720. These resolutions are exposed to get the " + "HDMI image under scanned with task bar visible." + EndPage ; Display features + + + + + Page "Power Conservation" + Link "Close Table" , ".." + + ;Combo $SDVO_Device_Power_Down, " SDVO device power down:", &Disabled_Enabled_List, + ;Help "This feature powers down the SDVO device when the system is " + "running in battery mode (DC) and the corresponding display " + "not connected." + + Combo $BIA_Enable, " Intel ® Display Power Saving Technology Support for the LFP:", &Disabled_Enabled_List, + Help "This feature determines whether the Intel ® Display Power " + "Savings Technology (DPST) is enabled or disabled. Intel ® DPST " + "is a display power savings technology that changes the " + "intensity of colors in order to conserve backlight power." + "\r\n\r\nNote: This technology is only active when the system " + "is running in battery mode and the LFP is the only active " + "display device." + + Combo $BIA_Aggress_Level, " Power Conservation Preference Level for the LFP:", &Pwr_Pref_List, + Help "This feature defines the Intel ® Display Power Saving Technology " + "aggressiveness level if and only if the feature Intel ® Display Power Saving " + "Technology is enabled." + "\r\n\r\nThe following are the definitions for each level:" + "\r\n1 - Maximum Quality - shall use no DPST " + "\r\n2 - Provides the user the maximum " + "brightness for their embedded Local Flat Panel (LFP)while DPST is in use" + "\r\n3 - This level defines maximum amount of brightness with " + "minimal power savings" + "\r\n4 - This level defines an intermediate value for brightness amount" + "\r\n5 - This level defines an intermediate value for the brightness amount" + "\r\n6 - Maximum Battery - Provided the user with the minimum amount of " + "brightness capable for their LFP with the maximum power savings" + + Combo $Panel_Self_Refresh, " Panel Self Refresh (PSR):", &Disabled_Enabled_List, + Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled. " + + Combo $PM_DRRS_Enable, " Intel ® Display Refresh Rate Switching (DRRS):", &Disabled_Enabled_List, + Help "This feature determines whether Intel ® Display Refresh Rate Switching (DRRS) is to be " + "enabled or not. " + + Combo $ALS_Enable, " Intel ® Automatic Display Brightness Support for the LFP:", &Disabled_Enabled_List, + Help "This feature determines whether Intel ® Automatic Display Brightness is to be " + "enabled. Intel ® Automatic Display Brightness adjusts the brightness of the " + "embedded Local Flat Panel (LFP) depending on the current " + "ambient light environment. When enabled, the driver and VBIOS" + " will control the backlight brightness of the LFP depending " + "on the ambient environment if and only if the LFP is the only " + "active display. When disabled, the driver and VBIOS will " + "perform no action." + + Combo $DMRRS, " Dynamic Media Refresh Rate Switching (DMRRS):", &Disabled_Enabled_List, + Help "This feature determines whether Dynamic Media Refresh Rate Switching feature is to be enabled. " + + Link "Ambient Light Response Data" , "Ambient Light Response Data" + + Page "Ambient Light Response Data" + Link "Close Table" , ".." + + Table $ALS_Response_Data " Ambient Light Response Data", + Column "Backlight Adjust", 2 bytes, EHEX + Column "Lux", 2 bytes, EHEX, + Help "This feature defines values used to calibrate the " + "Intel ® Automatic Display Brightness policy's " + "response to account for specific hardware implementation " + "details such as sensor placement and optics. Up to five " + "points can be specified, where each point indicates a given " + "ambient light illuminance to display luminance mapping " + "specified as (<%BacklightAdjust>, ). Points should be " + "listed in monotonically increasing order by ambient light " + "illuminance (lux). A minimum of two points are required " + "(min and max)." + EndPage + + EndPage + EndPage +;============================================================================== +; Page - Display Configuration +;------------------------------------------------------------------------------ + +Page "Display Configuration" + + Link "LFP" , "LFP" + Link "CRT" , "CRT" + Link "EFP 1" , "EFP 1" + Link "EFP 2" , "EFP 2" + + TitleB "DisplayPort SSC configuration: " + Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " + "This feature is valid only the attached DisplayPort panel support SSC. " + "\r\n" + + Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, + Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " + "and the attached DisplayPort panel should support SSC\r\n" + + + Page "LFP" + Link "Close Table", ".." + + Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration", &eDP_Config_List, + Help "This option select Device type. Save the configuration after selecting this field to see display related settings." + + ; #IF ($Int_LFP1_Type == 0x1806) + Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_list, + Help "This feature specifies which DVO port the device is " + ;#ENDIF + + Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List, + ;Help "This feature will select if the panel is primary or not. " + ; "The VLV platform has only one panel fitter. So, stretched mode will be only applicable " + ; "to primary panel . In secondary panel only native mode or " + ; "centering modes will be supported." + + Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, + Help "This feature selects the Local Flat Panel (LFP) the VBIOS " + "and driver is to enable.\r\n" + "\r\n" + "Note, a valid return from the system BIOS hook 5F40h will " + "replace this default value.\r\n" + "\r\n" + "Default LFP parameter values:\r\n" + "\tPANEL #01: 640x480 LVDS\r\n" + "\tPANEL #02: 800x600 LVDS\r\n" + "\tPANEL #03: 1024x768 LVDS\r\n" + "\tPANEL #04: 1280x1024 LVDS\r\n " + "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n" + "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n" + "\tPANEL #07: 1600x1200 LVDS\r\n" + "\tPANEL #08: 1280x768 LVDS\r\n" + "\tPANEL #09: 1680x1050 LVDS\r\n" + "\tPANEL #10: 1920x1200 LVDS\r\n" + "\tPANEL #11: Reserved\r\n" + "\tPANEL #12: Reserved\r\n " + "\tPANEL #13: Reserved\r\n" + "\tPANEL #14: 1280x800 LVDS\r\n" + "\tPANEL #15: 1280x600 LVDS\r\n" + "\tPANEL #16: Reserved" + + Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, + Help "This feature, when enabled, will activate support for a LFP " + "with an EDID. The video BIOS and drivers will load the EDID " + "and use its data to set appropriate timing on current panel. " + "If disabled, there will be no attempt to read an EDID and other methods " + "will be used to set panel timing." + "\r\n\r\nNote: The backlight data may need to be updated." + "\r\n The option on page General" + " Features must be correct for platform." + + Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List, + Help "This feature when set to yes, will enable 180 Degree rotation " + "otherwise, the rotation functionality will be disabled." + + Combo $Enable_Correction, "Gamma/Brightness/Contrast Correction Enable:", &Disabled_Enabled_List, + Help "This option will allow users to disable/enable Gamma/Brightness/Contrast correction feature for eDP. By default it will be disabled.\r\n" + "On enabling one can find option for entering values for Red/Blue/Green Palette Table under LFP Panel configuration.\r\n" + "Each Red/Blue/Green Palette Table has 256 entries/rows of 1-byte each. Enter required values in these fields.\r\n" + + EndPage + + + + Page "CRT" + Link "Close Window" , ".." + + Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_List, + Help "This option select CRT Device." + + Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + EndPage + + Page "EFP 1" + Link "Close Window" , ".." + + Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port the device is " + + Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_VLV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + + ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + + Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or not." + + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" + + Page "DisplayPort Redriver Configuration" + + Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, + Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." + + Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Title " " + + Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + + EndPage + + + Page "EFP 2" + Link "Close Window" , ".." + + Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port the device is " + + Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_VLV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + + ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + + Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or not." + + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" + + Page "DisplayPort Redriver Configuration" + + Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, + Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." + + Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Title " " + + Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + + EndPage + + +EndPage + + +;============================================================================ +; Page - LFP Panel configuration +;---------------------------------------------------------------------------- +Page "LFP Panel configuration" + Link "Panel #1 ", "Panel #1 " + Link "Panel #2 ", "Panel #2 " + Link "Panel #3 ", "Panel #3 " + Link "Panel #4 ", "Panel #4 " + Link "Panel #5 ", "Panel #5 " + Link "Panel #6 ", "Panel #6 " + Link "Panel #7 ", "Panel #7 " + Link "Panel #8 ", "Panel #8 " + Link "Panel #9 ", "Panel #9 " + Link "Panel #10 ", "Panel #10 " + Link "Panel #11 ", "Panel #11 " + Link "Panel #12 ", "Panel #12 " + Link "Panel #13 ", "Panel #13 " + Link "Panel #14 ", "Panel #14 " + Link "Panel #15 ", "Panel #15 " + Link "Panel #16 ", "Panel #16 " +#if($Enable_Correction == 1) + Link "RGB Palette Table ", "RGB Palette Table " +#endif + +;============================================================================== +; Page - Panel #1 (640x480) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #1 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_01, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_1, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_01, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-Emphasis Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_01, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_01 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_01 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + + EndPage + + +EndPage + +;============================================================================== +; Page - Panel #2 (800x600) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #2 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_02, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_2, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_02, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_02, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_02 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_02 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + +EndPage + + +;============================================================================== +; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #3 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_03, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_3, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_03, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level value for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_03, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_03 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_03 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + +EndPage + + +;============================================================================== +; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #4 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_04, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_4, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_04, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_04, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_04 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_04 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + +EndPage + + +;============================================================================== +; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #5 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_05, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + + Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_5, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_05, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_05, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_05 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_05 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + +EndPage + + +;============================================================================== +; Page - Panel #6 (1400x1050) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #6 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_06, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_6, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_06, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_06, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_06 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_06 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + +EndPage + + + +;============================================================================== +; Page - Panel #7 (1600x1200) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #7 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_07, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_7, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_07, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_07, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_07 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_07 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + + +;============================================================================== +; Page - Panel #8 (1280x768) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #8 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_08, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_8, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_08, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + + Combo $eDP_Link_Vswing_Level_08, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_08 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_08 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + + +;============================================================================== +; Page - Panel #9 (1680x1050) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #9 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_09, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_9, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_09, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_09, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_09 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_09 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + + +;============================================================================== +; Page - Panel #10 (1920x1200) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #10 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_10, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_10, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_10, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_10, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_10 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_10 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - Panel #11 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #11 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_11, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + "This feature selects the Vswing Pre-emph settings to be used.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_11, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_11, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_11 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_11 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - Panel #12 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #12 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_12, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_12, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_12, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_12, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_12 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_12 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - Panel #13 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #13 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_13, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_13, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_13, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_13, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_13 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_13 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage +;============================================================================== +; Page - Panel #14 (1280x800) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #14 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_14, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_14, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_14, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + + Combo $eDP_Link_Vswing_Level_14, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_14 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_14 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - Panel #15 (1280x600) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #15 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_15, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_15, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_15, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_15, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_15 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_15 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + + EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - Panel #16 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #16 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_16, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_16, "\tEdp Vswing Pre-emph table:", &eDP_Vswing_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_Level_16, " PreEmph Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + + Combo $eDP_Link_Vswing_Level_16, " VSwing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t Default Swing Setting Table \r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV | 350mV | \t\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV | N/A | \t\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A | N/A | \t\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/A | N/A | \t\t|Level 3(12000mV) | 12000mV | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------------------------------------\t\t---------------------------------------------------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_16 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_16 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + +EndPage + +;============================================================================== +; Page - RGB Palette Table +;------------------------------------------------------------------------------ +#if($Enable_Correction == 1) +Page "RGB Palette Table" + Link "Red Palette Table" , "Red Palette Table" + Link "Green Palette Table", "Green Palette Table" + Link "Blue Palette Table", "Blue Palette Table" + + Page "Red Palette Table" + Link "Close Table" , ".." + Table $Red_Table "Red Palette Table", + Column "Red", 1 byte, EHEX, + Help "Enter values for Red Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." + EndPage + + Page "Green Palette Table" + Link "Close Table" , ".." + Table $Green_Table "Green Palette Table", + Column "Green", 1 byte, EHEX, + Help "Enter values for Green Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." + EndPage + + Page "Blue Palette Table" + Link "Close Table" , ".." + Table $Blue_Table "Blue Palette Table", + Column "Blue", 1 byte, EHEX, + Help "Enter values for Blue Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." + EndPage +EndPage +#endif + + +EndPage ; "Integrated LFP Features" + + + +;============================================================================== +; Page - Display Device Toggle Lists +;------------------------------------------------------------------------------ + +Page "Display Device Toggle Lists" + + Link "Toggle/Capabilities List 1" , "Display Toggle List 1" + Link "Toggle/Capabilities List 2" , "Display Toggle List 2" + Link "Toggle/Capabilities List 3" , "Display Toggle List 3" + Link "Toggle/Capabilities List 4" , "Display Toggle List 4" + + Page "Display Toggle List 1" + + Link "Close Table" , ".." + + Table $Toggle_List1 "Display Toggle List 1", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 2" + + Link "Close Table" , ".." + + Table $Toggle_List2 "Display Toggle List 2", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 3" + + Link "Close Table" , ".." + + Table $Toggle_List3 "Display Toggle List 3", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 4" + + Link "Close Table" , ".." + + Table $Toggle_List4 "Display Toggle List 4", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT" + EndPage + +EndPage + +;============================================================================== +; Page - Modes Removal Table +;------------------------------------------------------------------------------ + +Page "Modes Removal Table" + + Table $Mode_Rem_Table "Modes Removal Table", + Column "X-Resolution", 2 bytes, DEC + Column "Y-Resolution", 2 bytes, DEC + Column "BPP", 1 byte, DEC + Column "Refresh Rate", 2 bytes, EHEX + Column "Removal Flags", 1 byte, EHEX + Column "Panel Type", 2 bytes, EHEX, + Help "This feature allows removing support for selected modes " + "resolutions.\r\n" + "\r\n" + "X-Resolution, Y-Resolution, and BPP in Decimal or " + "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n" + "\r\n" + "Refresh Rate bitmap selection (0 = Do not remove, 1 = " + "Remove):\r\n" + "\r\n" + "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n" + "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n" + "\r\n" + "Removal Flags bitmap selection (0 = Do not remove, 1 = " + "Remove):\r\n" + "\r\n" + "\tBit 7 6 5 4 3 2 1 0 \r\n" + "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n" + "\r\n" + "\tNote: 1) In order to remove mode from both Windows and DOS, " + "both Bit 1 and Bit 0 must be set to 1.\r\n" + "\r\n" + "(Mobile only) Panel Type bitmap selection (0 = Do not " + "remove, 1 = Remove if panel is active):/r/n" + "\r\n" + "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" + "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" + "\r\n" + "\tNote: Default is to remove a mode resolution from all " + "panel types." +EndPage + + +;============================================================================== +; Page - Display Configuration Removal Table +;------------------------------------------------------------------------------ + +Page "Display Configuration Removal Table" + + Table $Dev_Removed_Table " Display Device Configuration Removal Table", + Column "Pipe B" , 1 byte , BIN + Column "Pipe A" , 1 byte , BIN, + + Help "This feature allows blocking selected display configurations " + "by the video BIOS and driver.\r\n" + "\r\n" + "Display Devices are specified in the following bit patterns " + "(pipe A and B use the same bit pattern):\r\n" + "\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n" + "\r\n" + "Examples:\r\n" + "\tPipe B Pipe A\r\n" + "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n" + "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on " + "Pipe A" +EndPage + + +;============================================================================== +; Page - OEM Customizable Mode 2.0 +;------------------------------------------------------------------------------ + +Page "OEM Customizable Modes 2.0" + + Link "OEM Mode 1 Configuration", "OEM Mode #1" + Link "OEM Mode 2 Configuration", "OEM Mode #2" + Link "OEM Mode 3 Configuration", "OEM Mode #3" + Link "OEM Mode 4 Configuration", "OEM Mode #4" + Link "OEM Mode 5 Configuration", "OEM Mode #5" + Link "OEM Mode 6 Configuration", "OEM Mode #6" + + Page "OEM Mode #1" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 60h / VESA mode 160h" + Title " 16 bpp = VGA mode 61h / VESA mode 161h" + Title " 32 bpp = VGA mode 62h / VESA mode 162h" + + EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags1, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + EditNum $OEM_Mode_X1, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color1, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #2" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 63h / VESA mode 163h" + Title " 16 bpp = VGA mode 64h / VESA mode 164h" + Title " 32 bpp = VGA mode 65h / VESA mode 165h" + + EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags2, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X2, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y2, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color2, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #3" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 66h / VESA mode 166h" + Title " 16 bpp = VGA mode 67h / VESA mode 167h" + Title " 32 bpp = VGA mode 68h / VESA mode 168h" + + EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags3, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X3, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y3, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color3, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #4" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 69h / VESA mode 169h" + Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" + Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" + + EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags4, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X4, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y4, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color4, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #5" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" + Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" + Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" + + EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags5, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X5, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y5, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color5, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #6" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" + Title " 16 bpp = VGA mode 70h / VESA mode 170h" + Title " 32 bpp = VGA mode 71h / VESA mode 171h" + + EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags6, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X6, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y6, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color6, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage +EndPage + + +;============================================================================ +; End of File +;------------------------------------------------------------------------------ + diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git 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z{_NBLK1XBw@h0mFyK2`$JkV?L=B{+OoNMbBpF~NdIa2uhRFY^BLxh3JK?|7>nF|IB>A+-ufbrdU!f&sko!9JZXWT(&TocV{MNx-&hQB=f1vw#*}$ eU6~g%8BX0(d*|+-dth$++{1G_=8l>eI{yu&UjY^X literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf new file mode 100644 index 0000000..d34bf39 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf @@ -0,0 +1,137 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# CpuPeim.inf +# +# Abstract: +# +# Component description file for CPU module +# +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = CpuPeim + FILE_GUID = 01359d99-9446-456d-ada4-50a711c03adb + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeimInitializeCpu + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|CpuPeim.efi + PEI_DEPEX|CpuPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x27B0 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiMasterBootModePpiGuid + + + gEfiSecPlatformInformationPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiPlatformCpuInfoGuid + + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.depex new file mode 100644 index 0000000..4cbdd53 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.depex @@ -0,0 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf new file mode 100644 index 0000000..da142b4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf @@ -0,0 +1,190 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +# Module Name: +# +# DigitalThermalSensor.inf +# +# Abstract: +# +# Component description file for the DigitalThermalSensor SMM driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DigitalThermalSensor + FILE_GUID = 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallDigitalThermalSensor + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|DigitalThermalSensor.efi + SMM_DEPEX|DigitalThermalSensor.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3410 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3418 + + +[Protocols.IA32] + gEfiGlobalNvsAreaProtocolGuid + + gEfiSmmIoTrapDispatch2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiMpServiceProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Library/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookLib/Smm/DTSHookLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmIo/PlatSmmIo.inf +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/SmmKscLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiMpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.depex new file mode 100644 index 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = Dptf + FILE_GUID = 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DptfDriverEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D48 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2D40 + + +[Protocols.IA32] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDriverLib.inf + +[Depex.IA32] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformPolicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# DRIVER_BINDING = gSampleDrvDriverBinding +# COMPONENT_NAME = gSampleDrvComponentName +# COMPONENT_NAME2 = gSampleDrvComponentName2 +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) 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under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = ISPDxe + FILE_GUID = 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ISPDxeEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x4110 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x4118 + + +[Protocols.IA32] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MemoryInit.inf new file mode 100644 index 0000000..79dd341 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MemoryInit.inf @@ -0,0 +1,201 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Mobile Silicon Support Module" and is +# licensed for Intel Mobile CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +#/*++ +# +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# MemoryInit.inf +# +# Abstract: +# +# Component description file for MemoryInit module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = MemoryInit + FILE_GUID = D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeimMemoryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|MemoryInit.efi + PEI_DEPEX|MemoryInit.depex + +[PatchPcd.IA32] + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3 + + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31 + + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5 + + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x16FF8 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiReadOnlyVariable2PpiGuid + + + gSeCUmaPpiGuid + + gSeCfTPMPpiGuid + + gVlvMmioPolicyPpiGuid + + gPeiCapsulePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiGlobalVariableGuid + + gEfiVlv2VariableGuid + + gEfiMemoryConfigDataGuid + + + gEfiAcpiVariableGuid + + + gEfiPlatformInfoGuid + + gEfiSetupVariableGuid + + gEfiMemoryOverwriteControlDataGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf + +[Depex.IA32] +# gEfiPeiReadOnlyVariable2PpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D LPDDR2_SUPPORT=0 /D DDR3_SUPPORT=1 /D LPDDR3_SUPPORT=0 /D DEBUG_MODE=1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=1 +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. Upon termination, the End User must immediately destroy the Software or return all copies. diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchBiosWriteProtect.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchBiosWriteProtect.depex new file mode 100644 index 0000000..1b4e8e1 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchBiosWriteProtect.depex @@ -0,0 +1 @@ +©eKÖa#N µ>Çœ.0Õ·¿ÌôàöýGÔ¨ñPÁ‘>2 Åu*O¬ŽÒYj…ÌÜÆ£ê^ÈH¡Áµ3‰ù‰™öð£J&ð>òàÞÅ4/4 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchBiosWriteProtect.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchBiosWriteProtect.efi new file mode 100644 index 0000000000000000000000000000000000000000..e0abf0507c9fbfd7bdcd403ae23e393b2f6844e0 GIT binary patch literal 11264 zcmeHN4R90JonPAmgb}O=ZsHKyEXkUhK!`2LU}T%fwrn6LKv?o80wXNhlCUjTS^?(F z)jr8r#MYf$n{?VsG8dY3CT%j4UMGP<8dt`|n2;7i(vT*dgh1L#XD34-^+#gR{r zfkJ?GZfhsL<}!vcr6{gqe40s}KO&xBM|Pj3EVL3mC?F%S1OvTp~Dk2teDC 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchEarlyInitPeim + FILE_GUID = D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x640 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitDxe + FILE_GUID = DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x16C50 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x16C58 + + +[Protocols.IA32] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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zjvF|G*B~~IMGnOq4aPKMzOmF;Yiub!jX^rU_)61qeOxsQGnLaT^B;S^NXY$NsU2<;n+~msSCCQH_wtRhBKN6=jXEm2Jkx5DLX?fDlq~l3vlBB36N%}N>rM^!8bNy5Ljqt?Z z^vCtz>3#ZE!;^;J8eTE68sAZ>Q`{`7j0gnuRq+cjC^(eTfGXk0lZ# HLVx}rzk1^5 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitPeim.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitPeim.inf new file mode 100644 index 0000000..1a508fc --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitPeim.inf @@ -0,0 +1,150 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitPeim + FILE_GUID = FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x52B0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf new file mode 100644 index 0000000..92b2912 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchS3SupportDxe + FILE_GUID = 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchS3SupportEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6020 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x6028 + + +[Protocols.IA32] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.depex new file mode 100644 index 0000000..028e7ac --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.depex @@ -0,0 +1 @@ +5ä¶c¼2ÆI½·¡ þloLk°ØH¢ºåñÍ}V \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.efi new file mode 100644 index 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under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmbusArpDisabled.inf +# +# Abstract: +# +# Component description file for PchSmbus module +# This version will NOT include ARP support. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmbusArpDisabled + FILE_GUID = D82D57AC-99F9-4c7a-B591-BBCF8A0E7FBE + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchSmbusPeim + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PchSmbusArpDisabled.efi + PEI_DEPEX|PchSmbusArpDisabled.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1C80 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C88 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gEfiPeiMemoryDiscoveredPpiGuid + + gEfiPeiSmbus2PpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiVLVTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gPeiSmbusPolicyPpiGuid AND gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 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zu!%{OCn^$^iR#3d#Ms2RL`|YLF+MRNQI}{+Oil#B7Mxw-VbUe*3ZR`DokQgKnC|D$ V(RSTl-GJ^x-7($g(Bt3x`adK;!qNZ$ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf new file mode 100644 index 0000000..37a8491 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf @@ -0,0 +1,181 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmiDispatcher + FILE_GUID = 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchSmmDispatcher + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5010 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5018 + + +[Protocols.IA32] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.efi new file mode 100644 index 0000000000000000000000000000000000000000..948c2851afd39fe7f884555e6b0d8e3f51ee8bc7 GIT binary patch literal 10304 zcmb_i4O~;_xj!KRqC^t~l~&drXRx7IFC~abq66h)ZYY896+tMH#E>H4h7-m9(1jgn z38(4Zz3aODy56<@t=qb;>%42LV!whYU|lV>TUTrEs`g{Y#dfxC5G^(L|C|F9tzGxq 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ztkkUKS;bl9S+1vX#Zu*JoG1Ga| znCVV)xB0m>Lu;O1`@&lK|C3(O|3$`A8T!l>nMIkFOn+uyW{1&lywCWcady`HtgmDl zR@SWCx^nl*_f}4<)Mg9W-_L$J`-SW`v)|3WlC55~W>xVj`>NJeeXH(UbtvaV&RaQu z$yvO*c=gWJ-(LOw)eo(HesxA}Zf<36L+-b81G&G>?a%!<_j2xh(_&MO=^oSlreB-- KP1n<#VE+e=@4B1- literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.inf new file mode 100644 index 0000000..9b80bda --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.inf @@ -0,0 +1,139 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiPeim.inf +# +# Abstract: +# +# Component description file for the SPI PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiPeim + FILE_GUID = AA652CB9-2D52-4624-9FAE-D4E58B67CA46 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSpiPeim.efi + PEI_DEPEX|PchSpiPeim.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2700 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSpiPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only) +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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0000000..0129198 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf @@ -0,0 +1,251 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiSmm + FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5800 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5808 + + +[Protocols.IA32] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 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a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchUsb.inf +# +# Abstract: +# +# Component description file for PCH USB PEIM +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchUsb + FILE_GUID = 3B873142-4252-49eb-BF17-105CD6F3E808 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchUsb + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchUsb.efi + PEI_DEPEX|PchUsb.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1660 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1668 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiUsbControllerPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gEfiPeiMasterBootModePpiGuid AND gPchUsbPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmControl + FILE_GUID = FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1310 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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zD(+5h7MF-vJk4$4UgCCfZ*u)yvfij)rmxg*(r?r6*MFm*l~S7WaLS`8ze@RC%Ihh8 z@Z%RLlMQzo?l%-07@Ps=oVbds<1Abg*TV5!JGX)B;5xa@+!NfB;QTCjZ{?ojb|AJd zb2|~;KXD%JAa@8cKEb`io#sB|&TyY`B6pq};4X2)+@bVi=_k_PNk5(b;q{v$$O?S^ EA8N$=3jhEB literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf new file mode 100644 index 0000000..71d8f67 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf @@ -0,0 +1,227 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PlatformCpuPolicy.inf +# +# Abstract: +# +# Platform CPU driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PlatformCpuPolicy + FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformCpuPolicyEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PlatformCpuPolicy.efi + DXE_DEPEX|PlatformCpuPolicy.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3C70 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3C78 + + +[Protocols.IA32] + gEfiFirmwareVolume2ProtocolGuid + + gEfiPlatformCpuProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiStatusCodeRuntimeProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformCpuInfoGuid + + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[Depex.IA32] +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) 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zhU=#2rt9>&1-iw$<+|VN{-%3Ie-N$xT7Oy}iQXJxbQy0n-fw)w*ozo?#wbgioH#4d zm{`U7?MsRONKAqJE8sg@lI}?QbJD@2<4NJkQ<7tolam)ES0;OsA57kz{7&+>$;uRU zN&+N(F6D)kgDFv|GtpxgrQVYIMCyUmFH*lx4Nse%b{Sfbg#LO<8lUz^+6q&ZsmV0e ze2F>1Y&2hEUTm&3*P8D%-*0}z+-iQ>+-82weBAswqG*)m63bPVJj717g}3amJZJg9 z5}qENu1`-(FGS?L0kQK)`myxL3{^&ThAZRljEBfKuIK1y(Kt?*ue0iI(A}lmrF%p7 zzHYKUPM?ujn)sK*NlCp)|4hnF-jV!N^1pIZbA2;PIW8or{mD(&^!3avw1gIMlDa&-%0$Tsbr+ItYyA4D_( J(EpGA{twc??P>r3 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf new file mode 100644 index 0000000..d9ac1f5 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf @@ -0,0 +1,270 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +#Module Name: +# +# PowerManagement.inf +# +#Abstract: +# +# Component description file for Power Management module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PowerManagement2 + FILE_GUID = 41E89AB0-BD3D-44b6-A431-E4836EFBF2CB + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePowerManagement + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PowerManagement2.efi + SMM_DEPEX|PowerManagement2.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x8208 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x8200 + + +[Protocols.IA32] + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gPpmPlatformPolicyProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gPowerManagementAcpiTableStorageGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/IstApplet/Smm/IstApplet.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/ValleyView/Smm/MchLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/SouthCluster/Smm/IchLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Library/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/Silvermont/Smm/SilvermontPpmLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gPpmPlatformPolicyProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.bin b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.bin new file mode 100644 index 0000000000000000000000000000000000000000..fe3e741a3bb4bd78ea0bd2cf65e3ec14b77e2d4c GIT binary patch literal 64 scmaF&4gwgUV1Iz)YgrfvNGm$0w!i*&9xgIr!ppz^fxL<^6Cn@=0O7O~{r~^~ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.com b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.com new file mode 100644 index 0000000000000000000000000000000000000000..fe3e741a3bb4bd78ea0bd2cf65e3ec14b77e2d4c GIT binary patch literal 64 scmaF&4gwgUV1Iz)YgrfvNGm$0w!i*&9xgIr!ppz^fxL<^6Cn@=0O7O~{r~^~ literal 0 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0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SataController.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SataController.inf new file mode 100644 index 0000000..d19a159 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SataController.inf @@ -0,0 +1,204 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SataController.inf +# +# Abstract: +# +# Component description file for PCH SATA controller Driver module. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SataController + FILE_GUID = BB65942B-521F-4ec3-BAF9-A92540CF60D2 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSataControllerDriver + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SataController.efi + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D40 + + +[Protocols.IA32] + gEfiIdeControllerInitProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + gEfiPciIoProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gSataControllerDriverGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiLib/UefiLib.inf + +[Depex.IA32] +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.depex new file mode 100644 index 0000000..3ec1c91 --- /dev/null +++ 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zYaS{S9;g%So0H*O9_s;46DR!iX^|h|KC3dUz#J}f1Wv)EDJ}AY;&2K}OqnwtnLTs4BE)3D0~^cP=ZmdN({=bcdq5r(| z7Z%@FXpPJc{;wU8mn^=o+*(j>Ev$~T0{dac;MhZk{@cbGd`789{+!167C}I!)nVQE zo8SCq^@9&XJN{o?g1G2^*ia->fUKEt^Y~H*g?nU7NfY1@3uVV%$XCM;9zP~CrtaQ! zG3+XQqTia@M|ayrTE6d-uiXl?^O<5stFgKX-ztJ1fq-)BLpgb@Q9%*7 znVviS;pxAheqj39>5FDOGUJsQM`l=Nu9^9}nVy+vW+u;?HLGdX(ODN~O`PqTy?^$p z*-6 +# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SecCore + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + MODULE_UNI_FILE = SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + BIN|ResetVec.bin + PE32|SecCore.efi + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2188 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitLib.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmAccess.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmAccess.depex new file mode 100644 index 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmControl + FILE_GUID = DD787473-07CE-4c63-82CE-930B33F39C09 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|SmmControl.efi + DXE_DEPEX|SmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2A00 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2A08 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.inf new file mode 100644 index 0000000..f1ea1ca --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.inf @@ -0,0 +1,259 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitDxe + FILE_GUID = 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5AB0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5AB8 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.depex new file mode 100644 index 0000000..00c2f8d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.depex @@ -0,0 +1 @@ +²„}¡"rC±,ë²2Ó¦£;¹¬Ü\J“ÔãBß. \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitPeim.efi new file mode 100644 index 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a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/DigitalThermalSensor.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/DigitalThermalSensor.inf new file mode 100644 index 0000000..a3ea3da --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/DigitalThermalSensor.inf @@ -0,0 +1,182 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +# Module Name: +# +# DigitalThermalSensor.inf +# +# Abstract: +# +# Component description file for the DigitalThermalSensor SMM driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DigitalThermalSensor + FILE_GUID = 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallDigitalThermalSensor + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|DigitalThermalSensor.efi + SMM_DEPEX|DigitalThermalSensor.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1010 + + +[Protocols.IA32] + gEfiGlobalNvsAreaProtocolGuid + + gEfiSmmIoTrapDispatch2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiMpServiceProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Library/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookLib/Smm/DTSHookLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmIo/PlatSmmIo.inf +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/SmmKscLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiMpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = Dptf + FILE_GUID = 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DptfDriverEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB40 + + +[Protocols.IA32] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDriverLib.inf + +[Depex.IA32] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformPolicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# DRIVER_BINDING = gSampleDrvDriverBinding +# COMPONENT_NAME = gSampleDrvComponentName +# COMPONENT_NAME2 = gSampleDrvComponentName2 +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = GraphicDxeInitSmm + FILE_GUID = 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = GraphicDxeInitSmmEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1E00 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.depex new file mode 100644 index 0000000..9b2767a --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.depex @@ -0,0 +1 @@ +Ýkàÿa¦F{²Zœ~Å'\Ž—ëßÏÆI¾KÙ¥²†HN2¡GŒ,?­šfÜöð£J&ð>òàÞÅ4/4 \ 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = ISPDxe + FILE_GUID = 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ISPDxeEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x13F0 + + +[Protocols.IA32] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## 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as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchBiosWriteProtect.inf +# +# Abstract: +# +# Component description file for the PchBiosWriteProtect driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchBiosWriteProtect + FILE_GUID = B8B8B609-0B6C-4b8c-A731-DE03A6C3F3DC + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchBiosWriteProtect + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchBiosWriteProtect.efi + SMM_DEPEX|PchBiosWriteProtect.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x600 + + +[Protocols.IA32] + gDxePchPlatformPolicyProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid AND gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchEarlyInitPeim + FILE_GUID = D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x4A0 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) 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/dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchInitDxe.inf @@ -0,0 +1,272 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitDxe + FILE_GUID = DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xD1F0 + + +[Protocols.IA32] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchInitPeim.depex new file mode 100644 index 0000000..0e34453 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchInitPeim.depex @@ -0,0 +1 @@ +sF4eÓâK…—Ìa \ No newline at end of file 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the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitPeim + FILE_GUID = FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x27A0 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h 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+1,284 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitSmm.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitSmm + FILE_GUID = D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = PchInitSmmEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitSmm.efi + SMM_DEPEX|PchInitSmm.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3600 + + +[Protocols.IA32] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## 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+1,245 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchPcieSmm.inf +# +# Abstract: +# +# Component description file for PchPcieSmm driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchPcieSmm + FILE_GUID = acaeaa7a-c039-4424-88da-f42212ea0e55 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchPcieSmm + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchPcieSmm.efi + SMM_DEPEX|PchPcieSmm.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2600 + + +[Protocols.IA32] + ## CONSUMES + gEfiSmmIchnDispatchExProtocolGuid + + gDxePchPlatformPolicyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchExProtocolGuid AND gEfiPchInfoProtocolGuid AND gDxePchPlatformPolicyProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchPolicyInitDxe.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchPolicyInitDxe.depex new file mode 100644 index 0000000..0dc7ce4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchPolicyInitDxe.depex @@ -0,0 +1 @@ +öð£J&ð>òàÞÅ4/4 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchPolicyInitDxe.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchPolicyInitDxe.efi new file mode 100644 index 0000000000000000000000000000000000000000..9e8ef235023b5a735ae32e612d4abd04318ad855 GIT binary patch literal 2368 zcmeH|e{7RQ7{~AJ-rI__&={H+rDn#rhQy_TyHhbCrkR2mtD+1=5#4~zWkF`Pn&1?D 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchReset.inf +# +# Abstract: +# +# Component description file for Reset module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchReset + FILE_GUID = F5883FC5-F8EE-4e44-B386-6021FB320C9B + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchReset + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchReset.efi + DXE_DEPEX|PchReset.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xA10 + + +[Protocols.IA32] + gEfiResetArchProtocolGuid + + gEfiPchExtendedResetProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiCapsuleVendorGuid + + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +# Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) 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b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchS3SupportDxe.inf new file mode 100644 index 0000000..cfc7783 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchS3SupportDxe.inf @@ -0,0 +1,251 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchS3SupportDxe + FILE_GUID = 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchS3SupportEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3120 + + +[Protocols.IA32] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusArpDisabled.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusArpDisabled.depex new file mode 100644 index 0000000..028e7ac --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusArpDisabled.depex @@ -0,0 +1 @@ +5ä¶c¼2ÆI½·¡ þloLk°ØH¢ºåñÍ}V \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusArpDisabled.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusArpDisabled.efi new file mode 100644 index 0000000000000000000000000000000000000000..599f60c27969a0f521cfb0d385a1c84308f570f5 GIT binary patch literal 3136 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zda9G^&&~6D_UzgAz&Gf`O%MHF;$ZD#wU5^xsr^&!cx|TECX@@G6TT?a2rC4qK!oRo zUkcX*XI)#}H|l;~_d;E)?zeU0b)UK8p*yNq{AGo;erbJ8{XO;G`faP8aX#<-ALp-} yC!8-i6V8{Nr<}iYo^ihJ{Ihf1xnj-UH9uSfWmf&ie5vNn8dpuA<|cDKHvA{0^pq|D literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusDxe.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusDxe.inf new file mode 100644 index 0000000..ac9ef01 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmbusDxe.inf @@ -0,0 +1,206 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmbusDxe.inf +# +# Abstract: +# +# Component description file for PchSmbus driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmbusDxe + FILE_GUID = 99796403-CF03-42ec-A817-7183411D79E2 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchSmbus + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSmbusDxe.efi + DXE_DEPEX|PchSmbusDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1100 + + +[Protocols.IA32] + gDxePchPlatformPolicyProtocolGuid + + gEfiSmbusHcProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## SystemTable + gEfiHobListGuid + + gEfiSmbusArpMapGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmiDispatcher.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSmiDispatcher.depex new file mode 100644 index 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmiDispatcher + FILE_GUID = 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchSmmDispatcher + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1C10 + + +[Protocols.IA32] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git 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b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSpiRuntime.inf new file mode 100644 index 0000000..979fac0 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchSpiRuntime.inf @@ -0,0 +1,252 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiRuntime.inf +# +# Abstract: +# +# Component description file for the SPI Runtime driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiRuntime + FILE_GUID = C194C6EA-B68C-4981-B64B-9BD271474B20 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchSpiRuntime.efi + DXE_DEPEX|PchSpiRuntime.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2010 + + +[Protocols.IA32] + gEfiSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiSmm + FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2000 + + +[Protocols.IA32] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.depex new file mode 100644 index 0000000..05a6cfe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.depex @@ -0,0 +1 @@ +H×tŒüæN’ˆÄ¾À’¤s+ÀN+1J£”V{PD, \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.efi new file mode 100644 index 0000000000000000000000000000000000000000..e23277b217824ce7855f4899f29aa0a3f7727872 GIT binary patch literal 1344 zcmb_bUr19?7(a8Q}Bfa(@i&)Kzl`}TopO);8rDoDU_6KZgY%L#d zhYJQi^w2}0d#RWHz%r1yYvQz`SWiL_5(KkJRE8L=)_1lk%j!k?!MW$2-}n2z^L^)> zuk9q-H12QObMuZS4k4pN`dfenR90Il*@pCG2rU#X!|<BYfpX zV{uLYgZ~??fp|4wxDES~`F}y{?-}qzu)1Phq*hX2DKrT6X}i1pT|iF3AhnCd8K!mU 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchUsb.inf +# +# Abstract: +# +# Component description file for PCH USB PEIM +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchUsb + FILE_GUID = 3B873142-4252-49eb-BF17-105CD6F3E808 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchUsb + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchUsb.efi + PEI_DEPEX|PchUsb.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x470 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiUsbControllerPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gEfiPeiMasterBootModePpiGuid AND gPchUsbPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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or your vendor. This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for SmmAccess module +# +# Revision History: +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmAccess + FILE_GUID = B4E0CDFC-30CD-4b29-A445-B0AA95A532E4 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmAccessDriverEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmAccess.efi + PEI_DEPEX|PeiSmmAccess.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSmmAccessPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiMemoryDiscoveredPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.efi new file mode 100644 index 0000000000000000000000000000000000000000..0e4ef35820d1b180c1d6139915747adb7faf9d0f GIT binary patch literal 960 zcmeZ`VjvrAAX_K-8UtJz7CnK>(D<<7KLf)K1`Y;>wC;;(@3Rzo15F~{Hy<mq+YX@98x8{vKbBbM>+IkAez`O2xss#kx_N;D0YK~n)C0oq&LKXaxH$wA1IL$2ZXQ?< zP|g4(28|n7+R!V42!Qm0%z^M#s;a6|lG4E%Ap|HrsT!FWSsKkXT4cmyEMP2REMW|h F0{{UZe!2hv literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.inf new file mode 100644 index 0000000..fc85b5b --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/PeiSmmControl.inf @@ -0,0 +1,95 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmControl + FILE_GUID = FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x300 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SataController.inf +# +# Abstract: +# +# Component description file for PCH SATA controller Driver module. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SataController + FILE_GUID = BB65942B-521F-4ec3-BAF9-A92540CF60D2 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSataControllerDriver + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SataController.efi + +[PatchPcd.IA32] + +[Protocols.IA32] + gEfiIdeControllerInitProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + gEfiPciIoProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gSataControllerDriverGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiLib/UefiLib.inf + +[Depex.IA32] +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex new file mode 100644 index 0000000..3ec1c91 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex @@ -0,0 +1 @@ +oLk°ØH¢ºåñÍ}V \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi new file mode 100644 index 0000000000000000000000000000000000000000..8e9fc865872c0c751c0d6c26aaf854a20d6ef3b9 GIT binary patch literal 1856 zcmbVMZA@EL7(TbXv_M;Kv!G!KN;Q~hVsN3Ri7_S>MM*5Aq*8{pg*k?V=`iHhITGR} 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/dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf @@ -0,0 +1,101 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SeCUma.inf +# +# Abstract: +# +# Component description file for SeCUma module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SeCUma + FILE_GUID = E4CEDF93-672A-4782-A7FD-5FC6D239377D + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SeCUmaEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SeCUma.efi + PEI_DEPEX|SeCUma.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gSeCUmaPpiGuid + + gPeiSeCPlatformPolicyPpiGuid + + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) 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only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SecCore + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + MODULE_UNI_FILE = SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SecCore.efi + BIN|ResetVec.bin + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1CE8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) 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/FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 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zh3Tu)?@PZfV`JtvU`)#@%WBGcE6Yf{D3If;X^xR3k!()3B*V`sh;(sx+U~R?Y1d`! zLSBcmr{-+RS(1ByE&{4#_OZAEmG)NJ{ES0c&*q)ar!yK7 zfG)*xePVfHd{SmoY0`^HcO=hDxhnN{scGr=q;JU*dl3$poTRl$JClBp)Sddn)YBOs zXH3fM${fhPl=i02$HIt+;u5|b126RQ%pCH^q+nZ#cuE>BvWDx*B zlio-=lhlb?^tI&2lTRjJN={74O<9^!m$E%&cS>?s!&t}C}Gw>8(D+liXfmAgH6XYTIYhjaJjKAQVj?%v#ex%+bu{#lUoS2@t2Ap{!@zuoP z#3@NxN$ZlfC;c1v^5>-ZVrj4d0q%TQtPXBuPA?P1t#x0~!#`yhTu}t>^ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf new file mode 100644 index 0000000..79dd341 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf @@ -0,0 +1,201 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Mobile Silicon Support Module" and is +# licensed for Intel Mobile CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +#/*++ +# +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# MemoryInit.inf +# +# Abstract: +# +# Component description file for MemoryInit module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = MemoryInit + FILE_GUID = D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeimMemoryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|MemoryInit.efi + PEI_DEPEX|MemoryInit.depex + +[PatchPcd.IA32] + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3 + + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31 + + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5 + + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x16FF8 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiReadOnlyVariable2PpiGuid + + + gSeCUmaPpiGuid + + gSeCfTPMPpiGuid + + gVlvMmioPolicyPpiGuid + + gPeiCapsulePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiGlobalVariableGuid + + gEfiVlv2VariableGuid + + gEfiMemoryConfigDataGuid + + + gEfiAcpiVariableGuid + + + gEfiPlatformInfoGuid + + gEfiSetupVariableGuid + + gEfiMemoryOverwriteControlDataGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf + +[Depex.IA32] +# gEfiPeiReadOnlyVariable2PpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D LPDDR2_SUPPORT=0 /D DDR3_SUPPORT=1 /D LPDDR3_SUPPORT=0 /D DEBUG_MODE=1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=1 +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. Upon termination, the End User must immediately destroy the Software or return all copies. diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.efi b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.efi new file mode 100644 index 0000000000000000000000000000000000000000..769b1757675d2db405a68807c4c7742257fd642d GIT binary patch literal 15040 zcmeI3U2Ggz8HUI9#yG^mK^WwV2#oDqAfc%2E>$QMar~1w)Rj#ALqc8R{5Xx%O#+Tn zCuxz#vLfm@MM;%H1p$?&ih98X+=Pn=x|JnVAta&-m5K}ERuM|6r9?DRObHC{`<*@W zbLJapa!2ryW`Caf=Ka3&o-=1>J?n?R;oWt6<*tvs^8@?3J+HSampE|2tN!e&s*ibo zHSqmrS36#FD_26Bfw{S@{D6rgU*+zsykC>SH9P{nZP>xQ16sgcvh@?AM<;OXM5SMT z`{t4*P$U4t^_s@7W`07L0bEyx>_Seon-PZW4 zx4z_gJLXn1{ZG5_FgJL6`W-I_g4r`~;Q+H|Zm_Q5V)yOW-l!@XH|HnNKKv>923NSVP5r>Cl~bMGI$Sqvy57GAS)P5gDe6Z5)&Ja$ zE_Ndth#lXYo9*%&yy>^Se+9v#bJIVEqcgA972cSYmj-maQa4e%cjkkSj$bd7x6j9p zKRI28qZ=-kduEnaPkyf9qJIIWL(q2OB%TW8`9isUet-40`TaH6a@ba2tHoBgZT|Fr z#2mo(ZEQ!d9mDn=Y}430ud1rLx~3+VTd|@RGe&PXHM~pM8dsQ&Q9l}LdW_HY*c!22 z#y)OrcHe5e?!$H!oZBP)UH$8xs@Z;Y{BK|V!S5z+y%@Z`4O7_L{lM_#q46h%4;-A# z4|g0HEA1H`Dm|GW*j1Y78hvtX_h{b}j}LcscMNXXG1Q;G?+af%y5auet(yvY2{R#& zjPC6`v_~R`c9u$`$A-p6C-eP>b`SR-Ix?}ZvvlO}#OU~N-|l@|4~|U?_l=J6b@$Hk z(lG+OKVVX%@cM7<*@Ys}K4qT5$1R-$y<8KyhRAx-cHkg)+O^8A9rUdk9X0RUjvqh1 zXV>G1v+IOiJ3?XeVj=$i0^aoc81#Vjz4!P?@5oEO&KDJa9`SW8p7%axXdPa&QAc>2 z&Nm=_3GsG<*!T^I*Lb}TLBxL=Pi!{+^FH1v{8R?-1vmX|K?RXcDT6O&@cL;GwUzc=cU52vWFaq4TF`WiR-??a!^zCppX5>fNgmaoKWTp2%ztW^ z`C#imZRRsknGYcseHoV|kNi*Y*m*>mP$$Oy1dq-m;wV1ieuA5NrpVZAoo6HNC%CCI z9Ut*T{LAt#2)=uhDv^F;jrn~4h{0iAUeEAzKg9u5zA}Tira7-e8ngJibo>RxpY>(h zF5x9Ai|Q{bocdZkc~*R*qQkt`gm1(|DdSy~cc0IClAQWlJb6}pkD?RhT|nM7INHsd zJoYcsf}!+1@H`Xizf zT*pgk_Pks0Wxgdib=otyro;Fw9dFw6Zo}sq#IV`Cy}sln>g0pvC12-@3TIwThg{Pk z*L3KQ(eW@JTJX-TC(Vscl1KHVxv3}3vvj;x&$|KNu-r(aKh*cIZn&KF|F5iX1NQUx zd3Gl9c_4>z=jW-*YcqIV2FLKZI`mD;D_qGdT*)h3$tyf7Z(F(^j+fLU*8`@*cK(YG z8fQHkXFVEcJr0*T>A%M5gT|G-p$}SoR$ltx#M6he4}JxEn(+qB&U1|?;!SuuKE@f} z#s1!cK73-cK6kOd8fSksPMF`uw3~-=t;zL!hIYeIE-Hl&I9;&H8!i$g!QeWza`GO?p5?La#4Iv zIQ0dGI%~mQ{Z63V6puy*sKY{!*L~#PCO+H=<|X|(+5}e$u)i9X?=cPV0ljbJ(=^9pBE~} zxT_rFt8(c71NxAYX2*s4Du=$xp|5i2{}cLnO6jW{`YMOM${`&59gbEK*!s2WEAfr- zxKShv3@Wnm^0`c2X(8u%r|FY(B+cbgq(iRhTkh(kzp6gDrcbWvTkh)fyw>U`*YwFX zeal^a>p%L(W_`=Lo(z3vU@Si528TLwUBvobeflZqkr@D+SK_t$|C|4=KK<16t*^|6P4@P2c+L>RayWTmO-t&H7;cm+349SswcA>f7_e$b>qf|E|9HujpH!U46@4 zefq}nb@j=C(USF(YvXIVt8e{x^~HZh-}>yWqz7 zg1h?6>#QfDPp;|PI$eFsU42`BY`#VHC+AzDPFLTKi>q(zclD)yMc>xx>RTSuue_A& z-(Fw*09w8uZkD0see%W7pCn(tA71(X#PyPA)C*=-ar#}rc5mEoMAtk_05sdL<@@1g ze9u;M-3X?{oR~i`?sK2@ZTWt9<-Ev=Z>is3oWeQ}KhvD&m%`2OHRN+(Fz)m6{qXqu z!}Iqj?Fr|h`Mrt4#eap1|7pH_KfJOInEAoXT5dWnhv?9 z!@TXj%(uk-cJh%7zMydGYdYkb4tbW&^8I=9eYYe&dpM8qMG%eGOZ08g=Xj<0y?TGX z%>LpB)#lf&kq;W@yp_Lu(V^JiIfUn+qw(4d&d)C`p5MzI&T-N53Rm(9SMmy1@(Rz& z+m@~;^g-r{F~VMNFW=8M=aI~xE0`zE7(6uVk8sX6jGN{3U*q&S)RAaseo{Zi883f- z#f_Nd`~R4?^uhIq^IYR?Y0h!E*YE#VeW2g}ullRQJ89&HzyIH|$r%6f_T=vlS~?8> zWV56`*usMTo$>2R{&hsMc`qo_6ZNxk&BPu#i4PO9HUT138 zZ`9YWm&n_F)Dt9shX^eH7r8w@mY>K!mG|?{=YN)eE&rSR8~H!x7xTCB4TaAXdI}F0 zb`~ZJrwV5ZKQ6pfxLEjg;myKd3c2FSVpnl%aYu1)@nrFP#pjCOFaEIjlj2K7>azVC DfH~Uy literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.inf new file mode 100644 index 0000000..ca923c9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchEarlyInitPeim.inf @@ -0,0 +1,97 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchEarlyInitPeim + FILE_GUID = D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x640 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitPeim + FILE_GUID = FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x52B0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex new file mode 100644 index 0000000..028e7ac --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex @@ -0,0 +1 @@ +5ä¶c¼2ÆI½·¡ þloLk°ØH¢ºåñÍ}V \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.efi b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.efi new file mode 100644 index 0000000000000000000000000000000000000000..e97b8aa92af9e2fe4af36a2b85ce205613769e9e GIT binary patch literal 7616 zcmb_h3sh5Ax;`OMB197vl~(K=$7rEi2MJhgf`&(;-hxKLLj<9b1QO)6k`qLiwxIzf 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSpiPeim.inf @@ -0,0 +1,139 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiPeim.inf +# +# Abstract: +# +# Component description file for the SPI PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiPeim + FILE_GUID = AA652CB9-2D52-4624-9FAE-D4E58B67CA46 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSpiPeim.efi + PEI_DEPEX|PchSpiPeim.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2700 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSpiPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only) +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmAccess.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmAccess.inf new file mode 100644 index 0000000..d0b04fe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmAccess.inf @@ -0,0 +1,132 @@ +# +# This file contains an 'Intel Pre-EFI Module' and is licensed +# for Intel CPUs and Chipsets under the terms of your license +# agreement with Intel or your vendor. This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for SmmAccess module +# +# Revision History: +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmAccess + FILE_GUID = B4E0CDFC-30CD-4b29-A445-B0AA95A532E4 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmAccessDriverEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmAccess.efi + PEI_DEPEX|PeiSmmAccess.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1780 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSmmAccessPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiMemoryDiscoveredPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmControl.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmControl.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmControl.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmControl.efi 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/dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmControl.inf @@ -0,0 +1,110 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmControl + FILE_GUID = FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1310 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## 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This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SeCUma.inf +# +# Abstract: +# +# Component description file for SeCUma module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SeCUma + FILE_GUID = E4CEDF93-672A-4782-A7FD-5FC6D239377D + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SeCUmaEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SeCUma.efi + PEI_DEPEX|SeCUma.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C20 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gSeCUmaPpiGuid + + gPeiSeCPlatformPolicyPpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 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+++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.inf @@ -0,0 +1,130 @@ +# +# This file contains an 'Intel Pre-EFI Module' and is licensed +# for Intel CPUs and Chipsets under the terms of your license +# agreement with Intel or your vendor. This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +## @file +# SecCore module that implements the SEC phase. +# NOTE: This module was replaced by UefiCpuPkg/SecCore/SecCore.inf +# +# This is the first module taking control of the platform upon power-on/reset. +# It implements the first phase of the security phase. The entry point function is +# _ModuleEntryPoint in PlatformSecLib. The entry point function will switch to +# protected mode, setup flat memory model, enable temporary memory and +# call into SecStartup(). +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SecCore + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + MODULE_UNI_FILE = SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SecCore.efi + BIN|ResetVec.bin + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2188 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitLib.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/VlvInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/VlvInitPeim.depex new file mode 100644 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitPeim + FILE_GUID = 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2260 + + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = Dptf + FILE_GUID = 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DptfDriverEntry + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x69F8 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x69F0 + + +[Protocols.X64] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDriverLib.inf + +[Depex.X64] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformPolicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# DRIVER_BINDING = gSampleDrvDriverBinding +# COMPONENT_NAME = gSampleDrvComponentName +# COMPONENT_NAME2 = gSampleDrvComponentName2 +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) 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--- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf @@ -0,0 +1,265 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = GraphicDxeInitSmm + FILE_GUID = 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = GraphicDxeInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xC618 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC610 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.depex new file mode 100644 index 0000000..9b2767a --- /dev/null +++ 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = ISPDxe + FILE_GUID = 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ISPDxeEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x9140 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x9148 + + +[Protocols.X64] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.X64] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchBiosWriteProtect.inf +# +# Abstract: +# +# Component description file for the PchBiosWriteProtect driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchBiosWriteProtect + FILE_GUID = B8B8B609-0B6C-4b8c-A731-DE03A6C3F3DC + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchBiosWriteProtect + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchBiosWriteProtect.efi + SMM_DEPEX|PchBiosWriteProtect.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5E10 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5E18 + + +[Protocols.X64] + gDxePchPlatformPolicyProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS 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z=eds4B;LJ{7(W-MW4~6;_p?E z&$(#t8Zw^GHv>{`LeeV*WVr~*pOAP@0t&v66SjVq<4lRygn071nduJWG(Mw^oas1M zri*y$Q{lgkbjnFQpk%;7<59fMfS(e=EA@ S*dAj5c8TYlf#?8$_4&U`(*gwm literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf new file mode 100644 index 0000000..4ace397 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf @@ -0,0 +1,278 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitDxe + FILE_GUID = DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x293C0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x293C8 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.depex 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zNk*nJ(&AK_k*)j5ahbot?pF>C`-U?bxR*Myq5AJaqaywgPgtNk-@bxCX J6}u5u;6KmmZ}$KI literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.inf new file mode 100644 index 0000000..f2bfa8b --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.inf @@ -0,0 +1,290 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitSmm.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitSmm + FILE_GUID = D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = PchInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitSmm.efi + SMM_DEPEX|PchInitSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xF010 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xF018 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.depex new file mode 100644 index 0000000000000000000000000000000000000000..6f989cc9199142f9565a01ca77ca98fc2e1e5354 GIT binary patch literal 108 zcmV-y0F(a$x4+Ev;P(ATozxJh@le5$0$V^JIhV-VM2PcDNs4dxHUaqtZek35h@wlL-b35}Kfd zAq88t*lNW~1;r}fxJf8?CJ;4Q;7f#a7M#zWX+3W&)z$_x#`Y{D0?p zX7)LIuf5j0)?RzY19MubZ0 zLa6@k1Nb2z>aO&_k@)y5t87GdaZ#wqvTi;RSuOaUjPDkFU7w(3*&`&Gb$~W%$Cv3| zd|jWQWwni{l7vD>=xU|l`;vJgU8WNkaX203oGXVD6?TJ zK?hs8KS9vB&;N7$?JaQG<#y8>cGJt#nsa+~*<-)5n-11^ri}f(CM~zAbxK2fZ@aal z=g0OhI*-b2dg`?%aADT&7`{?}{t!rW5R@q7=KS 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.inf new file mode 100644 index 0000000..43501e8 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.inf @@ -0,0 +1,251 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchPcieSmm.inf +# +# Abstract: +# +# Component description file for PchPcieSmm driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchPcieSmm + FILE_GUID = acaeaa7a-c039-4424-88da-f42212ea0e55 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchPcieSmm + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchPcieSmm.efi + SMM_DEPEX|PchPcieSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xCC10 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xCC18 + + +[Protocols.X64] + ## CONSUMES + gEfiSmmIchnDispatchExProtocolGuid + + gDxePchPlatformPolicyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchExProtocolGuid AND gEfiPchInfoProtocolGuid AND gDxePchPlatformPolicyProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 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zCG{k{^^@=^@HK$X+$8;Q1aR!l(pQ8xt8^*g9z4CEe**ADg(p0&(uC)fN`0~bXQ=c{ zzyO|l)FrIJiB-lqr&KE%4;aa?1NOAnt`{6VLoa!1GeH z^9YG29FwArVfke)?Xr{^+J*HOtU2GO%0I2j^8s0pbi-4%;VI`zJ$EWR%c(cZX%F)M z`X~?7BStXUkzpcsqO@c^&=^qoc5+q+?A-RY!eCV@Fd*OUL$(9Ubi*4|nY9 z*xS+7(bI9XRt4zuG#$H@-uk&H*O9?5=0f5iKU?-B6ZF4wSy?PUJ1&p)dN{x3LD BV4eT~ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf new file mode 100644 index 0000000..8f249d7 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf @@ -0,0 +1,137 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchReset.inf +# +# Abstract: +# +# Component description file for Reset module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchReset + FILE_GUID = F5883FC5-F8EE-4e44-B386-6021FB320C9B + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchReset + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchReset.efi + DXE_DEPEX|PchReset.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6820 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x6828 + + +[Protocols.X64] + gEfiResetArchProtocolGuid + + gEfiPchExtendedResetProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiCapsuleVendorGuid + + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +# Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchS3SupportDxe + FILE_GUID = 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchS3SupportEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xDA00 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0xDA08 + + +[Protocols.X64] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 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contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmiDispatcher + FILE_GUID = 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchSmmDispatcher + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB020 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB028 + + +[Protocols.X64] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = 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+# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiRuntime.inf +# +# Abstract: +# +# Component description file for the SPI Runtime driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiRuntime + FILE_GUID = C194C6EA-B68C-4981-B64B-9BD271474B20 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchSpi + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchSpiRuntime.efi + DXE_DEPEX|PchSpiRuntime.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xBA20 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xBA28 + + +[Protocols.X64] + gEfiSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) 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+# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiSmm + FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchSpi + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC610 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC618 + + +[Protocols.X64] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 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This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# PciHostBridge.inf +# +# Abstract: +# +# Component description file for PciHostBridge module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PciHostBridge + FILE_GUID = 9fd2360e-6b48-11d5-8e71-00902707b35e + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciHostBridgeEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PciHostBridge.efi + DXE_DEPEX|PciHostBridge.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB798 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB790 + + +[Protocols.X64] + gEfiPciRootBridgeIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + gEfiMetronomeArchProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + +[Depex.X64] +# (gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- /O1=/Od +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## 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z`_~b`E3cRI8Gzr#m-wB4f5w+Fkc1V}X?$rf;n!}E{wLgzFZ;!FfUX-QpCN!(;Y)w| z0XM63Jz$$k6CS~r?MV0;zVzWKz}-c%tqF&%fIgrZ0eDl1lvNG56<@XyVY5mTw&6>i z37bl#Ejs|ODU;~{;Lw#)w^YE1_|mRR0TddFj7mn$faGBFjYIZdQ{O!pQ5|nDj%;U;0pGr zgb9)#>ya<{j7rc(5uTT*otKa+^~ge=dOQqBxybkWRBIYsuGR0_x@*U-ox7TM?cTL# z*S=kCyE=9q*>!AJ=Pq;C$z7**X)VbusV!+OdW*Nk*OJlVZ!uc(S_)f=T2{AIx74-N mw`^_M(Xz9pxn+0Do|ewX&BsqZe(G`UiR35Jp6Dghf%t!lG{gk} literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PlatformCpuPolicy.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PlatformCpuPolicy.inf new file mode 100644 index 0000000..f2c0505 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PlatformCpuPolicy.inf @@ -0,0 +1,227 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PlatformCpuPolicy.inf +# +# Abstract: +# +# Platform CPU driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PlatformCpuPolicy + FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformCpuPolicyEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PlatformCpuPolicy.efi + DXE_DEPEX|PlatformCpuPolicy.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x7D80 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x7D88 + + +[Protocols.X64] + gEfiFirmwareVolume2ProtocolGuid + + gEfiPlatformCpuProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiStatusCodeRuntimeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformCpuInfoGuid + + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[Depex.X64] +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchEarlyInitPeim + FILE_GUID = D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x4A0 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PchInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PchInitPeim.depex new file mode 100644 index 0000000..0e34453 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PchInitPeim.depex @@ -0,0 +1 @@ +sF4eÓâK…—Ìa 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terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitPeim + FILE_GUID = FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x27A0 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h 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b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PchUsb.inf @@ -0,0 +1,124 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchUsb.inf +# +# Abstract: +# +# Component description file for PCH USB PEIM +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchUsb + FILE_GUID = 3B873142-4252-49eb-BF17-105CD6F3E808 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchUsb + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchUsb.efi + PEI_DEPEX|PchUsb.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x470 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiUsbControllerPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# gEfiPeiMasterBootModePpiGuid AND gPchUsbPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.depex b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.depex new file mode 100644 index 0000000..95be042 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.depex @@ -0,0 +1 @@ +=d”øIÄÑBŽ¨…½ØÆ[Þ \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.efi b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.efi new file 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a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.inf new file mode 100644 index 0000000..2b58b58 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmAccess.inf @@ -0,0 +1,119 @@ +# +# This file contains an 'Intel Pre-EFI Module' and is licensed +# for Intel CPUs and Chipsets under the terms of your license +# agreement with Intel or your vendor. This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for SmmAccess module +# +# Revision History: +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmAccess + FILE_GUID = B4E0CDFC-30CD-4b29-A445-B0AA95A532E4 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmAccessDriverEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmAccess.efi + PEI_DEPEX|PeiSmmAccess.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSmmAccessPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiMemoryDiscoveredPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.depex b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.efi b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.efi new file mode 100644 index 0000000000000000000000000000000000000000..0e4ef35820d1b180c1d6139915747adb7faf9d0f GIT binary patch literal 960 zcmeZ`VjvrAAX_K-8UtJz7CnK>(D<<7KLf)K1`Y;>wC;;(@3Rzo15F~{Hy<mq+YX@98x8{vKbBbM>+IkAez`O2xss#kx_N;D0YK~n)C0oq&LKXaxH$wA1IL$2ZXQ?< zP|g4(28|n7+R!V42!Qm0%z^M#s;a6|lG4E%Ap|HrsT!FWSsKkXT4cmyEMP2REMW|h F0{{UZe!2hv literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.inf new file mode 100644 index 0000000..fc85b5b --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/PeiSmmControl.inf @@ -0,0 +1,95 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSmmControl + FILE_GUID = FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x300 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/ResetVec.bin b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/ResetVec.bin new file mode 100644 index 0000000000000000000000000000000000000000..fe3e741a3bb4bd78ea0bd2cf65e3ec14b77e2d4c GIT binary patch literal 64 scmaF&4gwgUV1Iz)YgrfvNGm$0w!i*&9xgIr!ppz^fxL<^6Cn@=0O7O~{r~^~ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/ResetVec.com b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/ResetVec.com new file mode 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is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SeCUma.inf +# +# Abstract: +# +# Component description file for SeCUma module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SeCUma + FILE_GUID = E4CEDF93-672A-4782-A7FD-5FC6D239377D + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SeCUmaEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SeCUma.efi + PEI_DEPEX|SeCUma.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gSeCUmaPpiGuid + + gPeiSeCPlatformPolicyPpiGuid + + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) 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+## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) 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only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SecCore + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + MODULE_UNI_FILE = SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SecCore.efi + BIN|ResetVec.bin + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1CE8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/VlvInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/VlvInitPeim.depex new file mode 100644 index 0000000..00c2f8d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/VlvInitPeim.depex @@ -0,0 +1 @@ +²„}¡"rC±,ë²2Ó¦£;¹¬Ü\J“ÔãBß. \ No newline at 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your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitPeim + FILE_GUID = 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = GraphicDxeInitSmm + FILE_GUID = 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = GraphicDxeInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2000 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitDxe + FILE_GUID = DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xD070 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) 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X_zyzBDgG}GTX_nduwA_V!w~o%5FQxC literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchInitSmm.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchInitSmm.inf new file mode 100644 index 0000000..40e0abd --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchInitSmm.inf @@ -0,0 +1,284 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitSmm.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchInitSmm + FILE_GUID = D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = PchInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitSmm.efi + SMM_DEPEX|PchInitSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3400 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGuid AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 diff --git 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as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchPolicyInitDxe.inf +# +# Abstract: +# +# Component description file for the PchPolicyInitDxe DXE driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchPolicyInitDxe + FILE_GUID = D6AC4AC2-8BC2-4cdd-8776-280E1469DE02 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchPolicyInitDxeEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchPolicyInitDxe.efi + DXE_DEPEX|PchPolicyInitDxe.depex + +[PatchPcd.X64] + +[Protocols.X64] + gDxePchPlatformPolicyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## 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zY&BcXszBF55(2GSrkl9w_@Z|ah|fk0mDPvQsO S(I7|K2m&Jrj3Dr@An+%;aXCl; literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchReset.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchReset.inf new file mode 100644 index 0000000..03762b6 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchReset.inf @@ -0,0 +1,130 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchReset.inf +# +# Abstract: +# +# Component description file for Reset module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchReset + FILE_GUID = F5883FC5-F8EE-4e44-B386-6021FB320C9B + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchReset + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchReset.efi + DXE_DEPEX|PchReset.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC10 + + +[Protocols.X64] + gEfiResetArchProtocolGuid + + gEfiPchExtendedResetProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiCapsuleVendorGuid + + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +# Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF 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/DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER 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b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchS3SupportDxe.inf @@ -0,0 +1,251 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchS3SupportDxe + FILE_GUID = 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PchS3SupportEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x39C0 + + +[Protocols.X64] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressHelpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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h0(}G|v_9YQeCP9B&$~9{Zphm(VFN%H(!Zz%{ttwrn85%5 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSmiDispatcher.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSmiDispatcher.inf new file mode 100644 index 0000000..7ab0c46 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSmiDispatcher.inf @@ -0,0 +1,175 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSmiDispatcher + FILE_GUID = 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePchSmmDispatcher + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2010 + + +[Protocols.X64] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSpiRuntime.depex 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zMFW$oYE;Suu7|To|EG%nJN5>?#EQ1-yZ4E?&^{rY{{K@+*O`BRx^{^P@S{!t(YSX0 z(xrq?wm~*x_PbWBSg~OKcc{Y+r$cy)`w96aX*c2Z|F4QrE0Q?!k U9?AZ6!PEa#K9`CAOKRZ10hG8c#Q*>R literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSpiSmm.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSpiSmm.inf new file mode 100644 index 0000000..e6e2f11 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PchSpiSmm.inf @@ -0,0 +1,245 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PchSpiSmm + FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InstallPchSpi + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2400 + + +[Protocols.X64] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK = IchSpiVirtualddressChangeEvent +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## 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a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PlatformCpuPolicy.inf b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PlatformCpuPolicy.inf new file mode 100644 index 0000000..e88898f --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PlatformCpuPolicy.inf @@ -0,0 +1,216 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PlatformCpuPolicy.inf +# +# Abstract: +# +# Platform CPU driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PlatformCpuPolicy + FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformCpuPolicyEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PlatformCpuPolicy.efi + DXE_DEPEX|PlatformCpuPolicy.depex + +[PatchPcd.X64] + +[Protocols.X64] + gEfiFirmwareVolume2ProtocolGuid + + gEfiPlatformCpuProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiStatusCodeRuntimeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformCpuInfoGuid + + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[Depex.X64] +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.depex b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.depex new file mode 100644 index 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b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.inf new file mode 100644 index 0000000..0c16379 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/PnpDxe.inf @@ -0,0 +1,200 @@ +#/** @file +# +# Component description file a sinngle segment PCI Host Bridge driver. +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +# +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PnpDxe + FILE_GUID = CE7CD764-a1d9-44e5-9857-14fefaae96dd + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePnpSetting + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PnpDxe.efi + DXE_DEPEX|PnpDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xBD0 + + +[Protocols.X64] + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiNormalSetupGuid + + gEfiPlatformInfoGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.X64] +# (gEfiVariableArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) 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/DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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z=V#27c(YYKA=?ojKeC!d{Btw3a|xNZ%4e%`Lds>q`;f;St(=VtvYc`;f3ZuuIAf7^ zLDTsaGyJOlE>(XYAmz-b#v`5*`Tsf4cDHx$?%vbAxBG$aecip? ziSB{!Bi%>42fNMg6Wu4fwH|j*c27=^-s9`>_XK)^Jw{JSPgzezPi;?APfJg0kM@wo G<-Y(^-ZfkR literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf new file mode 100644 index 0000000..ff15e86 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf @@ -0,0 +1,210 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for the SmmAccess module +# {1323C7F8-DAD5-4126-A54B-7A05FBF4151} +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmAccess + FILE_GUID = 326E9CC6-9839-4885-B2ED-275903B668E1 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmmAccessDriverEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + +[Binaries.X64] + PE32|SmmAccess.efi + DXE_DEPEX|SmmAccess.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5DE0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5DE8 + + +[Protocols.X64] + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS = /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS = /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS = -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmControl.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmControl.depex new file mode 100644 index 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your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitDxe + FILE_GUID = 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC620 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC628 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS = -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS = --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS = +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS = -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS = -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 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i9)JqS@VHa!*qM} z3_-xvd}+Zu`7nHXdACa(GynNjt6k;w*i-7tUUP=V_@zaD%e+v@vxQ0gHWPRBO}qjF zCS2weedib3zHNhZ!7b08I}3GF*7f1pR z{At^^6PZDOYOd>A9mpc53oH0mDqMRT99Rab6pO~P9a^$X@XG$v8iL|x&s|+|!Ggn!NTE)@B zX%?dg!wA0nh2{~6lzndaiSfC{6MIu+@P_*Mo~7}v>4_~Z#tZuKZRbAw@zh&?ma|-T z*L%MnZ~AMh?W6U8_e0P=Sf5LdBilBa=zaJi=kA0{Me|TtUsOP{TbUere=V}1{rzoWn+Du=f9ki21X)o=g z{d9u6ZAWpp+C?I^eW9$!pc|$+svM1PqTWqo$X*vY!}V!Q65{9+AJ0&&U~hPQEPvB>yhEm4LEUsZk!}qyH~p{~Ltch>QRL literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SmmControl.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SmmControl.inf new file mode 100644 index 0000000..fd21028 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SmmControl.inf @@ -0,0 +1,122 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmControl + FILE_GUID = DD787473-07CE-4c63-82CE-930B33F39C09 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmmControlDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|SmmControl.efi + DXE_DEPEX|SmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x800 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF 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/DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER 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vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitDxe + FILE_GUID = 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x30D0 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid uninstalled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib/PchPlatformLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocolGuid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiDatabaseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex new file mode 100644 index 0000000..00c2f8d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex @@ -0,0 +1 @@ +²„}¡"rC±,ë²2Ó¦£;¹¬Ü\J“ÔãBß. \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.efi b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.efi new file mode 100644 index 0000000000000000000000000000000000000000..7152888719c4c31ef172a954f6e8d03875e95ac7 GIT binary patch literal 3104 zcmbVOeQXow8Gp|{f7G#ab}_0ug~lo8m7$EdHmwNB)|kZEA5Fj^#F z#1Mo_F9Dxl9si(KnzU7XRQ>p`LnSz^3USQh&`JohwY1_7Ot(V70WwCZ5njCKy>rN! zRY>Jz-@VVr?|FaE^FHr;*ZLdu$k&IDjC^!pD2PxCr7sDPLAt6ksvKp^2)QZMb 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zVC?AN?n6)aHU70ad(`*$caK183U=6Xb5}dsf;hyZ*FiBqUJKey=ryz*o_*+#bIuPu zZ6Jr>|7VCt{=aHm*FwJa$Ty$z{m1_PRRsbz;y3rLM?SDxh}@@s{1L2TS7dhQ&YhcI c`KR literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.inf new file mode 100644 index 0000000..a032c7f --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.inf @@ -0,0 +1,101 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = VlvInitPeim + FILE_GUID = 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS = Symbol renaming not needed for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS = -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS = /nologo /E /TC /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS = -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS = /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=0E0000000h /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS = +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS = -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS = /nologo /E /TC /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h /DMINNOW2_PO /DENBDT_PF_ENABLE=1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=1 /DPCIESC_SUPPORT=1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS = objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS = /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS = /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS = -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h b/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h new file mode 100644 index 0000000..b14d40e --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h @@ -0,0 +1,72 @@ +// +// This file contains an 'Intel Peripheral Driver' and is +// licensed for Intel CPUs and chipsets under the terms of your +// license agreement with Intel or your vendor. This file may +// be modified by the user, subject to additional terms of the +// license agreement +// +/** @file + + + Cache PPI definition. + +Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +**/ + +#ifndef _PEI_CACHE_PPI_H_ +#define _PEI_CACHE_PPI_H_ + +#define PEI_CACHE_PPI_GUID \ + { \ + 0xc153205a, 0xe898, 0x4c24, {0x86, 0x89, 0xa4, 0xb4, 0xbc, 0xc5, 0xc8, 0xa2 } \ + } + +typedef struct _PEI_CACHE_PPI PEI_CACHE_PPI; + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +// +// PEI_SET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_SET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +// +// PEI_RESET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_RESET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ); + +// +// PEI_CACHE_PPI +// +struct _PEI_CACHE_PPI { + PEI_SET_CACHE_PPI SetCache; + PEI_RESET_CACHE_PPI ResetCache; +}; + +extern EFI_GUID gPeiCachePpiGuid; + +#endif diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc new file mode 100644 index 0000000..aefa4e2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc @@ -0,0 +1,13056 @@ +dd 000000001h ; Header Version +dd 000000321h ; Patch ID +dd 001142014h ; DATE +dd 000030673h ; CPUID +dd 0984d6012h ; Checksum +dd 000000001h ; Loader Version +dd 000000001h ; Platform ID +dd 00000cbd0h ; Data size +dd 00000cc00h ; Total size +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h +dd 0000000a1h +dd 000020001h +dd 000000321h +dd 000000000h +dd 000000000h +dd 020140114h +dd 000003211h +dd 000000001h +dd 000030673h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 0000032f4h +dd 000000000h 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mode 100644 index 0000000..e5c50e8 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130678806.inc @@ -0,0 +1,12800 @@ +dd 000000001h ; Header Version +dd 000000806h ; Patch ID +dd 011262013h ; DATE +dd 000030678h ; CPUID +dd 014d372a6h ; Checksum +dd 000000001h ; Loader Version +dd 000000001h ; Platform ID +dd 00000c7d0h ; Data size +dd 00000c800h ; Total size +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h +dd 0000000a1h +dd 000020001h +dd 000000806h +dd 000000000h +dd 000000000h +dd 020131125h +dd 0000031f1h +dd 000000001h +dd 000030678h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 0000031f4h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 06fbddad0h +dd 097b60ec8h +dd 08252afd4h +dd 0e61f6d91h +dd 03542ee8ch +dd 084b597b4h +dd 0ec4d4fd9h +dd 0ffb27814h +dd 0156866dbh +dd 0c4bf175ah +dd 09d00ca4fh +dd 0b3e89a09h +dd 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+dd 0e6c219ebh +dd 040792f9fh +dd 0ce382acah +dd 049031196h +dd 09f99e1d0h +dd 010da299fh +dd 0e20103fdh +dd 0cb1ff4bah +dd 054137653h +dd 06ccbcae4h +dd 01b225379h +dd 0293f0143h +dd 0077a7d0fh +dd 0e6e0e7b6h +dd 025a8c9b5h +dd 067284ae4h +dd 035cfc4f1h +dd 0833ad665h +dd 09bf4fb0bh +dd 013b90783h +dd 0c3a94a2ah +dd 071b2756fh +dd 028832cach +dd 009514869h +dd 05ad02897h +dd 0ac973470h +dd 0ec1e6f9fh +dd 0fc71febbh +dd 059a286f7h +dd 0b448bbf7h diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf new file mode 100644 index 0000000..e5b847d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf @@ -0,0 +1,51 @@ +#/*++ +# +# Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved +# + +# This program and the accompanying materials are licensed and made available under + +# the terms and conditions of the BSD License that accompanies this distribution. + +# The full text of the license may be found at + +# http://opensource.org/licenses/bsd-license.php. + +# + +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +# + +# +# +# Module Name: +# +# MicrocodeUpdates.inf +# +# Abstract: +# +# List all of the microcode updates that you want included at build time. +# +#--*/ + +[defines] +BASE_NAME = MicrocodeUpdates +FILE_GUID = 1FAE4D78-CB33-4f73-8881-A1EA8F5EDFEF +COMPONENT_TYPE = Microcode +FFS_EXT = .ffs +MODULE_TYPE = USER_DEFINED + +[sources.common] +M0F30679909.inc +M0130673321.inc +M0130678806.inc +M023067221D.inc + +[includes.common] + +[libraries.common] + +[nmake.common] diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. Upon termination, the End User must immediately destroy the Software or return all copies. diff --git a/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. 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b/Silicon/Intel/Vlv2SocBinPkg/UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. Upon termination, the End User must immediately destroy the Software or return all copies. diff --git a/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) +PRODUCTION LICENSE AGREEMENT + +IMPORTANT – READ BEFORE COPYING, INSTALLING OR USING. + +Do not copy, install, use or load software identified in this Agreement or any associated materials until you have carefully read the following terms and conditions. By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. 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By copying, installing, using or loading the software identified in this Agreement or any associated materials, you agree to the terms of this Agreement. If you do not wish to so agree, do not copy, install, use or load the software or any associated materials. If you are an employee, representative or agent of a legal entity, you represent and warrant that you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions + +This agreement (“Agreement”) is by and between Licensee and Intel Corporation, a Delaware corporation, having its principal place of business at 2200 Mission College Boulevard, Santa Clara, California 95054 (“Intel”) and is effective as of the first date Licensee copies, installs, uses or loads the software identified in this Agreement or any associated materials (“Effective Date”). + +1.0 DEFINITIONS + +1.1 “ASL Code” means code written in the ‘ACPI source language’ and designed and delivered to Licensee by Intel and designed to be compatible with Intel products. Such ASL Code remains ASL Code regardless of any legends in header files of the ASL Code. +1.2 “Assembly Code” means code written in the ‘assembly source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.3 “MBM-UDK” means the MinnowBoard MAX UEFI Development Kit, which is an Intel implementation of the +UEFI specification, and is based on the Intel® UEFI Development Kit 2014 (Intel® UDK2014), consisting of +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundation Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Assembly Code, C Code and Reference Drivers together, as well as any and all documentation and tools, provided by Intel for the purposes of implementation. +1.4 “MBM-UDK Libraries” means the core library services offered in the MinnowBoard MAX UEFI Development +Kit. +1.5 “Boot Loader” means a device and use-case-specific firmware program a computer’s processor uses to get the computer system started after power-on, with some basic hardware initialization, until handoff to the operating system. +1.6 “BSD License” means the Berkeley Software Distribution License, which is a family of permissive free software licenses created for the original Berkeley Software Distribution operating system. +1.7 “C Code” means code written in the ‘C source language’ and designed and delivered to Licensee by Intel under this Agreement. +1.8 “Customer” means Original Equipment Manufacturer (a company that makes computer systems for sale under its own brand name), Independent Authorized Developer (a company that performs services for Licensee in the development of Licensee’s products), or Original Design Manufacturer (a company that +designs and manufactures computer systems for Independent Authorized Developers and Original Equipment Manufacturers) but excluding End Users. +1.9 “Derived Object Code” means the subset of Derivative Works that is the Object Code derived from Source Code or Derived Source Code. +1.10 “Derived Source Code” means the subset of Derivative Works that is the source code derived from Source Code by modifying the Source Code in any way. +1.11 “Derivative Works” means those bodies of work defined in 17 U.S.C. §101 as “derivative works” of existing copyrighted material. For purposes of this Agreement, Derivative Works include both Derived Source Code and Derived Object Code. +1.12 “DXE Driver” means Driver Execution Environment driver, which is a hardware device driver compliant with the execution environment as defined in the UEFI specification. +1.13 “DXE Foundation Code” means the foundational Driver Execution Environment code that provides the standard function and services that are available to the DXE Drivers. +1.14 “End User” means a purchaser or recipient or user of Licensee’s computer products who does not resell Licensee’s products in the normal course of the End User’s business. +1.15 “Firmware” means the programming code that is inserted into the programmable read-only memory of a computer system, thus becoming a permanent part of a particular computing device. +1.16 “Intel Processor” means processors designed by Intel and released by or on behalf of Intel and marketed under Intel’s (or Intel licensed) trademarks. +1.17 “Licensee” means the individual accepting these terms or, if the individual is accepting these terms on behalf of a legal entity (such as a corporation, partnership, agency, etc.), “Licensee” means the legal entity. +1.18 “Object Code” means the binary version of the Source Code, including all computer programming code, entirely in binary form, which is directly executable by a computer and includes those help, message, overlay, and other files necessary for supporting the intended use of the executable code. +1.19 “PEI Foundation Code” means Pre-extensible firmware interface (“PEFI”) initialization foundation code, which performs basic hardware initialization in order to load and execute the DXE Foundation Code. +1.20 “PEI Modules” means PEFI initialization modules, which are code modules that perform basic environmental set up prior to initialization of DXE Foundation Code. +1.21 “Peripheral Drivers” means code that initializes and operates hardware devices that are peripheral to the Intel Processor. +1.22 “Reference Drivers” means those drivers supplied as part of the Source Code that are marked or tagged by Intel as ‘reference drivers’. +1.23 “Source Code” means the source code of the MB-UDK Libraries and Reference Drivers delivered to Licensee by Intel under this Agreement, along with all Intel-delivered tools, documentation, specifications, and schematics related thereto. +1.24 “Subsidiaries” means, with respect to any legally recognizable entity, any entity Controlling, Controlled by, or under common Control with the entity. “Control” means (i) ownership of fifty percent (50%) or more of the outstanding shares representing the right to vote for members of the directors or other managing officers of the entity, or (ii) for an entity which does not have outstanding shares, fifty percent (50%) or more of the ownership interest representing the right to make decisions for the entity. An entity will be deemed a Subsidiary only so long as the Control exists. +1.25 “UDK2014” means the Intel® UEFI Development Kit 2014 (Intel® UDK2014), which is an openly available implementation of the UEFI framework provided by Intel under BSD License terms. +1.26 “UEFI” means the Unified Extensible Firmware Interface, which is an industry standard detailing an interface that helps hand off control of the system for the pre-boot environment (i.e., after the system is powered on, but before the operating system starts) to an operating system. + +2.0 LICENSE RIGHTS AND CONDITIONS + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of this Agreement, Intel grants to Licensee a limited, non-exclusive, non-transferable, non-sublicensable, worldwide and royalty-free license under Intel’s copyrights to: +Reproduce and prepare Derivative Works of the Source Code solely for Licensee’s own internal use, to design, develop, modify or debug Derivative Works that operate in or in conjunction only with Intel Chipsets or Intel Processors as specified in Exhibit A; +Reproduce and distribute MB-UDK internally for Licensee’s own use in developing and maintaining products or services supporting Intel Chipsets or Intel Processors as specified in Exhibit A; and +Distribute Object Code and Derived Object Code externally to Licensee’s End Users, either directly or through Licensee’s usual distribution channels and methods, but only for use with Intel Chipsets or Intel Processors as specified in Exhibit A. Licensee will distribute all Licensed Programs under an end user license agreement (“End User License”) containing at a minimum the terms and conditions set forth in Exhibit B. +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are also subject to the following +limitations: +Licensee will not make any statement that the Derivative Works are "certified," or that performance is guaranteed, by Intel; +Licensee will not disassemble, reverse engineer, or decompile any Object Code provided to Licensee. +Licensee will not use Intel's name or trademarks without prior written permission; and +Licensee may not disclose, distribute or make commercial use of the MB-UDK as a stand-alone product. +Except as specifically permitted in Sections 2.1, above, Licensee is not licensed to use the MB-UDK in any other manner, including for Licensee’s other internal or business use or for use in association with any other products. Licensee will not license MB-UDK to any third party. Licensee will include all copyright notices in all full and partial copies of the MB-UDK, including all Derived Source Code, and will not deface, obscure or alter any copyright notices. +Licensee is not obligated to provide Intel with comments or suggestions regarding Derived Source Code or the MB-UDK received under this Agreement. Should Licensee, however, provide Intel with designs, comments or suggestions for the modification, correction, improvement or enhancement of the MB-UDK or Intel products which may embody the MB-UDK (collectively, “Feedback”), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide, royalty-free license, including the right to sublicense Intel licensees and customers, under Licensee’s intellectual property rights in the Feedback, and the rights to use and disclose the Feedback in any manner Intel chooses and to display, perform, copy, have copied, make, have made, use, sell, offer to sell, and otherwise dispose of Intel’s and its sublicenses’ products embodying the Feedback in any manner and via any media Intel chooses, but without reference to the source of the Feedback. + +3.0 DISCLAIMER OF WARRANTY +Neither Intel nor its suppliers make any representation or warranty or condition of any kind whether express or implied (either in fact or by operation of law) with respect to the MB-UDK. Intel and its suppliers expressly disclaim all warranties or conditions of merchantability or fitness for a particular purpose. Intel and its suppliers do not warrant that the MB-UDK is error-free or that operation of the MB-UDK will be secure or uninterrupted and hereby disclaim any and all liability on account thereof. There is also no implied warranty of non-infringement. MB-UDK is licensed on an "as is" basis and neither Intel nor its suppliers will provide any support, assistance, installation, training or other services. Intel and its suppliers may provide any updates, enhancements or extensions at their sole discretion. + +4.0 LIMITATION OF LIABILITY +In no event will Intel or its suppliers be liable for: (a) any representation or warranty made to any third party by Licensee, any agent of Licensee or distributor; (b) failure of the MB-UDK to perform as expected; (c) failure of the MB-UDK to provide security; or (d) any use of the MB-UDK or the results or information obtained or decisions made by licensee’s use of the MB-UDK. +Intel and its suppliers will not be liable for any direct, indirect, special, incidental or consequential damages of any kind, even if advised of the possibility of these damages. + +5.0 PROTECTION AND SECURITY +Licensee acknowledges that information and materials disclosed or provided to Licensee pursuant to this Agreement may contain Intel trade secrets. Such trade secrets are protected by the provisions of the applicable nondisclosure agreement(s) between the parties. Licensee will not make MB-UDK or Derivative Works available in whole or in part or in any form, to any person other than Licensee's employees who are designated to work on Licensee's development effort authorized hereunder and who have a specific need for access to MB-UDK. Licensee agrees to instruct these employees of his or her obligations with respect to use, copying, protection, and security of MB-UDK and associated documentation. Notwithstanding the earlier termination of this Agreement, the obligations of this section are to remain in effect until the time as MB-UDK becomes publicly known, through no act or failure to act on Licensee's or Subsidiary’s part. + +6.0 ASSIGNMENT, SALE OR TRANSFER +Licensee will not assign, sublicense, or otherwise transfer this Agreement or any right or obligation hereunder without Intel's prior written consent, which consent will not be unreasonably withheld in the event Licensee is acquired by an entity that is not a competitor of Intel. Any attempt to do so will be null and void. + +TERMINATION + +Licensee may terminate this Agreement and the licenses granted in the Agreement at any time upon Intel’s receipt of written notice. +Intel may terminate this Agreement and any licenses granted in the Agreement at any time if Licensee fails to cure any material breach of this Agreement within thirty (30) days after notice of the breach. Such termination will not prejudice Intel's right to damages or any other remedy available at law or in equity. +Upon termination of the Agreement or any license granted hereunder for any reason whatsoever, Licensee will completely remove MB-UDK from all Derived Source Code. In the event of any termination, Licensee will, at Intel's option, either return to Intel or destroy the original and all full or partial copies of MB-UDK, including those portions in Derived Source Code, and certify to Intel that they have been destroyed. +The following sections will survive expiration or termination of this Agreement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. + +OWNERSHIP + +MB-UDK and all copies, and any updates provided by Intel, in whole or in part, are and will remain the property of Intel or its suppliers. Licensee understands and agree that no license under any Intel patent, copyright (except as expressly described in Sections 2.1, above), trade secret or other intellectual property right is granted or conferred upon Licensee in this Agreement or by the providing of the MB-UDK by Intel to Licensee hereunder, either expressly, by implication, inducement, estoppel or otherwise, and that any further license under the intellectual property rights must be express and in writing. +Title in and to the Derived Source Code will be held by Licensee or Licensee’s suppliers as appropriate, subject to Intel’s underlying ownership of the MB-UDK. + +9.0 EXPORT CONTROL +Neither party will export, either directly or indirectly, any product, service or technical data or system incorporating the MB-UDK without first obtaining any required license or other approval from the U.S. Department of Commerce or any other agency or department of the United States Government. In the event any product or software is exported from the United States or re-exported from a foreign destination by either party, that party will ensure that the distribution and export/re-export or import of the product or software is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its Subsidiaries will export/re-export any software, technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is shipping requires an export license, or other governmental approval, without first obtaining the license or approval. + +GENERAL + +Any dispute arising directly under the express terms of this Agreement or the grounds for termination of any rights granted under this Agreement will be resolved as follows: First, within forty five (45) days from one party’s written request to the other, senior executives of both parties will meet to attempt to resolve the dispute. If the senior executives cannot resolve the dispute, either party may then make a written demand for formal dispute resolution by tendering to the other party notice of the dispute and its intent to invoke the terms of this Section 10.1. The parties agree to meet within ninety (90) days of the demand with an impartial mediator selected by mutual agreement to participate in a one-day, non-binding mediation. In the event the parties cannot agree on a mediator, they will each select one nominator, who will not at that time be employed by either party, and the two nominators will agree on and appoint the mediator. If the parties have not resolved the dispute or claim within thirty (30) days after the one-day, non-binding mediation, either party may begin litigation proceedings. +This is the complete and exclusive Agreement between the parties relating to this subject matter. No amendment will be effective unless in writing signed by authorized representatives of both parties. +The terms and conditions stated in the Agreement are declared to be severable. If any paragraph, provision, or clause in this Agreement will be found or be held to be invalid or unenforceable in any jurisdiction in which this Agreement is being performed, the remainder of this Agreement will be valid and enforceable and the +parties will use good faith to negotiate a substitute, valid and enforceable provision which most nearly effects the parties' intent in entering into this Agreement. +Any claim arising under or relating to this Agreement, will be governed by the laws of the State of Delaware, excluding its conflicts of laws provisions. The parties agree that all disputes and litigation regarding the above defined claims will be subject to the exclusive jurisdiction of the courts of the State of Delaware or of the Federal courts sitting in Delaware. + +[END OF GENERAL TERMS AND CONDITIONS] + +EXHIBIT A +SUPPORTED PLATFORMS + +List of supported platforms with which the MB-UDK may be used: + BayTrail-I Atom E3825, E3845, E3815, + E38xx E3826, E3827 + +EXHIBIT B +MINIMUM OBJECT CODE +END-USER LICENSING TERMS + +Licensee will ensure that terms at least as restrictive and protective of Intel’s interests as the following minimum terms, as described below, are included in all End User Licenses. These minimum terms apply to distribution of Licensed Programs (object code) only. + +An End User may: +Copy the Licensed Programs and accompanying materials (“Software”) onto the End User’s computers for End User’s internal use solely for development and maintenance of the End User’s products supporting Intel Chipsets or Intel Processors. + +An End User may not: +Sublicense or further distribute the Software, or permit simultaneous use of the Software by more than one user. +Reverse engineer, decompile, or disassemble the Software. +Use, copy, modify, sell or transfer the Software except as provided in this Exhibit B. +Remove any copyright notices from the Software or any copies thereof. +Export or import Software in violation of any law, regulation, order or other restriction of the United States government and its agencies, or any foreign government. + +An End User will also be made aware of and agree that: + +Title to the Software and all copies thereof remain with Licensee or its suppliers, as applicable, and the Software is copyrighted and protected by United States and international copyright laws. + +Except as expressly provided in this Exhibit B, End User is not granted any express or implied right under Intel patents, copyrights, trademarks or trade secret information. + +The Software is provided “AS IS” without any express or implied warranty of any kind, including warranties +of merchantability, noninfringement of third-party intellectual property or fitness for any particular purpose. + +Liability to End User is completely disclaimed to the extent allowed by law, including without limitation all indirect, special, incidental, and consequential damages of any kind. + +The technical data and Software covered by this license is a “Commercial Item,” as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is “commercial computer software” and “commercial computer software documentation” as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software and related documentation is provided to End Users for use by and on behalf of the U.S. Government, with only those rights as are granted to all other End Users pursuant to the terms and conditions of the End User License. Use for or on behalf of the U.S. Government is permitted only if the party acquiring or using this software is properly authorized by an appropriate U.S. Government official. This use by or for the U.S. Government clause is in lieu of, and supersedes, any other FAR, DFARS, or other provision that addresses Government rights in the computer software or documentation covered by this license. + +The End User License may be terminated at any time if the End User is in breach of any of its terms and conditions. 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zb+~#t_|u~?jptB7^ClwRWqsv?$pke`gV#&wUCb?kgjKLQ3jt!k6Wb@B^ zyCD_dTJ>;kF8pCDp#%S?MJu?+L+Ws%D-lW6lx-WU)ZyFYk__)7)86@BqkT`g5 zWC`yBv;Z;kk?~N)w4>w1LceQPd!{IydQ)&VHkAy4Upmg8tn!s-J|_4!X{vGZx!emB50aF4V{A*Gu>~s1%h +# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Vlv2SocBinPkg.dec + PACKAGE_GUID = 7dbe088f-2e1a-475c-b006-55632c2a5489 + PACKAGE_VERSION = 0.9 + +[Includes] + Include + +[Ppis] + gPeiCachePpiGuid = { 0xC153205A, 0xE898, 0x4C24, { 0x86, 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2 }} diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi new file mode 100644 index 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