From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: michael.d.kinney@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Sun, 30 Jun 2019 20:07:31 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jun 2019 20:07:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,437,1557212400"; d="scan'208";a="338482507" Received: from mdkinney-mobl2.amr.corp.intel.com ([10.251.143.61]) by orsmga005.jf.intel.com with ESMTP; 30 Jun 2019 20:07:11 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Zailiang Sun , Yi Qian Subject: [edk2-non-osi Patch] Vlv2SocBinPkg: Add initial binaries for Vlv2TbltDevicePkg Date: Sun, 30 Jun 2019 20:07:07 -0700 Message-Id: <20190701030707.5848-1-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Add the initial version of the binaries required to build Vlv2TbltDevicePkg in the edk2-platform repository Cc: Zailiang Sun Cc: Yi Qian Signed-off-by: Michael D Kinney --- .../RELEASE_VS2008x86/IA32/IntelGopDriver.efi | Bin 0 -> 60192 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../RELEASE_VS2008x86/X64/IntelGopDriver.efi | Bin 0 -> 75008 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../GOP/7.2.1011/VBT/MNW2/Vbt.bin | Bin 0 -> 4096 bytes .../GOP/7.2.1011/VBT/MNW2/vbt.bsf | 9216 +++++++++++ .../IA32DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf | 137 + .../IA32DEBUG/IA32/DigitalThermalSensor.depex | 1 + .../IA32DEBUG/IA32/DigitalThermalSensor.efi | Bin 0 -> 14848 bytes .../IA32DEBUG/IA32/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.efi | Bin 0 -> 12704 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.inf | 219 + .../IA32DEBUG/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 25088 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.inf | 265 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.efi | Bin 0 -> 17984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf | 247 + .../IA32DEBUG/IA32/MemoryInit.depex | 1 + .../IA32DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../IA32DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32DEBUG/IA32/PchBiosWriteProtect.depex | 1 + .../IA32DEBUG/IA32/PchBiosWriteProtect.efi | Bin 0 -> 11264 bytes .../IA32DEBUG/IA32/PchBiosWriteProtect.inf | 130 + .../IA32DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../IA32DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../IA32DEBUG/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/PchInitDxe.efi | Bin 0 -> 102496 bytes .../IA32DEBUG/IA32/PchInitDxe.inf | 278 + .../IA32DEBUG/IA32/PchInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../IA32DEBUG/IA32/PchInitPeim.inf | 150 + .../IA32DEBUG/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/PchInitSmm.efi | Bin 0 -> 35840 bytes .../IA32DEBUG/IA32/PchInitSmm.inf | 290 + .../IA32DEBUG/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32DEBUG/IA32/PchPcieSmm.efi | Bin 0 -> 26112 bytes .../IA32DEBUG/IA32/PchPcieSmm.inf | 251 + .../IA32DEBUG/IA32/PchPolicyInitDxe.depex | 1 + .../IA32DEBUG/IA32/PchPolicyInitDxe.efi | Bin 0 -> 9440 bytes .../IA32DEBUG/IA32/PchPolicyInitDxe.inf | 123 + .../IA32DEBUG/IA32/PchReset.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.efi | Bin 0 -> 12288 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.inf | 137 + .../IA32DEBUG/IA32/PchS3SupportDxe.depex | 1 + .../IA32DEBUG/IA32/PchS3SupportDxe.efi | Bin 0 -> 25760 bytes .../IA32DEBUG/IA32/PchS3SupportDxe.inf | 257 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../IA32DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../IA32DEBUG/IA32/PchSmbusDxe.depex | 1 + .../IA32DEBUG/IA32/PchSmbusDxe.efi | Bin 0 -> 15552 bytes .../IA32DEBUG/IA32/PchSmbusDxe.inf | 214 + .../IA32DEBUG/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.efi | Bin 0 -> 24576 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.inf | 181 + .../IA32DEBUG/IA32/PchSpiPeim.depex | 1 + .../IA32DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../IA32DEBUG/IA32/PchSpiPeim.inf | 139 + .../IA32DEBUG/IA32/PchSpiRuntime.depex | 1 + .../IA32DEBUG/IA32/PchSpiRuntime.efi | Bin 0 -> 23552 bytes .../IA32DEBUG/IA32/PchSpiRuntime.inf | 258 + .../IA32DEBUG/IA32/PchSpiSmm.depex | 1 + .../IA32DEBUG/IA32/PchSpiSmm.efi | Bin 0 -> 24064 bytes .../IA32DEBUG/IA32/PchSpiSmm.inf | 251 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.inf | 137 + .../IA32DEBUG/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32DEBUG/IA32/PciHostBridge.efi | Bin 0 -> 22336 bytes .../IA32DEBUG/IA32/PciHostBridge.inf | 254 + .../IA32DEBUG/IA32/PeiSmmAccess.depex | 1 + .../IA32DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../IA32DEBUG/IA32/PeiSmmAccess.inf | 132 + .../IA32DEBUG/IA32/PeiSmmControl.depex | 1 + .../IA32DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../IA32DEBUG/IA32/PeiSmmControl.inf | 110 + .../IA32DEBUG/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.efi | Bin 0 -> 17632 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.inf | 227 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.efi | Bin 0 -> 17472 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.inf | 207 + .../IA32DEBUG/IA32/PowerManagement2.depex | 1 + .../IA32DEBUG/IA32/PowerManagement2.efi | Bin 0 -> 36352 bytes .../IA32DEBUG/IA32/PowerManagement2.inf | 270 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32DEBUG/IA32/SataController.efi | Bin 0 -> 12128 bytes .../IA32DEBUG/IA32/SataController.inf | 204 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.inf | 130 + .../IA32DEBUG/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32DEBUG/IA32/SmmAccess.efi | Bin 0 -> 10336 bytes .../IA32DEBUG/IA32/SmmAccess.inf | 210 + .../IA32DEBUG/IA32/SmmControl.depex | 1 + .../IA32DEBUG/IA32/SmmControl.efi | Bin 0 -> 11776 bytes .../IA32DEBUG/IA32/SmmControl.inf | 129 + .../IA32DEBUG/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/VlvInitDxe.efi | Bin 0 -> 26656 bytes .../IA32DEBUG/IA32/VlvInitDxe.inf | 259 + .../IA32DEBUG/IA32/VlvInitPeim.depex | 1 + .../IA32DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../IA32DEBUG/IA32/VlvInitPeim.inf | 116 + .../IA32RELEASE/IA32/CpuPeim.depex | 1 + .../IA32RELEASE/IA32/CpuPeim.efi | Bin 0 -> 6080 bytes .../IA32RELEASE/IA32/CpuPeim.inf | 123 + .../IA32/DigitalThermalSensor.depex | 1 + .../IA32RELEASE/IA32/DigitalThermalSensor.efi | Bin 0 -> 6144 bytes .../IA32RELEASE/IA32/DigitalThermalSensor.inf | 182 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.efi | Bin 0 -> 3872 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf | 213 + .../IA32RELEASE/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 9216 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.inf | 259 + .../IA32RELEASE/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.efi | Bin 0 -> 6144 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf | 241 + .../IA32RELEASE/IA32/MemoryInit.depex | 1 + .../IA32RELEASE/IA32/MemoryInit.efi | Bin 0 -> 93888 bytes .../IA32RELEASE/IA32/MemoryInit.inf | 196 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32/PchBiosWriteProtect.depex | 1 + .../IA32RELEASE/IA32/PchBiosWriteProtect.efi | Bin 0 -> 2560 bytes .../IA32RELEASE/IA32/PchBiosWriteProtect.inf | 121 + .../IA32RELEASE/IA32/PchEarlyInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchEarlyInitPeim.efi | Bin 0 -> 14752 bytes .../IA32RELEASE/IA32/PchEarlyInitPeim.inf | 97 + .../IA32RELEASE/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/PchInitDxe.efi | Bin 0 -> 61536 bytes .../IA32RELEASE/IA32/PchInitDxe.inf | 272 + .../IA32RELEASE/IA32/PchInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchInitPeim.efi | Bin 0 -> 11776 bytes .../IA32RELEASE/IA32/PchInitPeim.inf | 136 + .../IA32RELEASE/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/PchInitSmm.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PchInitSmm.inf | 284 + .../IA32RELEASE/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32RELEASE/IA32/PchPcieSmm.efi | Bin 0 -> 11264 bytes .../IA32RELEASE/IA32/PchPcieSmm.inf | 245 + .../IA32RELEASE/IA32/PchPolicyInitDxe.depex | 1 + .../IA32RELEASE/IA32/PchPolicyInitDxe.efi | Bin 0 -> 2368 bytes .../IA32RELEASE/IA32/PchPolicyInitDxe.inf | 109 + .../IA32RELEASE/IA32/PchReset.depex | 1 + .../IA32RELEASE/IA32/PchReset.efi | Bin 0 -> 3584 bytes .../IA32RELEASE/IA32/PchReset.inf | 130 + .../IA32RELEASE/IA32/PchS3SupportDxe.depex | 1 + .../IA32RELEASE/IA32/PchS3SupportDxe.efi | Bin 0 -> 13472 bytes .../IA32RELEASE/IA32/PchS3SupportDxe.inf | 251 + .../IA32/PchSmbusArpDisabled.depex | 1 + .../IA32RELEASE/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 3136 bytes .../IA32RELEASE/IA32/PchSmbusArpDisabled.inf | 130 + .../IA32RELEASE/IA32/PchSmbusDxe.depex | 1 + .../IA32RELEASE/IA32/PchSmbusDxe.efi | Bin 0 -> 4832 bytes .../IA32RELEASE/IA32/PchSmbusDxe.inf | 206 + .../IA32RELEASE/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.efi | Bin 0 -> 12288 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.inf | 175 + .../IA32RELEASE/IA32/PchSpiPeim.depex | 1 + .../IA32RELEASE/IA32/PchSpiPeim.efi | Bin 0 -> 4384 bytes .../IA32RELEASE/IA32/PchSpiPeim.inf | 125 + .../IA32RELEASE/IA32/PchSpiRuntime.depex | 1 + .../IA32RELEASE/IA32/PchSpiRuntime.efi | Bin 0 -> 10240 bytes .../IA32RELEASE/IA32/PchSpiRuntime.inf | 252 + .../IA32RELEASE/IA32/PchSpiSmm.depex | 1 + .../IA32RELEASE/IA32/PchSpiSmm.efi | Bin 0 -> 9728 bytes .../IA32RELEASE/IA32/PchSpiSmm.inf | 245 + .../IA32RELEASE/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.efi | Bin 0 -> 1344 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.inf | 124 + .../IA32RELEASE/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32RELEASE/IA32/PciHostBridge.efi | Bin 0 -> 9792 bytes .../IA32RELEASE/IA32/PciHostBridge.inf | 248 + .../IA32RELEASE/IA32/PeiSmmAccess.depex | 1 + .../IA32RELEASE/IA32/PeiSmmAccess.efi | Bin 0 -> 1664 bytes .../IA32RELEASE/IA32/PeiSmmAccess.inf | 119 + .../IA32RELEASE/IA32/PeiSmmControl.depex | 1 + .../IA32RELEASE/IA32/PeiSmmControl.efi | Bin 0 -> 960 bytes .../IA32RELEASE/IA32/PeiSmmControl.inf | 95 + .../IA32RELEASE/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.efi | Bin 0 -> 8064 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.inf | 216 + .../IA32RELEASE/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.efi | Bin 0 -> 9664 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.inf | 200 + .../IA32RELEASE/IA32/PowerManagement2.depex | 1 + .../IA32RELEASE/IA32/PowerManagement2.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PowerManagement2.inf | 264 + .../IA32RELEASE/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/SataController.efi | Bin 0 -> 3264 bytes .../IA32RELEASE/IA32/SataController.inf | 195 + .../IA32RELEASE/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi | Bin 0 -> 1856 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf | 101 + .../IA32RELEASE/IA32/SecCore.efi | Bin 0 -> 8000 bytes .../IA32RELEASE/IA32/SecCore.inf | 152 + .../IA32RELEASE/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32RELEASE/IA32/SmmAccess.efi | Bin 0 -> 1984 bytes .../IA32RELEASE/IA32/SmmAccess.inf | 198 + .../IA32RELEASE/IA32/SmmControl.depex | 1 + .../IA32RELEASE/IA32/SmmControl.efi | Bin 0 -> 3072 bytes .../IA32RELEASE/IA32/SmmControl.inf | 122 + .../IA32RELEASE/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/VlvInitDxe.efi | Bin 0 -> 16640 bytes .../IA32RELEASE/IA32/VlvInitDxe.inf | 253 + .../IA32RELEASE/IA32/VlvInitPeim.depex | 1 + .../IA32RELEASE/IA32/VlvInitPeim.efi | Bin 0 -> 3104 bytes .../IA32RELEASE/IA32/VlvInitPeim.inf | 101 + .../Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h | 72 + .../Vlv2SocBinPkg/Microcode/M0130673321.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130678806.inc | 12800 +++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679901.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679906.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679907.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M023067221D.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0F30679909.inc | 13056 ++++++++++++++++ .../Microcode/MicrocodeUpdates.inf | 51 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/I211PcieUndiDxe/X64/E7006X3.EFI | Bin 0 -> 341536 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/IA32/RtkUndiDxe.efi | Bin 0 -> 78368 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/X64/RtkUndiDxe.efi | Bin 0 -> 92064 bytes Silicon/Intel/Vlv2SocBinPkg/Vlv2SocBinPkg.dec | 36 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.inf | 137 + .../X64DEBUG/IA32/MemoryInit.depex | 1 + .../X64DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../X64DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../X64DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../X64DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../X64DEBUG/IA32/PchInitPeim.depex | 1 + .../X64DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../X64DEBUG/IA32/PchInitPeim.inf | 150 + .../X64DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../X64DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../X64DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../X64DEBUG/IA32/PchSpiPeim.depex | 1 + .../X64DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../X64DEBUG/IA32/PchSpiPeim.inf | 139 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.inf | 137 + .../X64DEBUG/IA32/PeiSmmAccess.depex | 1 + .../X64DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../X64DEBUG/IA32/PeiSmmAccess.inf | 132 + .../X64DEBUG/IA32/PeiSmmControl.depex | 1 + .../X64DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../X64DEBUG/IA32/PeiSmmControl.inf | 110 + .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.inf | 130 + .../X64DEBUG/IA32/VlvInitPeim.depex | 1 + .../X64DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../X64DEBUG/IA32/VlvInitPeim.inf | 116 + .../X64DEBUG/X64/DigitalThermalSensor.depex | 1 + .../X64DEBUG/X64/DigitalThermalSensor.efi | Bin 0 -> 32768 bytes .../X64DEBUG/X64/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/X64DEBUG/X64/Dptf.depex | Bin 0 -> 108 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.efi | Bin 0 -> 29120 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.inf | 219 + .../X64DEBUG/X64/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../X64DEBUG/X64/GraphicDxeInitSmm.efi | Bin 0 -> 54272 bytes .../X64DEBUG/X64/GraphicDxeInitSmm.inf | 265 + .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.efi | Bin 0 -> 39328 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.inf | 247 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64DEBUG/X64/PchBiosWriteProtect.depex | 1 + .../X64DEBUG/X64/PchBiosWriteProtect.efi | Bin 0 -> 26624 bytes .../X64DEBUG/X64/PchBiosWriteProtect.inf | 130 + .../X64DEBUG/X64/PchInitDxe.depex | Bin 0 -> 126 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.efi | Bin 0 -> 176256 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf | 278 + .../X64DEBUG/X64/PchInitSmm.depex | Bin 0 -> 162 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.efi | Bin 0 -> 67072 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchInitSmm.inf | 290 + .../X64DEBUG/X64/PchPcieSmm.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.efi | Bin 0 -> 55808 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchPcieSmm.inf | 251 + .../X64DEBUG/X64/PchPolicyInitDxe.depex | 1 + .../X64DEBUG/X64/PchPolicyInitDxe.efi | Bin 0 -> 23616 bytes .../X64DEBUG/X64/PchPolicyInitDxe.inf | 123 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.efi | Bin 0 -> 29184 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf | 137 + .../X64DEBUG/X64/PchS3SupportDxe.depex | 1 + .../X64DEBUG/X64/PchS3SupportDxe.efi | Bin 0 -> 58368 bytes .../X64DEBUG/X64/PchS3SupportDxe.inf | 257 + .../X64DEBUG/X64/PchSmbusDxe.depex | 1 + .../X64DEBUG/X64/PchSmbusDxe.efi | Bin 0 -> 35328 bytes .../X64DEBUG/X64/PchSmbusDxe.inf | 214 + .../X64DEBUG/X64/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../X64DEBUG/X64/PchSmiDispatcher.efi | Bin 0 -> 53760 bytes .../X64DEBUG/X64/PchSmiDispatcher.inf | 181 + .../X64DEBUG/X64/PchSpiRuntime.depex | 1 + .../X64DEBUG/X64/PchSpiRuntime.efi | Bin 0 -> 50688 bytes .../X64DEBUG/X64/PchSpiRuntime.inf | 258 + .../X64DEBUG/X64/PchSpiSmm.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.efi | Bin 0 -> 54272 bytes .../Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf | 251 + .../X64DEBUG/X64/PciHostBridge.depex | Bin 0 -> 54 bytes .../X64DEBUG/X64/PciHostBridge.efi | Bin 0 -> 49856 bytes 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+Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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=3DA$|AIE;~o)0A2Vih;f9w|9hH_i|y zyi6}2eD-YNsw;-24_i+F+57>-9Cej?n~o`%PcMxHUE^ntjl7dlGIK1Y@a{}>4^mN? zJe%#T;`hDk^NAX+>4L69+SUD^hWhgPl}_PL%2Dt;x>sO1$IJ#&3zd zpc>bN=3DQ<;}Y)-qEX9L1X#ZRq@+{!Sa)#J4w6vHh<)#Gjx+$yX1b7Oy%IM}{m8`GF)F<%@d(wZhBiPs} zG+bnnLl(MtE-iF( z%DlEvoX6i(n8&lK(92UV%;D>`g~NGP6=3DpD{4vLZ);$QZ{x}4*xfI-A45vr)i;kihO zhY_f%w;@~#*~lz}f<}l_m+CBBP7K>n3UTgXl|)KJYAVuqDL&`0Bpph+R0o!NRFeEU zslhHXTPC%N9#)syRHwA^T!nh`94A6)%KE^gH_wtrb$jYk?I?zWAayjNWtKx9zgvqT z{!b-DnJ#kB>u+9`sgK`M*M7*QH{a|=3DU(QR$q)Q+FMqvE**tXavVkjDX2}`kAdUIfK zqRUm+{!wQ37KAO4_Y!2F0;&a>O6u@3#loazACA16+dM1VpZ)jdKyGs&&!2s?IWVL- z;B5{d*9qr{{|;yV>PX1xnKe{vswx~D&XS*@p>rd%hK`B_tjLf%H?!Fa4`of5HPj{J z&k}Ms6vDuz`ld~md@;YW<=3Dgn0UgVQAy`qrW_p9Pl&O%z}U5k6O34V2WL;C0mIytXT zoeDv0+}(3=3Dz?k1tgih67*v4k*F3^pXRFV)7+Ek zEOlb#CR+$>u*`vCc=3D_@0IC+&tK44V!T-=3D`!*P`tn^KQwTvsXF>c8gM{W%@}mmf@=3D0 z)TE{$=3DCO z)*e3@I_m)LJVqU@Pg2(xd-z>t``_+iiHsoQss<6yK31MDj^Tf$Go7xF7o0MNQm-md zx(HqV?~?g{=3D%huq?cfG0EHLAfN@L5>e}mMTmf~@JDp1rb*Si(d*Nr^Reu`IbsA4v~u6kN$>|D)GJ)Y)7hdah-R$UO4Kg_dA2? zyzgfPqaE1C>&!p+k@t^>>%8CLQ*v;nailW7v@G?xG~qX&S=3DHLD+p&Y@ouDSr->M54 z6~?E_w;{mW7A)R#^mjpg=3DN`0b8(QZ*l(6cdj$_neY&-fpcm#4Fvj4o7V?D_i%-Lv1 zN%>kVA&Qm#`g2MJ!E_B@i*>0U<=3D1)dP5j+kpKy3b4y;l2id*MWZ#(r$`2z~4Ic)lP zuj*IF?^P$95*r#RMb}Bur}pIcR*C7JSieE!2rIW8+vusQBwr}Iszq*8a~#_m+|wP( zx0(mldyNH, ). Points should = be "=0D + "listed in monotonically increasing order by ambient light= "=0D + "illuminance (lux). A minimum of two points are required = "=0D + "(min and max)."=0D + EndPage=0D +=0D + EndPage=0D + EndPage =0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Display Configuration=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Display Configuration"=0D +=0D + Link "LFP" , "LFP"=0D + Link "CRT" , "CRT"=0D + Link "EFP 1" , "EFP 1"=0D + Link "EFP 2" , "EFP 2"=0D + =0D + TitleB "DisplayPort SSC configuration: " =0D + Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum= Clock:", &Disabled_Enabled_List,=0D + Help "This feature allow OEMs to enable/disable SSC for external Displ= ayPort. "=0D + "This feature is valid only the attached DisplayPort panel support SSC= . "=0D + "\r\n"=0D +=0D + Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/D= isable for Dongles:", &Disabled_Enabled_List,=0D + Help "This feature is to enable or disable DisplayPort Dongle Spread S= pectrum Clock when dongle are used "=0D + "and the attached DisplayPort panel should support SSC\r\n"=0D +=0D + =0D + Page "LFP"=0D + Link "Close Table", ".."=0D + =0D + Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration",= &eDP_Config_List,=0D + Help "This option select Device type. Save the configuration af= ter selecting this field to see display related settings."=0D +=0D + ; #IF ($Int_LFP1_Type =3D=3D 0x1806)=0D + Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_list,=0D + Help "This feature specifies which DVO port the device is "=0D + ;#ENDIF=0D + =0D + Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channe= l_List,=0D + Help "This feature specifies the AUX Channel for int-DisplayPort. "=0D + "This field is valid only if integrated DP is selected for Device Type.= " =0D + =0D + ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List,= =0D + ;Help "This feature will select if the panel is primary or not.= "=0D + ; "The VLV platform has only one panel fitter. So, stretche= d mode will be only applicable "=0D + ; "to primary panel . In secondary panel only native mode o= r "=0D + ; "centering modes will be supported."=0D + =0D + Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, =0D + Help "This feature selects the Local Flat Panel (LFP) the VBIOS= "=0D + "and driver is to enable.\r\n" =0D + "\r\n"=0D + "Note, a valid return from the system BIOS hook 5F40h will= "=0D + "replace this default value.\r\n"=0D + "\r\n"=0D + "Default LFP parameter values:\r\n"=0D + "\tPANEL #01: 640x480 LVDS\r\n"=0D + "\tPANEL #02: 800x600 LVDS\r\n"=0D + "\tPANEL #03: 1024x768 LVDS\r\n"=0D + "\tPANEL #04: 1280x1024 LVDS\r\n "=0D + "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n"=0D + "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n"=0D + "\tPANEL #07: 1600x1200 LVDS\r\n"=0D + "\tPANEL #08: 1280x768 LVDS\r\n"=0D + "\tPANEL #09: 1680x1050 LVDS\r\n"=0D + "\tPANEL #10: 1920x1200 LVDS\r\n"=0D + "\tPANEL #11: Reserved\r\n"=0D + "\tPANEL #12: Reserved\r\n "=0D + "\tPANEL #13: Reserved\r\n"=0D + "\tPANEL #14: 1280x800 LVDS\r\n"=0D + "\tPANEL #15: 1280x600 LVDS\r\n"=0D + "\tPANEL #16: Reserved" =0D + =0D + Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", = &Disabled_Enabled_List,=0D + Help "This feature, when enabled, will activate support for a L= FP "=0D + "with an EDID. The video BIOS and drivers will load the E= DID "=0D + "and use its data to set appropriate timing on current pan= el. "=0D + "If disabled, there will be no attempt to read an EDID and= other methods "=0D + "will be used to set panel timing."=0D + "\r\n\r\nNote: The backlight data may need to be updated.= " =0D + "\r\n The option on page Gen= eral"=0D + " Features must be correct for platform."=0D + =0D + Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Ye= s_List,=0D + Help "This feature when set to yes, will enable 180 Degree rotation = "=0D + "otherwise, the rotation functionality will be disabled."=0D + =0D + Combo $Enable_Correction, "Gamma/Brightness/Contrast Correction Enable:"= , &Disabled_Enabled_List,=0D + Help "This option will allow users to disable/enable Gamma/Brightness/Co= ntrast correction feature for eDP. By default it will be disabled.\r\n"=0D + "On enabling one can find option for entering values for Red/Blue/Gree= n Palette Table under LFP Panel configuration.\r\n"=0D + "Each Red/Blue/Green Palette Table has 256 entries/rows of 1-byte each= . Enter required values in these fields.\r\n"=0D + =0D + EndPage =0D + =0D + =0D +=0D + Page "CRT"=0D + Link "Close Window" , ".."=0D +=0D + Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_Lis= t,=0D + Help "This option select CRT Device."=0D +=0D + Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_Lis= t,=0D + Help "This feature specifies the GPIO pin pair "=0D + "used as DDC bus by this device. If this device "=0D + "doesn't support DDC bus, this field will be ignored."=0D +=0D + EndPage=0D +=0D + Page "EFP 1"=0D + Link "Close Window" , ".."=0D +=0D + Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List,= =0D + Help "This option specifies the Device Type."=0D +=0D + Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List,=0D + Help "This feature specifies which DVO port the device is "=0D +=0D + Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List= ,=0D + Help "This feature specifies the GPIO pin pair "=0D + "used as DDC bus by this device. If this device "=0D + "doesn't support DDC bus, this field will be ignored."=0D + =0D + Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_= List,=0D + Help "This feature specifies the AUX Channel for int-DisplayPort. "=0D + "This field is valid only if integrated DP is selected for Devic= e Type." =0D + =0D + Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configura= tion:", &Hdmi_LS_List_VLV,=0D + Help "This feature specifies the Level shifter configuration for HDMI. "= =0D + "This field is valid only if HDMI is selected for Device Type."=0D + =0D + ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_En= abled_List,=0D + ;Help "This option Enables/Disables detection of type of dongle= connected to DP port.\r\n"=0D + ; "This option is used only by the GFX driver."=0D +=0D + Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List,=0D + Help "This field describes if the Display Port is routed through Dock or= not." =0D + =0D + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Config= uration"=0D + =0D + Page "DisplayPort Redriver Configuration"=0D +=0D + Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_Lis= t,=0D + Help "This feature will describe if Non-dock topology/OnBoard Redriver = DP Link is present or not."=0D +=0D + Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_P= reEmp_List,=0D + Help "This feature allows for the selection of "=0D + "Pre-emphasis level for the OnBoard redriver DP link.\n"=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + =0D + Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of "=0D + "Voltage Swing level for the OnBoard redriver DP link.\n"=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + =0D + Title " "=0D +=0D + Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &N= o_Yes_List,=0D + Help "This feature will describe if Dock Topology/Dock Redriver DP Link= is present or not.\r\n\r\n"=0D + "Note: For Dock Topology to work SBIOS should implement a GOP Policy = Protocol to provide the"=0D + " docking status of the platform to GOP.\n"=0D + =0D + Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_Pr= eEmp_List,=0D + Help "This feature allows for the selection of "=0D + "Pre-emphasis level for the Dock redriver DP link."=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VS= wing_List,=0D + Help "This feature allows for the selection of "=0D + "Voltage Swing level for the Dock redriver DP link."=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + EndPage ; "DisplayPort Redriver Configuration"=0D + =0D + EndPage=0D +=0D + =0D + Page "EFP 2"=0D + Link "Close Window" , ".."=0D +=0D + Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List= ,=0D + Help "This option specifies the Device Type."=0D +=0D + Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List,=0D + Help "This feature specifies which DVO port the device is "=0D + =0D + Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List= ,=0D + Help "This feature specifies the GPIO pin pair "=0D + "used as DDC bus by this device. If this device "=0D + "doesn't support DDC bus, this field will be ignored."=0D + =0D + Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel= _List,=0D + Help "This feature specifies the AUX Channel for int-DisplayPort. "=0D + "This field is valid only if integrated DP is selected for Devic= e Type." =0D +=0D + Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configura= tion:", &Hdmi_LS_List_VLV,=0D + Help "This feature specifies the Level shifter configuration for HDMI. "= =0D + "This field is valid only if HDMI is selected for Device Type."=0D + =0D + ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disab= led_Enabled_List,=0D + ;Help "This option Enables/Disables detection of type of dongle= connected to DP port.\r\n"=0D + ; "This option is used only by the GFX driver."=0D + =0D + Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List,=0D + Help "This field describes if the Display Port is routed through Dock or= not." =0D + =0D + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Config= uration"=0D + =0D + Page "DisplayPort Redriver Configuration"=0D +=0D + Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_Lis= t,=0D + Help "This feature will describe if Non-dock topology/OnBoard Redriver = DP Link is present or not."=0D +=0D + Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_P= reEmp_List,=0D + Help "This feature allows for the selection of "=0D + "Pre-emphasis level for the OnBoard redriver DP link.\n"=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + =0D + Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of "=0D + "Voltage Swing level for the OnBoard redriver DP link.\n"=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + =0D + Title " "=0D +=0D + Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &N= o_Yes_List,=0D + Help "This feature will describe if Dock Topology/Dock Redriver DP Link= is present or not.\r\n\r\n"=0D + "Note: For Dock Topology to work SBIOS should implement a GOP Policy = Protocol to provide the"=0D + " docking status of the platform to GOP.\n"=0D +=0D + Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_Pr= eEmp_List,=0D + Help "This feature allows for the selection of "=0D + "Pre-emphasis level for the Dock redriver DP link."=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VS= wing_List,=0D + Help "This feature allows for the selection of "=0D + "Voltage Swing level for the Dock redriver DP link."=0D + "\r\n\n\t\t\tDefault Swing Setting Table\n" =0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t \t | \t\t PreEmphasis Levels\t\t |\n"= =0D + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n "=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n"=0D + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n"=0D + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n"=0D + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n"=0D + "\t-------------------------------------------------------------------= --------------------------------\n"=0D + "\tColumn - Non-Transition VDiff \r\n"=0D + "\tRow - Transition VDiff \r\n"=0D +=0D + EndPage ; "DisplayPort Redriver Configuration"=0D + =0D + EndPage=0D + =0D + =0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=0D +; Page - LFP Panel configuration=0D +;-------------------------------------------------------------------------= ---=0D +Page "LFP Panel configuration"=0D + Link "Panel #1 ", "Panel #1 "=0D + Link "Panel #2 ", "Panel #2 "=0D + Link "Panel #3 ", "Panel #3 "=0D + Link "Panel #4 ", "Panel #4 "=0D + Link "Panel #5 ", "Panel #5 "=0D + Link "Panel #6 ", "Panel #6 "=0D + Link "Panel #7 ", "Panel #7 "=0D + Link "Panel #8 ", "Panel #8 "=0D + Link "Panel #9 ", "Panel #9 "=0D + Link "Panel #10 ", "Panel #10 "=0D + Link "Panel #11 ", "Panel #11 "=0D + Link "Panel #12 ", "Panel #12 "=0D + Link "Panel #13 ", "Panel #13 "=0D + Link "Panel #14 ", "Panel #14 "=0D + Link "Panel #15 ", "Panel #15 "=0D + Link "Panel #16 ", "Panel #16 "=0D +#if($Enable_Correction =3D=3D 1)=0D + Link "RGB Palette Table ", "RGB Palette Table "=0D +#endif =0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #1 (640x480) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #1 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_01, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver only. Pane= l name can be only of 13 characters maximum and rest of the characters will= be truncated. "=0D +=0D + Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_01, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D +=0D + Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List= ,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D +=0D + Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_Li= st,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D + =0D + Combo $eDP_VswingPreEmph_1, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D +=0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D + =0D + EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D +=0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it." =0D + =0D + Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_01, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-Emphasis Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_01, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + EndPage=0D + =0D + #endif=0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_01 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_01 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D + EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D +=0D + EndPage=0D + =0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #2 (800x600) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #2 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_02, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_02, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_2, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephasis = table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_02, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Combo $eDP_Link_Vswing_Level_02, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_02 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_02 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D + EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #3 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_03, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_03, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806) =0D + TitleB "Integrated eDP Features" =0D + =0D + Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D +=0D + Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_3, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD en= able until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryin= g the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D +=0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_03, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level value for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_03, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D +=0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_03 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_03 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #4 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_04, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_04, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D +=0D +=0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D +=0D + Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_4, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D + Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon af= ter VDD enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time be= fore trying the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D +=0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_04, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Combo $eDP_Link_Vswing_Level_04, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_04 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_04 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D + =0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #5 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_05, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_05, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D +=0D + Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + =0D +=0D + Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_5, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D + Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D +=0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_05, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_05, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_05 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_05 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #6 (1400x1050) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #6 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_06, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_06, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled= _List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + =0D + Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_6, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D +=0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_06, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_06, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_06 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_06 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +=0D +=0D +EndPage=0D +=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #7 (1600x1200) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #7 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_07, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_07, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D +=0D + Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_7, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_07, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_07, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_07 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_07 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #8 (1280x768) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #8 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_08, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_08, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + =0D + Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_8, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_08, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + =0D + Combo $eDP_Link_Vswing_Level_08, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_08 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_08 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D + EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #9 (1680x1050) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #9 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_09, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_09, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806) =0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_9, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D + =0D + EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_09, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_09, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_09 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_09 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarit= y_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC= ,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #10 (1920x1200) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #10 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_10, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_10, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features" =0D + =0D + Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n "=0D + Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_10, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D + Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_10, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Combo $eDP_Link_Vswing_Level_10, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_10 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_10 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #11 (Reserved) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #11 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_11, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_11, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D +=0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + "This feature selects the Vswing Pre-emph settings to be used.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Fea= ture Supported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_11, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_11, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_11 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_11 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #12 (Reserved) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #12 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_12, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_12, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D +=0D + Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_12, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_12, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_12, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_12 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_12 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #13 (Reserved) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #13 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_13, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_13, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D +=0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features"=0D + =0D + Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D + =0D +=0D + Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_13, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_13, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Combo $eDP_Link_Vswing_Level_13, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_13 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_13 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #14 (1280x800) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #14 "=0D +=0D + TitleB "Common LFP Features" =0D +=0D + EditText $Panel_Name_14, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_14, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features" =0D + =0D + Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_14, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D +=0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D + =0D + EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_14, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + =0D + Combo $eDP_Link_Vswing_Level_14, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_14 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_14 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #15 (1280x600) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #15 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_15, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_15, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features" =0D + =0D + Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D +=0D + Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_15, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D + =0D + EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D + =0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_15, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + Combo $eDP_Link_Vswing_Level_15, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D + =0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_15 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_15 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D +=0D + EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Panel #16 (Reserved) Flat Panel parameters=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Panel #16 "=0D +=0D + TitleB "Common LFP Features" =0D + =0D + EditText $Panel_Name_16, "\tLFP Panel Name:", =0D + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. "=0D +=0D + Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List,= =0D + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n"=0D + "from Target X-Res and Target Y-Res fields.\r\n"=0D +=0D + EditNum $Panel_Width_16, "\tTarget X-Res:", DEC,=0D + Help "This value specifies the Target X-Resolution for this panel."= =0D +=0D + EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC,=0D + Help "This value specifies the Target Y-Resolutoin for this panel."= =0D +=0D + =0D + Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st,=0D + Help "This feature allows OEM to select the DPS Panel Type.\r\n "= =0D + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n"=0D + "which reduces display power\r\n"=0D + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n"=0D + "rate will not adversely impact the user experience\r\n"=0D + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n"=0D + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n"=0D + "rate switching, which eliminates the screen blink that occur= red\r\n" =0D + "during the refresh rate transitions\r\n"=0D +=0D + EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC,=0D + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n"=0D + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n"=0D + =0D + Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type= _List,=0D + Help "This feature allows OEM to select the Backlight Technology.\= r\n "=0D +=0D + Title " " =0D + Link "LFP PnP ID Table" , "LFP PnP ID"=0D + Link "DTD Timings Table" , "DTD Timings"=0D + Link "Backlight Control Parameters" , "Backlight Control Parameter= s"=0D + =0D + #if ($Int_LFP1_Type =3D=3D 0x1806)=0D + TitleB "Integrated eDP Features" =0D + =0D + Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List,=0D + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n "=0D + =0D + Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List,=0D + Help "This feature specifies the color depth of eDP panel used. "=0D +=0D + Combo $eDP_VswingPreEmph_16, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List,=0D + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n"=0D + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n"= =0D + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D + =0D + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing"=0D + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration"=0D + =0D + Page "eDP Panel Power Sequencing"=0D + Link "Close Table", ".."=0D +=0D + Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List= ,=0D + Help "This feature enables or disables T3 optimization. \r\n"=0D + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n"=0D + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction"=0D +=0D + EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", D= EC,=0D + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n"=0D + "Valid Range: 0 to 200msec\r\n"=0D +=0D + EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Back= light Enable delay (T8):", DEC,=0D + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n"=0D + "T8 is inclusive of T7.\r\n"=0D + "Valid Range of T7: 0 to 50msec\r\n"=0D +=0D + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enab= le delay:", DEC,=0D + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n"=0D + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n"=0D + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n"=0D +=0D + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to P= WM-Off delay:", DEC,=0D + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n"=0D + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n"=0D + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n"=0D + =0D + EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC,=0D + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n"=0D + =0D + EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data t= o Power-Off delay (T10):", DEC,=0D + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n"=0D + "Valid Range: 0 to 500 msec\r\n"=0D +=0D + EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC,=0D + Help "Using this field Power-off time can be specified in 100uS.\r= \n"=0D +=0D + EndPage=0D +=0D + Page "eDP Fast Link Training Configuration"=0D +=0D + Link "Close Table" , ".."=0D + Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature S= upported:", &No_Yes_List,=0D + Help "This feature if set to Yes will enable "=0D + "Fast Link Training for eDp, if Panel also supports it."=0D + =0D + Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate= _List,=0D + Help "This feature allows for the selection of the "=0D + "Data Rate for the embedded DP link. It will be used if th= e "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCo= unt_List,=0D + Help "This feature allows for the selection of the "=0D + "Lane Count (Port Width) for the embedded DP link. It will= be used if the "=0D + "sink indicates that no aux handshake is required during l= ink training."=0D +=0D + Combo $eDP_Link_PreEmp_Level_16, " PreEmph Level:", &eDP_Link_= PreEmp_List,=0D + Help "This feature allows for the selection of the "=0D + "Pre-emphasis level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + =0D + Combo $eDP_Link_Vswing_Level_16, " VSwing Level:", &eDP_Link_V= Swing_List,=0D + Help "This feature allows for the selection of the "=0D + "Voltage Swing Level for the embedded DP link."=0D + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n"=0D + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n"=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n"=0D + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n"=0D + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n"=0D + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n"=0D + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n= "=0D + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n"=0D + "Column - Non-Transition VDiff \r\n"=0D + "Row - Transition VDiff \r\n"=0D +=0D + EndPage=0D + =0D + #endif=0D +=0D + Page "DTD Timings"=0D + =0D + Link "Close Table" , ".."=0D +=0D + Table $DVO_Tbl_16 " DTD Timings Values",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This feature allows for the definition of the DTD "=0D + "timings parameters related to the LFP. The "=0D + "table is the 18-byte DTD structure defined in the "=0D + "VESA EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D +=0D + EndPage=0D +=0D + Page "LFP PnP ID"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $LVDS_PnP_ID_16 " LFP PnP ID Values",=0D + Column "PnP ID" , 1 byte , EHEX,=0D + Help "This feature allows the 10 bytes of EDID Vendor / "=0D + "Product ID starting at offset 08h to be used as a "=0D + "PnP ID.\r\n"=0D + "\r\n"=0D + " Table Definition:\r\n"=0D + " Word: ID Manufacturer Name\r\n"=0D + " Word: ID Product Code\r\n"=0D + " DWord: ID Serial Number\r\n"=0D + " Byte: Week of Manufacture\r\n"=0D + " Byte: Year of Manufacture"=0D +=0D + EndPage=0D +=0D + Page "Backlight Control Parameters"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List,=0D + Help "This feature allows for the selection of the "=0D + "Backlight Inverter type that is to be used to "=0D + "control the backlight brightness of the LFP. When "=0D + "PWM is selected, the driver and VBIOS will control "=0D + "the backlight brightness via the integrated PWM "=0D + "solution for the applicable chipsets. When I2C is "=0D + "selected, the driver and VBIOS will control the "=0D + "backlight brightness via the I2C solution for the "=0D + "applicable chipsets. When None/External is "=0D + "selected, the system BIOS will control the backlight "=0D + "brightness via the external solution."=0D +=0D + Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_P= wm_Source_List,=0D + Help "This field allows to select the Source of the PWM to be used "= =0D + "for the selected Local Flat Panel.\r\n"=0D + "\r\n"=0D + =0D + Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polari= ty_List,=0D + Help "This feature allows the backlight inverter polarity "=0D + "to be specified.\r\n"=0D + "\r\n"=0D + "Normal means 0 value is minimum brightness.\r\n"=0D + "Inverted means 0 value is maximum brightness."=0D +=0D + EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC,=0D + Help "This feature allows defining the absolute minimum "=0D + "backlight brightness setting. The graphics driver "=0D + "will never decrease the backlight less than this "=0D + "value. The value must be specified using normal "=0D + "polarity semantics."=0D +=0D +EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC,=0D + Help "This feature is used to set default brightness value at P= OST."=0D + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. "=0D +=0D + EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DE= C,=0D + Help "This feature allows for the definition of the "=0D + "frequency needed for PWM Inverter.\r\n"=0D + "\r\n"=0D + "Note: The frequency range, entered as a decimal "=0D + "number, for the integrated PWM is 200Hz - 40KHz."=0D + EndPage=0D + =0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - RGB Palette Table=0D +;-------------------------------------------------------------------------= -----=0D +#if($Enable_Correction =3D=3D 1)=0D +Page "RGB Palette Table"=0D + Link "Red Palette Table" , "Red Palette Table"=0D + Link "Green Palette Table", "Green Palette Table"=0D + Link "Blue Palette Table", "Blue Palette Table"=0D + =0D + Page "Red Palette Table"=0D + Link "Close Table" , ".."=0D + Table $Red_Table "Red Palette Table",=0D + Column "Red", 1 byte, EHEX,=0D + Help "Enter values for Red Palette. Allowed range for entering values in= each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal."= =0D + EndPage=0D + =0D + Page "Green Palette Table"=0D + Link "Close Table" , ".."=0D + Table $Green_Table "Green Palette Table",=0D + Column "Green", 1 byte, EHEX,=0D + Help "Enter values for Green Palette. Allowed range for entering values = in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal= ."=0D + EndPage=0D + =0D + Page "Blue Palette Table"=0D + Link "Close Table" , ".."=0D + Table $Blue_Table "Blue Palette Table",=0D + Column "Blue", 1 byte, EHEX,=0D + Help "Enter values for Blue Palette. Allowed range for entering values i= n each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal.= "=0D + EndPage=0D +EndPage =0D +#endif=0D +=0D + =0D +EndPage ; "Integrated LFP Features"=0D +=0D + =0D + =0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Display Device Toggle Lists=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Display Device Toggle Lists"=0D +=0D + Link "Toggle/Capabilities List 1" , "Display Toggle List 1"=0D + Link "Toggle/Capabilities List 2" , "Display Toggle List 2"=0D + Link "Toggle/Capabilities List 3" , "Display Toggle List 3"=0D + Link "Toggle/Capabilities List 4" , "Display Toggle List 4"=0D +=0D + Page "Display Toggle List 1"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $Toggle_List1 "Display Toggle List 1",=0D + Column "Display Select", 2 bytes, EHEX=0D + Column "Reserved", 1 byte, DEC,=0D + Help "These toggle lists are used by the video BIOS and "=0D + "device drivers to help support the system BIOS with "=0D + "switch display device Hot Keys. The basic algorithm "=0D + "in the current display is found on the list and the "=0D + "next settable display combination is set. If no "=0D + "settable display combinations are found the function "=0D + "returns fail.\r\n"=0D + "\r\n"=0D + "The video BIOS will 'OR' the bits of the two pipes "=0D + "together to create a single pipe display device. "=0D + "The Intel developed drivers will use the display "=0D + "lists as they are. The divers also use this list to "=0D + "get pipe information for ACPI switch display device "=0D + "Hot Keys. Four lists are given to allow for multiple "=0D + "Hot Keys or creative solutions.\r\n"=0D + "\r\n"=0D + "Display Select (Refer to VBIOS HLD for valid "=0D + "selections):\r\n"=0D + "\r\n"=0D + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"=0D + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"=0D + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"=0D + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT"=0D +=0D + EndPage=0D +=0D + Page "Display Toggle List 2"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $Toggle_List2 "Display Toggle List 2",=0D + Column "Display Select", 2 bytes, EHEX=0D + Column "Reserved", 1 byte, DEC,=0D + Help "These toggle lists are used by the video BIOS and "=0D + "device drivers to help support the system BIOS with "=0D + "switch display device Hot Keys. The basic algorithm "=0D + "in the current display is found on the list and the "=0D + "next settable display combination is set. If no "=0D + "settable display combinations are found the function "=0D + "returns fail.\r\n"=0D + "\r\n"=0D + "The video BIOS will 'OR' the bits of the two pipes "=0D + "together to create a single pipe display device. "=0D + "The Intel developed drivers will use the display "=0D + "lists as they are. The divers also use this list to "=0D + "get pipe information for ACPI switch display device "=0D + "Hot Keys. Four lists are given to allow for multiple "=0D + "Hot Keys or creative solutions.\r\n"=0D + "\r\n"=0D + "Display Select (Refer to VBIOS HLD for valid "=0D + "selections):\r\n"=0D + "\r\n"=0D + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"=0D + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"=0D + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"=0D + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT"=0D +=0D + EndPage=0D +=0D + Page "Display Toggle List 3"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $Toggle_List3 "Display Toggle List 3",=0D + Column "Display Select", 2 bytes, EHEX=0D + Column "Reserved", 1 byte, DEC,=0D + Help "These toggle lists are used by the video BIOS and "=0D + "device drivers to help support the system BIOS with "=0D + "switch display device Hot Keys. The basic algorithm "=0D + "in the current display is found on the list and the "=0D + "next settable display combination is set. If no "=0D + "settable display combinations are found the function "=0D + "returns fail.\r\n"=0D + "\r\n"=0D + "The video BIOS will 'OR' the bits of the two pipes "=0D + "together to create a single pipe display device. "=0D + "The Intel developed drivers will use the display "=0D + "lists as they are. The divers also use this list to "=0D + "get pipe information for ACPI switch display device "=0D + "Hot Keys. Four lists are given to allow for multiple "=0D + "Hot Keys or creative solutions.\r\n"=0D + "\r\n"=0D + "Display Select (Refer to VBIOS HLD for valid "=0D + "selections):\r\n"=0D + "\r\n"=0D + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"=0D + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"=0D + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"=0D + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT"=0D +=0D + EndPage=0D +=0D + Page "Display Toggle List 4"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $Toggle_List4 "Display Toggle List 4",=0D + Column "Display Select", 2 bytes, EHEX=0D + Column "Reserved", 1 byte, DEC,=0D + Help "These toggle lists are used by the video BIOS and "=0D + "device drivers to help support the system BIOS with "=0D + "switch display device Hot Keys. The basic algorithm "=0D + "in the current display is found on the list and the "=0D + "next settable display combination is set. If no "=0D + "settable display combinations are found the function "=0D + "returns fail.\r\n"=0D + "\r\n"=0D + "The video BIOS will 'OR' the bits of the two pipes "=0D + "together to create a single pipe display device. "=0D + "The Intel developed drivers will use the display "=0D + "lists as they are. The divers also use this list to "=0D + "get pipe information for ACPI switch display device "=0D + "Hot Keys. Four lists are given to allow for multiple "=0D + "Hot Keys or creative solutions.\r\n"=0D + "\r\n"=0D + "Display Select (Refer to VBIOS HLD for valid "=0D + "selections):\r\n"=0D + "\r\n"=0D + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"=0D + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"=0D + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT"=0D + EndPage=0D +=0D +EndPage=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Modes Removal Table=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Modes Removal Table"=0D +=0D + Table $Mode_Rem_Table "Modes Removal Table",=0D + Column "X-Resolution", 2 bytes, DEC=0D + Column "Y-Resolution", 2 bytes, DEC =0D + Column "BPP", 1 byte, DEC =0D + Column "Refresh Rate", 2 bytes, EHEX =0D + Column "Removal Flags", 1 byte, EHEX =0D + Column "Panel Type", 2 bytes, EHEX,=0D + Help "This feature allows removing support for selected modes "=0D + "resolutions.\r\n"=0D + "\r\n"=0D + "X-Resolution, Y-Resolution, and BPP in Decimal or "=0D + "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n"=0D + "\r\n"=0D + "Refresh Rate bitmap selection (0 =3D Do not remove, 1 =3D "=0D + "Remove):\r\n"=0D + "\r\n"=0D + "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n"=0D + "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n"=0D + "\r\n"=0D + "Removal Flags bitmap selection (0 =3D Do not remove, 1 =3D "=0D + "Remove):\r\n"=0D + "\r\n"=0D + "\tBit 7 6 5 4 3 2= 1 0 \r\n"=0D + "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n"= =0D + "\r\n"=0D + "\tNote: 1) In order to remove mode from both Windows and DOS, "=0D + "both Bit 1 and Bit 0 must be set to 1.\r\n"=0D + "\r\n"=0D + "(Mobile only) Panel Type bitmap selection (0 =3D Do not "=0D + "remove, 1 =3D Remove if panel is active):/r/n"=0D + "\r\n"=0D + "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n"=0D + "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n"=0D + "\r\n"=0D + "\tNote: Default is to remove a mode resolution from all "=0D + "panel types."=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - Display Configuration Removal Table=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "Display Configuration Removal Table"=0D +=0D + Table $Dev_Removed_Table " Display Device Configuration Removal Tab= le",=0D + Column "Pipe B" , 1 byte , BIN=0D + Column "Pipe A" , 1 byte , BIN, =0D + =0D + Help "This feature allows blocking selected display configurations = "=0D + "by the video BIOS and driver.\r\n"=0D + "\r\n"=0D + "Display Devices are specified in the following bit patterns "=0D + "(pipe A and B use the same bit pattern):\r\n"=0D + "\r\n"=0D + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"=0D + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n"=0D + "\r\n"=0D + "Examples:\r\n"=0D + "\tPipe B Pipe A\r\n"=0D + "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n"=0D + "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on "=0D + "Pipe A"=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=0D +; Page - OEM Customizable Mode 2.0=0D +;-------------------------------------------------------------------------= -----=0D +=0D +Page "OEM Customizable Modes 2.0"=0D +=0D + Link "OEM Mode 1 Configuration", "OEM Mode #1"=0D + Link "OEM Mode 2 Configuration", "OEM Mode #2"=0D + Link "OEM Mode 3 Configuration", "OEM Mode #3"=0D + Link "OEM Mode 4 Configuration", "OEM Mode #4"=0D + Link "OEM Mode 5 Configuration", "OEM Mode #5"=0D + Link "OEM Mode 6 Configuration", "OEM Mode #6" =0D +=0D + Page "OEM Mode #1"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 60h / VESA mode 160h"=0D + Title " 16 bpp =3D VGA mode 61h / VESA mode 161h"=0D + Title " 32 bpp =3D VGA mode 62h / VESA mode 162h"=0D +=0D + EditNum $OEM_Mode_Flags1, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags1, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D + EditNum $OEM_Mode_X1, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y1, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color1, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD1 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D + =0D + Page "OEM Mode #2"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 63h / VESA mode 163h"=0D + Title " 16 bpp =3D VGA mode 64h / VESA mode 164h"=0D + Title " 32 bpp =3D VGA mode 65h / VESA mode 165h"=0D +=0D + EditNum $OEM_Mode_Flags2, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags2, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D +=0D + EditNum $OEM_Mode_X2, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y2, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color2, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D +=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD2 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D +=0D + Page "OEM Mode #3"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 66h / VESA mode 166h"=0D + Title " 16 bpp =3D VGA mode 67h / VESA mode 167h"=0D + Title " 32 bpp =3D VGA mode 68h / VESA mode 168h"=0D +=0D + EditNum $OEM_Mode_Flags3, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags3, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D +=0D + EditNum $OEM_Mode_X3, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y3, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color3, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D +=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD3 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D +=0D + Page "OEM Mode #4"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 69h / VESA mode 169h"=0D + Title " 16 bpp =3D VGA mode 6Ah / VESA mode 16Ah"=0D + Title " 32 bpp =3D VGA mode 6Bh / VESA mode 16Bh"=0D +=0D + EditNum $OEM_Mode_Flags4, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags4, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D +=0D + EditNum $OEM_Mode_X4, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y4, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color4, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D +=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD4 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D +=0D + Page "OEM Mode #5"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 6Ch / VESA mode 16Ch"=0D + Title " 16 bpp =3D VGA mode 6Dh / VESA mode 16Dh"=0D + Title " 32 bpp =3D VGA mode 6Eh / VESA mode 16Eh"=0D +=0D + EditNum $OEM_Mode_Flags5, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags5, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D +=0D + EditNum $OEM_Mode_X5, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y5, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color5, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D +=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD5 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D +=0D + Page "OEM Mode #6"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Title " 8 bpp =3D VGA mode 6Fh / VESA mode 16Fh"=0D + Title " 16 bpp =3D VGA mode 70h / VESA mode 170h"=0D + Title " 32 bpp =3D VGA mode 71h / VESA mode 171h"=0D +=0D + EditNum $OEM_Mode_Flags6, "Support Flags:", BIN,=0D + Help "Support flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tDriver"=0D + "\tVBIOS"=0D + "\r\n"=0D + =0D + EditNum $OEM_Display_Flags6, "Display Flags:", BIN,=0D + Help "Display Flags:"=0D + "(0 =3D Disabled, 1 =3D Enabled)"=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tLFP2"=0D + "\tEFP2"=0D + "\tTV2"=0D + "\tCRT2"=0D + "\tLFP"=0D + "\tEFP"=0D + "\tTV"=0D + "\tCRT"=0D + "\r\n"=0D +=0D + Title "Mode Characteristics"=0D +=0D + EditNum $OEM_Mode_X6, " X Resolution:", DEC,=0D + Help "X Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Y6, " Y Resolution:", DEC,=0D + Help "Y Resolution in pixels (decimal)."=0D +=0D + EditNum $OEM_Mode_Color6, " Color Depth:", BIN,=0D + Help "Color Depth, bits can be set simultaneously (binary)."=0D + "\r\n\r\n"=0D + "\tBit 7"=0D + "\tBit 6"=0D + "\tBit 5"=0D + "\tBit 4"=0D + "\tBit 3"=0D + "\tBit 2"=0D + "\tBit 1"=0D + "\tBit 0"=0D + "\r\n"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\tRsvd"=0D + "\t32 BPP"=0D + "\t16 BPP"=0D + "\t8 BPP"=0D + "\r\n"=0D +=0D + EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC,=0D + Help "Refresh rate for OEM customizable mode (decimal)."=0D +=0D + Link "18 Bytes DTD" , "DTD"=0D +=0D + Page "DTD"=0D +=0D + Link "Close Table" , ".."=0D +=0D + Table $OEM_Mode_DTD6 " Detailed Timings Descriptor",=0D + Column "Timings" , 1 byte , EHEX,=0D + Help "This table is the 18-byte DTD(Detailed Timings"=0D + " Descriptor) structure defined in the VESA"=0D + " EDID version 1.x.\r\n" =0D + "\r\n"=0D + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n"=0D + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n"=0D + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"=0D + "\tDB ?\t; Vertical Active in lines, LSB\r\n"=0D + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"=0D + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n"=0D + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"=0D + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"=0D + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"= =0D + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"=0D + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"= =0D + "\tDB ?\t; Horizontal Image Size, LSB\r\n"=0D + "\tDB ?\t; Vertical Image Size, LSB\r\n"=0D + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"=0D + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"= =0D + "\tDB 0\t; Horizontal Border in pixels\r\n"=0D + "\tDB 0\t; Vertical Border in lines\r\n"=0D + "\tDB ?\t; Flags:\r\n"=0D + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n"=0D + "\t \t; Bit 6-5: 00 =3D Reserved\r\n"=0D + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n"=0D + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n"=0D + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n"=0D + "\t \t; Bit 0: 0 =3D Reserved"=0D + EndPage=0D + EndPage=0D +EndPage=0D +=0D +=0D +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=0D +; End of File=0D +;-------------------------------------------------------------------------= -----=0D + =0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex b/Sil= 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# CpuPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for CPU module=0D +#=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D CpuPeim=0D + FILE_GUID =3D 01359d99-9446-456d-ada4-50a711c03adb=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PeimInitializeCpu=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|CpuPeim.efi=0D + PEI_DEPEX|CpuPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x27B0=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiMasterBootModePpiGuid=0D +=0D +=0D + gEfiSecPlatformInformationPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiPlatformCpuInfoGuid=0D +=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSenso= r.depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.d= epex new file mode 100644 index 0000000..4cbdd53 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.depex @@ -0,0 +1 @@ +=02=B7=BF=CC=F4=E0=F6=FDG=9D=D4=10=A8=F1P=C1=91=02=DC=C6=A3=18=EA^=C8H=A1= =C1=B53=89=F9=89=99=02H=1EN=072=81=A1G=8C,?=14=AD=9Af=DC=02=05=A6=DD?n=A7FO= =AD)=12=F4S=1B=3D=08=02Y(mEK=A8GN=A2=EE2v=D8=86=99}=02=F6=F0=A3=13J&=F0>=F2= =E0=DE=C5=124/4=02t+p=C2=0C=801A=87F=8F=B5=B8=9C=E4=AC=02=DDk=E0=FF=07a=A6F= {=B2Z=9C~=C5'\=02=8E=08=97=EB=DF=CF=C6I=BEK=D9=06=A5=B2=0E=86=03=03=03=03= =03=03=03=03=08 \ No newline at end of file diff --git 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a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSenso= r.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf new file mode 100644 index 0000000..da142b4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf @@ -0,0 +1,190 @@ +#/*++=0D +# This file contains an 'Intel Peripheral Driver' and uniquely=0D +# identified as "Intel Reference Module" and is=0D +# licensed for Intel CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#--*/=0D +#=0D +#/*++=0D +#=0D +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved=0D +#This software and associated documentation (if any) is furnished=0D +#under a license and may only be used or copied in accordance=0D +#with the terms of the license. Except as permitted by such=0D +#license, no part of this software or documentation may be=0D +#reproduced, stored in a retrieval system, or transmitted in any=0D +#form or by any means without the express written consent of=0D +#Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# DigitalThermalSensor.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the DigitalThermalSensor SMM driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D DigitalThermalSensor=0D + FILE_GUID =3D 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InstallDigitalThermalSensor=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|DigitalThermalSensor.efi=0D + SMM_DEPEX|DigitalThermalSensor.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 410=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3418=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiSmmIoTrapDispatch2ProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + gEfiMpServiceProtocolGuid=0D +=0D + gEfiSmmSxDispatch2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gEfiSetupVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookL= ib/Smm/DTSHookLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmI= o/PlatSmmIo.inf=0D +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/= SmmKscLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2Proto= colGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfi= MpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAcc= ess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolG= uid AND gEfiAcpiSdtProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED.=0D +#=0D +#**/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D Dptf=0D + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D DptfDriverEntry=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|Dptf.efi=0D + DXE_DEPEX|Dptf.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D48=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= D40=0D +=0D +=0D +[Protocols.IA32]=0D + # CONSUMED=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiAcpiTableProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEfiI2cBusProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf=0D +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# DRIVER_BINDING =3D gSampleDrvDriverBinding=0D +# COMPONENT_NAME =3D gSampleDrvComponentName=0D +# COMPONENT_NAME2 =3D gSampleDrvComponentName2=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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zic6pAJJX;EFJjC}bBH<2tTu<6Bg~Oz)~qo{ndh3L%{sFl(x*WFh2~7N)tqNuYA!+i cl$-753Uig2GuN88nCr|9=3DB;=3Dyb+ym`2d|H6AOHXW literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf b/Silico= n/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf new file mode 100644 index 0000000..0806799 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf @@ -0,0 +1,247 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# IspDxe.inf=0D +#=0D +# Abstract:=0D +#=0D +#=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D ISPDxe=0D + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D ISPDxeEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|ISPDxe.efi=0D + DXE_DEPEX|ISPDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x4= 110=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x4118=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MemoryInit.depex b/= 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+# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# MemoryInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for MemoryInit module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D MemoryInit=0D + FILE_GUID =3D D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PeimMemoryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|MemoryInit.efi=0D + PEI_DEPEX|MemoryInit.depex=0D +=0D +[PatchPcd.IA32]=0D + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6FF8=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D + gSeCUmaPpiGuid=0D +=0D + gSeCfTPMPpiGuid=0D +=0D + gVlvMmioPolicyPpiGuid=0D +=0D + gPeiCapsulePpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiVlv2VariableGuid=0D +=0D + gEfiMemoryConfigDataGuid=0D +=0D +=0D + gEfiAcpiVariableGuid=0D +=0D +=0D + gEfiPlatformInfoGuid=0D +=0D + gEfiSetupVariableGuid=0D +=0D + gEfiMemoryOverwriteControlDataGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_EN= ABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_= ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OP= TIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTI= ONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D= 1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /D= PCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D= LPDDR2_SUPPORT=3D0 /D DDR3_SUPPORT=3D1 /D LPDDR3_SUPPORT=3D0 /D DEBUG_MODE= =3D1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=3D1=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIF= irmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/= IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIFirmware= -LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchEarlyInitPeim.inf new file mode 100644 index 0000000..ca923c9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchEarlyInitPeim.inf @@ -0,0 +1,97 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchEarlyInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the PCH Early Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchEarlyInitPeim=0D + FILE_GUID =3D D9F5B28C-9FF1-47D6-B503-3DC23BD345FF=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchEarlyInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchEarlyInitPeim.efi=0D + PEI_DEPEX|PchEarlyInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 40=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 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'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchInitDxe.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for Pch Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchInitDxe=0D + FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE823=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchInitEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchInitDxe.efi=0D + DXE_DEPEX|PchInitDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6C50=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x16C58=0D +=0D +=0D +[Protocols.IA32]=0D + ## CONSUMES=0D + gDxePchPlatformPolicyProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPchS3SupportProtocolGuid=0D +=0D + ## PRODUCES=0D + gEfiPchInfoProtocolGuid=0D +=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiPciHostBridgeResourceAllocationProtocolGuid=0D +=0D + ## PRODUCES=0D + gLpssDummyProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gEfiPlatformInfoGuid=0D +=0D + gEfiEventExitBootServicesGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +=0D +[Depex.IA32]=0D +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocol= Guid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocol= Guid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AN= D gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTime= rArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArc= hProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProt= ocolGuid AND gEfiAcpiSdtProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the PCH Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchInitPeim=0D + FILE_GUID =3D FD236AE7-0791-48c4-B29E-29BDEEE1A838=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallPchInitPpi=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchInitPeim.efi=0D + PEI_DEPEX|PchInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 2B0=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + ## CONSUMES=0D + gEfiPeiMemoryDiscoveredPpiGuid=0D +=0D + ## CONSUMES=0D + gPchPlatformPolicyPpiGuid=0D +=0D + gEfiPeiStallPpiGuid=0D +=0D + gPchPeiInitPpiGuid=0D +=0D + gPchUsbPolicyPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## HOB=0D + gEfiPlatformInfoGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# gPchPlatformPolicyPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitSmm.depex b/= Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitSmm.depex new file mode 100644 index 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zls~6@&ZapJ&-u?ePtN)8IXmb0=3Dlp%n`*Tju`DTv6X13XEmA3U5_0P5rTc7PMTVnG3 zO6$)6-^Q!0V~KJfN@ z%KnstDKbV`XfLx@+THeF*`Kh}KNcXrX0}`HHjJKT&$KVH=3Dhz+g0{e1%seQG*%I>n) z**Dk)dy{<&B-3i&Zhz4Jko{r%Blbt_kJ+EJKV^T${+#^<`!4$)d#8QBz1Plh{~HTE B!?*wd literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf= b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf new file mode 100644 index 0000000..92b2912 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +#=0D +# This file contains an 'Intel Peripheral Driver' and is=0D +# licensed for Intel CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +## @file=0D +# Component description file for Pch Initialization driver=0D +#=0D +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
= =0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +##=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchS3SupportDxe=0D + FILE_GUID =3D 14537da0-222a-4bbe-9a5c-212a3cbca9ef=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchS3SupportEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchS3SupportDxe.efi=0D + DXE_DEPEX|PchS3SupportDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 020=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x6028=0D +=0D +=0D +[Protocols.IA32]=0D + # PROTOCOL ALWAYS_PRODUCED=0D + gEfiPchS3SupportProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadFileProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadFile2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleFileSystemProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiFileInfoGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +=0D +[Depex.IA32]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled= .depex b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.dep= ex new file mode 100644 index 0000000..028e7ac --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.depex @@ -0,0 +1 @@ +=025=E4=B6c=BC2=C6I=81=BD=B7=A1=A0=FE=1Al=02=90oL=1Fk=B0=D8H=A2=01=BA=E5= =F1=CD}V=03=08 \ No newline at end of file diff --git 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/dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.inf @@ -0,0 +1,144 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSmbusArpDisabled.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PchSmbus module=0D +# This version will NOT include ARP support.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSmbusArpDisabled=0D + FILE_GUID =3D D82D57AC-99F9-4c7a-B591-BBCF8A0E7FBE=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePchSmbusPeim=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchSmbusArpDisabled.efi=0D + PEI_DEPEX|PchSmbusArpDisabled.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= C80=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C88=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiStallPpiGuid=0D +=0D + gEfiPeiMemoryDiscoveredPpiGuid=0D +=0D + gEfiPeiSmbus2PpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiVLVTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D +=0D +[PcdEx.IA32]=0D + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# gPeiSmbusPolicyPpiGuid AND gEfiPeiStallPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## 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V(RSTl-GJ^x-7($g(Bt3x`adK;!qNZ$ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.in= f b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf new file mode 100644 index 0000000..37a8491 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf @@ -0,0 +1,181 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSmiDispatcher.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the Pch SMI Dispatch Handlers module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSmiDispatcher=0D + FILE_GUID =3D 6BE18C9C-BF61-499e-88EC-5CD57430460C=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InitializePchSmmDispatcher=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchSmiDispatcher.efi=0D + SMM_DEPEX|PchSmiDispatcher.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 010=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5018=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiPciRootBridgeIoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D +=0D +=0D + gEfiSmmIchnDispatchExProtocolGuid=0D +=0D + gEfiSmmIchnDispatchProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + gEfiSmmPowerButtonDispatch2ProtocolGuid=0D +=0D + gEfiSmmSxDispatch2ProtocolGuid=0D +=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Prot= ocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfi= MetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfi= RealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntime= ArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocol= Guid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid= AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiPeim.depex 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSpiPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SPI PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSpiPeim=0D + FILE_GUID =3D AA652CB9-2D52-4624-9FAE-D4E58B67CA46=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallPchSpi=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchSpiPeim.efi=0D + PEI_DEPEX|PchSpiPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 700=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gPeiSpiPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC (EBC is for build on= ly)=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 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zet$NTg*g@Cyfq;{;U3dU(_Ygg^Q-1h%{I#)EM2gjpQdb0*^>UJbc1!0m02PGH`!U1 zT+2L5fyHJiu~b;9Ac0zo(^79~ws4kK%Q{P&rQNd8@`z=3DVmM39{TP#n5-d4+Y j%Pz}bE!~#=3DmVV2Np#G}mqy?Q*48}v3V1QQt&;R~6ge$xH literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf b/Sil= icon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf new file mode 100644 index 0000000..0129198 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf @@ -0,0 +1,251 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSpiSmm.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SPI SMM driver.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSpiSmm=0D + FILE_GUID =3D 27F4917B-A707-4aad-9676-26DF168CBF0D=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InstallPchSpi=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchSpiSmm.efi=0D + SMM_DEPEX|PchSpiSmm.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 800=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5808=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiSmmSpiProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoc= olGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBas= e2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGu= id AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMo= notonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gE= fiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArc= hProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoc= olGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGu= id)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex b/Sili= con/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex new file mode 100644 index 0000000..05a6cfe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex @@ -0,0 +1 @@ +=02H=D7=08t=8C=FC=E6N=92=88=C4=BE=C0=92=A4=10=02s=05+=C0N+1J=A3=1A=94V{PD,= =03=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi b/Silico= n/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi new file mode 100644 index 0000000000000000000000000000000000000000..9593093310385bcda923d6bbe58= 9bcdd756ada1a GIT binary patch literal 5984 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.inf @@ -0,0 +1,137 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchUsb.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PCH USB PEIM=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchUsb=0D + FILE_GUID =3D 3B873142-4252-49eb-BF17-105CD6F3E808=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePchUsb=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchUsb.efi=0D + PEI_DEPEX|PchUsb.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 660=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1668=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gPeiUsbControllerPpiGuid=0D +=0D + gPchUsbPolicyPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiMasterBootModePpiGuid AND gPchUsbPolicyPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SmmControl.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SmmControl module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiSmmControl=0D + FILE_GUID =3D FF456B9C-0DC7-4682-9E92-0DE84B6E4067=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmControlPeiDriverEntryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PeiSmmControl.efi=0D + PEI_DEPEX|PeiSmmControl.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 310=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiSmmControl2ProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) 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a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.i= nf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf new file mode 100644 index 0000000..71d8f67 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PlatformCpuPolicy.inf @@ -0,0 +1,227 @@ +#=0D +# This file contains an 'Intel Peripheral Driver' and is=0D +# licensed for Intel CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PlatformCpuPolicy.inf=0D +#=0D +# Abstract:=0D +#=0D +# Platform CPU driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PlatformCpuPolicy=0D + FILE_GUID =3D cb933912-df8f-4305-b1f9-7b44fa11395c=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PlatformCpuPolicy.efi=0D + DXE_DEPEX|PlatformCpuPolicy.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= C70=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3C78=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiPlatformCpuProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiStatusCodeRuntimeProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gEfiPlatformCpuInfoGuid=0D +=0D + gEfiSetupVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf= =0D +=0D +[Depex.IA32]=0D +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid A= ND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArch= ProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid = AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolG= uid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiS= ecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWrite= ArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArch= ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 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--- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf @@ -0,0 +1,270 @@ +#/*++=0D +# This file contains an 'Intel Peripheral Driver' and uniquely=0D +# identified as "Intel Reference Module" and is=0D +# licensed for Intel CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#--*/=0D +#=0D +#/*++=0D +#=0D +#Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +#This software and associated documentation (if any) is furnished=0D +#under a license and may only be used or copied in accordance=0D +#with the terms of the license. Except as permitted by such=0D +#license, no part of this software or documentation may be=0D +#reproduced, stored in a retrieval system, or transmitted in any=0D +#form or by any means without the express written consent of=0D +#Intel Corporation.=0D +#=0D +#Module Name:=0D +#=0D +# PowerManagement.inf=0D +#=0D +#Abstract:=0D +#=0D +# Component description file for Power Management module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PowerManagement2=0D + FILE_GUID =3D 41E89AB0-BD3D-44b6-A431-E4836EFBF2CB=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InitializePowerManagement=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PowerManagement2.efi=0D + SMM_DEPEX|PowerManagement2.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x8208=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x8= 200=0D +=0D +=0D +[Protocols.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gPpmPlatformPolicyProtocolGuid=0D +=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gPowerManagementAcpiTableStorageGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/IstAppl= et/Smm/IstApplet.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/ValleyV= iew/Smm/MchLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/SouthCl= uster/Smm/IchLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/Silverm= ont/Smm/SilvermontPpmLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid = AND gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid A= ND gEfiGlobalNvsAreaProtocolGuid AND gPpmPlatformPolicyProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess= 2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND= gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND= gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRu= ntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchPro= tocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtoco= lGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid= AND gEfiAcpiSdtProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SataController.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PCH SATA controller Driver module.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SataController=0D + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2=0D + MODULE_TYPE =3D UEFI_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializeSataControllerDriver=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SataController.efi=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D40=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiIdeControllerInitProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gSataControllerDriverGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) 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Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +##=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SecCore=0D + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09=0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + MODULE_UNI_FILE =3D SecCore.uni=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + BIN|ResetVec.bin=0D + PE32|SecCore.efi=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 188=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + ## PRODUCES=0D + gEfiSecPlatformInformationPpiGuid=0D +=0D + ## PRODUCES=0D + gEfiTemporaryRamDonePpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf=0D +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf=0D +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf=0D +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf=0D +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.in= f=0D +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf=0D +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +=0D +[Depex.IA32]=0D +=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) 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zjXJCD2f82Wj_3U@uVDH2mal$f(<8rpgyFDpFE?bzM4-ZoBRo-A>&%bHb0Yf^HAEzM^|ow_o=3D&onLoI*RMOK mJE8lf?mgZ6x-+`-I#D;IyQsUO8_|vFn4I_=3D1@hGY^z|Pt%UXW` literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf b/Si= licon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf new file mode 100644 index 0000000..262dfd4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf @@ -0,0 +1,129 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SmmControl.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SmmControl module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmControl=0D + FILE_GUID =3D DD787473-07CE-4c63-82CE-930B33F39C09=0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmControlDriverEntryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SmmControl.efi=0D + DXE_DEPEX|SmmControl.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= A00=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2A08=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiSmmControl2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## CONSUMES ## Event=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D + ## CONSUMES ## Event=0D + gEfiEventExitBootServicesGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D +=0D +[Depex.IA32]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) 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mode 100644 index 0000000..f1ea1ca --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/VlvInitDxe.inf @@ -0,0 +1,259 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitDxe=0D + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|VlvInitDxe.efi=0D + DXE_DEPEX|VlvInitDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= AB0=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5AB8=0D +=0D +=0D +[Protocols.IA32]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D +=0D + gIgdOpRegionProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiCpuIo2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gBmpImageGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid= )=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) 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This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#--*/=0D +#=0D +#/*++=0D +#=0D +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved=0D +#This software and associated documentation (if any) is furnished=0D +#under a license and may only be used or copied in accordance=0D +#with the terms of the license. Except as permitted by such=0D +#license, no part of this software or documentation may be=0D +#reproduced, stored in a retrieval system, or transmitted in any=0D +#form or by any means without the express written consent of=0D +#Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# DigitalThermalSensor.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the DigitalThermalSensor SMM driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D DigitalThermalSensor=0D + FILE_GUID =3D 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InstallDigitalThermalSensor=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|DigitalThermalSensor.efi=0D + SMM_DEPEX|DigitalThermalSensor.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 010=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiSmmIoTrapDispatch2ProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + gEfiMpServiceProtocolGuid=0D +=0D + gEfiSmmSxDispatch2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gEfiSetupVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookL= ib/Smm/DTSHookLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmI= o/PlatSmmIo.inf=0D +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/= SmmKscLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2Proto= colGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfi= MpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAcc= ess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolG= uid AND gEfiAcpiSdtProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## 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zd)a#|;Y^&BOX1SEiQH7q&3%t6=3DazA=3Da%;FcuAU2WZ*jZ1_qZ1BL+%83mh0mF%w6OD m&V9xGi@VPaat2qtYm{reE7Qff=3D44&S`bSn@)}5^3!uTJb($V(- literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf b/Silico= n/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf new file mode 100644 index 0000000..113299d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf @@ -0,0 +1,213 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED.=0D +#=0D +#**/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D Dptf=0D + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D DptfDriverEntry=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|Dptf.efi=0D + DXE_DEPEX|Dptf.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 40=0D +=0D +=0D +[Protocols.IA32]=0D + # CONSUMED=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiAcpiTableProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEfiI2cBusProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf=0D +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# DRIVER_BINDING =3D gSampleDrvDriverBinding=0D +# COMPONENT_NAME =3D gSampleDrvComponentName=0D +# COMPONENT_NAME2 =3D gSampleDrvComponentName2=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D GraphicDxeInitSmm=0D + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|GraphicDxeInitSmm.efi=0D + SMM_DEPEX|GraphicDxeInitSmm.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= E00=0D +=0D +=0D +[Protocols.IA32]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEdkiiSmmReadyToBootProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmEndOfDxeProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D +# MdePkg/Library/SmmIoLib/SmmIoLib.inf=0D +=0D +[Depex.IA32]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data /ALIGN:4096=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) 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'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# IspDxe.inf=0D +#=0D +# Abstract:=0D +#=0D +#=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D ISPDxe=0D + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D ISPDxeEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|ISPDxe.efi=0D + DXE_DEPEX|ISPDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 3F0=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for= =0D +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/MemoryInit.depex = b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/MemoryInit.depex new file mode 100644 index 0000000..4db74a3 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/MemoryInit.depex @@ -0,0 +1 @@ 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SataController.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PCH SATA controller Driver module.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SataController=0D + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2=0D + MODULE_TYPE =3D UEFI_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializeSataControllerDriver=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SataController.efi=0D +=0D +[PatchPcd.IA32]=0D +=0D +[Protocols.IA32]=0D + gEfiIdeControllerInitProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gSataControllerDriverGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +=0D +[Depex.IA32]=0D +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for= =0D +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS 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contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SeCUma.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SeCUma module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SeCUma=0D + FILE_GUID =3D E4CEDF93-672A-4782-A7FD-5FC6D239377D=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SeCUmaEntry=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SeCUma.efi=0D + PEI_DEPEX|SeCUma.depex=0D +=0D +[PatchPcd.IA32]=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiStallPpiGuid=0D +=0D + gSeCUmaPpiGuid=0D +=0D + gPeiSeCPlatformPolicyPpiGuid=0D +=0D +=0D +[Guids.IA32]=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiStallPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO 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Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +##=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SecCore=0D + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09=0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + MODULE_UNI_FILE =3D SecCore.uni=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SecCore.efi=0D + BIN|ResetVec.bin=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= CE8=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + ## PRODUCES=0D + gEfiSecPlatformInformationPpiGuid=0D +=0D + ## PRODUCES=0D + gEfiTemporaryRamDonePpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf=0D +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf=0D +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf=0D +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf=0D +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.in= f=0D +# MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNul= l.inf=0D +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +=0D +[Depex.IA32]=0D +=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SmmControl.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SmmControl module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmControl=0D + FILE_GUID =3D DD787473-07CE-4c63-82CE-930B33F39C09=0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmControlDriverEntryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SmmControl.efi=0D + DXE_DEPEX|SmmControl.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x8= 00=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiSmmControl2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## CONSUMES ## Event=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D + ## CONSUMES ## Event=0D + gEfiEventExitBootServicesGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D +=0D +[Depex.IA32]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitDxe=0D + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|VlvInitDxe.efi=0D + DXE_DEPEX|VlvInitDxe.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 0D0=0D +=0D +=0D +[Protocols.IA32]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D +=0D + gIgdOpRegionProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiCpuIo2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + gBmpImageGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.IA32]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid= )=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for= =0D +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex= b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex new file mode 100644 index 0000000..00c2f8d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex @@ -0,0 +1 @@ +=02=C2=B2=84}=A1"rC=B1,=EB=B22=D3=A6=A3=02=08;=B9=AC=DC\=8FJ=93=D4=06=E3B= =DF=18.=03=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.efi b= /Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.efi new file mode 100644 index 0000000000000000000000000000000000000000..7152888719c4c31ef172a954f6e= 8d03875e95ac7 GIT binary patch literal 3104 zcmbVOeQXow8Gp|{f7G#ab}_0ug~lo8m7$EdHmwNB)|kZEA5Fj^#F z#1Mo_F9Dxl9si(KnzU7XRQ>p`LnSz^3USQh&`JohwY1_7Ot(V70WwCZ5njCKy>rN! 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the VLV Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitPeim=0D + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitPeiEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|VlvInitPeim.efi=0D + PEI_DEPEX|VlvInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gVlvPolicyPpiGuid=0D +=0D + gVlvPeiInitPpiGuid=0D +=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiSetupVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +=0D +[Depex.IA32]=0D +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT=0D +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for= =0D +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h b/Silicon/Inte= l/Vlv2SocBinPkg/Include/Ppi/Cache.h new file mode 100644 index 0000000..b14d40e --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h @@ -0,0 +1,72 @@ +//=0D +// This file contains an 'Intel Peripheral Driver' and is=0D +// licensed for Intel CPUs and chipsets under the terms of your=0D +// license agreement with Intel or your vendor. This file may=0D +// be modified by the user, subject to additional terms of the=0D +// license agreement=0D +//=0D +/** @file=0D +=0D +=0D + Cache PPI definition.=0D +=0D +Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
=0D +This software and associated documentation (if any) is furnished=0D +under a license and may only be used or copied in accordance=0D +with the terms of the license. Except as permitted by such=0D +license, no part of this software or documentation may be=0D +reproduced, stored in a retrieval system, or transmitted in any=0D +form or by any means without the express written consent of=0D +Intel Corporation.=0D +=0D +**/=0D +=0D +#ifndef _PEI_CACHE_PPI_H_=0D +#define _PEI_CACHE_PPI_H_=0D +=0D +#define PEI_CACHE_PPI_GUID \=0D + { \=0D + 0xc153205a, 0xe898, 0x4c24, {0x86, 0x89, 0xa4, 0xb4, 0xbc, 0xc5, 0xc8,= 0xa2 } \=0D + }=0D +=0D +typedef struct _PEI_CACHE_PPI PEI_CACHE_PPI;=0D +=0D +//=0D +// EFI_MEMORY_CACHE_TYPE=0D +//=0D +typedef INT32 EFI_MEMORY_CACHE_TYPE;=0D +=0D +//=0D +// PEI_SET_CACHE_PPI=0D +//=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PEI_SET_CACHE_PPI) (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN PEI_CACHE_PPI *This,=0D + IN EFI_PHYSICAL_ADDRESS MemoryAddress,=0D + IN UINT64 MemoryLength,=0D + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType=0D + );=0D +=0D +//=0D +// PEI_RESET_CACHE_PPI=0D +//=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PEI_RESET_CACHE_PPI) (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN PEI_CACHE_PPI *This=0D + );=0D +=0D +//=0D +// PEI_CACHE_PPI=0D +//=0D +struct _PEI_CACHE_PPI {=0D + PEI_SET_CACHE_PPI SetCache;=0D + PEI_RESET_CACHE_PPI ResetCache;=0D +};=0D +=0D +extern EFI_GUID gPeiCachePpiGuid;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc b/Silico= n/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc new file mode 100644 index 0000000..aefa4e2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc @@ -0,0 +1,13056 @@ +dd 000000001h ; Header Version +dd 000000321h ; Patch ID +dd 001142014h ; DATE +dd 000030673h ; CPUID +dd 0984d6012h ; Checksum +dd 000000001h ; Loader Version +dd 000000001h ; Platform ID +dd 00000cbd0h ; Data size +dd 00000cc00h ; Total size +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h +dd 0000000a1h +dd 000020001h +dd 000000321h +dd 000000000h +dd 000000000h +dd 020140114h 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2005 - 2015, Intel Corporation. All rights reserved +#=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 + +# This program and the accompanying materials are licensed and made availa= ble under + +# the terms and conditions of the BSD License that accompanies this distri= bution.=20=20 + +# The full text of the license may be found at=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20 + +# http://opensource.org/licenses/bsd-license.php.=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20 + +#=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 + +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=20= =20=20=20=20=20=20=20=20=20=20=20 + +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED.=20=20=20=20 + +#=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 + +# +# +# Module Name: +# +# MicrocodeUpdates.inf +# +# Abstract: +# +# List all of the microcode updates that you want included at build tim= e. +# +#--*/ + +[defines] +BASE_NAME =3D MicrocodeUpdates +FILE_GUID =3D 1FAE4D78-CB33-4f73-8881-A1EA8F5EDFEF +COMPONENT_TYPE =3D Microcode=20 +FFS_EXT =3D .ffs +MODULE_TYPE =3D USER_DEFINED +=20=20 +[sources.common] +M0F30679909.inc +M0130673321.inc +M0130678806.inc +M023067221D.inc + +[includes.common] + +[libraries.common] + +[nmake.common] diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmwa= re-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/Microcode/Minno= wBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmware-Lice= nseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. Upon termination, the End User m= ust immediately destroy the Software or return all copies. =0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-License= Agreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmwar= e-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-LicenseAgreeme= nt-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.= txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUE= FIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. Upon termination, the End User m= ust immediately destroy the Software or return all copies. =0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMA= XUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/UNDI= /RtkUndiDxe/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMAXUEFIFi= rmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/X64/MinnowBoardMAXUEFIFir= mware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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zlio-=3Dlhlb?^tI&2lTRjJN=3D{74O<9^!m$E%&cS>?s!&t}C}Gw>8(D+liXfmAgH6XYTIYhjaJjKAQVj?%v#ex%+bu{#lUoS2@t2Ap{!@zuoP z#3@NxN$ZlfC;c1v^5>-ZVrj4d0q%TQtPXBuPA?P1t#x0~!#`yhTu}t>^ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf b/Sil= icon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf new file mode 100644 index 0000000..79dd341 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf @@ -0,0 +1,201 @@ +#/*++=0D +# This file contains an 'Intel Peripheral Driver' and uniquely=0D +# identified as "Intel Mobile Silicon Support Module" and is=0D +# licensed for Intel Mobile CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# MemoryInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for MemoryInit module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D MemoryInit=0D + FILE_GUID =3D D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PeimMemoryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|MemoryInit.efi=0D + PEI_DEPEX|MemoryInit.depex=0D +=0D +[PatchPcd.IA32]=0D + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5=0D +=0D + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6FF8=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D + gSeCUmaPpiGuid=0D +=0D + gSeCfTPMPpiGuid=0D +=0D + gVlvMmioPolicyPpiGuid=0D +=0D + gPeiCapsulePpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiVlv2VariableGuid=0D +=0D + gEfiMemoryConfigDataGuid=0D +=0D +=0D + gEfiAcpiVariableGuid=0D +=0D +=0D + gEfiPlatformInfoGuid=0D +=0D + gEfiSetupVariableGuid=0D +=0D + gEfiMemoryOverwriteControlDataGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_EN= ABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_= ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OP= TIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTI= ONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D= 1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /D= PCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D= LPDDR2_SUPPORT=3D0 /D DDR3_SUPPORT=3D1 /D LPDDR3_SUPPORT=3D0 /D DEBUG_MODE= =3D1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=3D1=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFi= rmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA= 32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFirmware-= LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchEarlyInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the PCH Early Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchEarlyInitPeim=0D + FILE_GUID =3D D9F5B28C-9FF1-47D6-B503-3DC23BD345FF=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchEarlyInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchEarlyInitPeim.efi=0D + PEI_DEPEX|PchEarlyInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 40=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 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zdOzt{(&?msCViVENtPvlmb`D)Im|^A4wA_`FiLT|LZeuYG4m?ERU|5RsrIN2sE?`7 zsL!dVYAmQ*k7`=3DkkvO9{ueqX$*6HBWGTm<7N!>Y}1l2@mNHtU#Y7IX(JY(1dPyEer z((s+ZZ)h<-ZTzkARbwA&#v$Ve#^bR1l(7=3DE;%BhXYZ@>`m?h>1%n>EvgVHzvQGyg&KFWaw+*))-yN-O2;X!^#s%Vnq1Q F{{wI`;Cui8 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf b/Si= licon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf new file mode 100644 index 0000000..1a508fc --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf @@ -0,0 +1,150 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the PCH Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchInitPeim=0D + FILE_GUID =3D FD236AE7-0791-48c4-B29E-29BDEEE1A838=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallPchInitPpi=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchInitPeim.efi=0D + PEI_DEPEX|PchInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 2B0=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + ## CONSUMES=0D + gEfiPeiMemoryDiscoveredPpiGuid=0D +=0D + ## CONSUMES=0D + gPchPlatformPolicyPpiGuid=0D +=0D + gEfiPeiStallPpiGuid=0D +=0D + gPchPeiInitPpiGuid=0D +=0D + gPchUsbPolicyPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## HOB=0D + gEfiPlatformInfoGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# gPchPlatformPolicyPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.= depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex new file mode 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/dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSpiPeim.inf @@ -0,0 +1,139 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSpiPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SPI PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSpiPeim=0D + FILE_GUID =3D AA652CB9-2D52-4624-9FAE-D4E58B67CA46=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallPchSpi=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PchSpiPeim.efi=0D + PEI_DEPEX|PchSpiPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 700=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gPeiSpiPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC (EBC is for build on= ly)=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex new file mode 100644 index 0000000..05a6cfe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex @@ -0,0 +1 @@ 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PeiSmmAccess.inf @@ -0,0 +1,132 @@ +#=0D +# This file contains an 'Intel Pre-EFI Module' and is licensed=0D +# for Intel CPUs and Chipsets under the terms of your license=0D +# agreement with Intel or your vendor. This file may be=0D +# modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2009 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SmmAccess.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SmmAccess module=0D +#=0D +# Revision History:=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiSmmAccess=0D + FILE_GUID =3D B4E0CDFC-30CD-4b29-A445-B0AA95A532E4=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmAccessDriverEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PeiSmmAccess.efi=0D + PEI_DEPEX|PeiSmmAccess.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1780=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gPeiSmmAccessPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiPeiFirmwareVolumeInfo2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid.=0D + gEfiFirmwareFileSystem2Guid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob=0D + gEfiHobMemoryAllocStackGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob=0D + gEfiHobMemoryAllocBspStoreGuid=0D +=0D + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob=0D + gEfiHobMemoryAllocModuleGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiMemoryDiscoveredPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS)=0D +## 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SmmControl.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SmmControl module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiSmmControl=0D + FILE_GUID =3D FF456B9C-0DC7-4682-9E92-0DE84B6E4067=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmControlPeiDriverEntryInit=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|PeiSmmControl.efi=0D + PEI_DEPEX|PeiSmmControl.depex=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 310=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318=0D +=0D +=0D +[Protocols.IA32]=0D + gEfiSmmControl2ProtocolGuid=0D +=0D +=0D +[Ppis.IA32]=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +=0D +[Depex.IA32]=0D +# TRUE=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SeCUma.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SeCUma module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SeCUma=0D + FILE_GUID =3D E4CEDF93-672A-4782-A7FD-5FC6D239377D=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SeCUmaEntry=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SeCUma.efi=0D + PEI_DEPEX|SeCUma.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C20=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gEfiPeiStallPpiGuid=0D +=0D + gSeCUmaPpiGuid=0D +=0D + gPeiSeCPlatformPolicyPpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +=0D +[Depex.IA32]=0D +# gEfiPeiStallPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 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This file may be=0D +# modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +## @file=0D +# SecCore module that implements the SEC phase.=0D +# NOTE: This module was replaced by UefiCpuPkg/SecCore/SecCore.inf=0D +#=0D +# This is the first module taking control of the platform upon power-on/r= eset.=0D +# It implements the first phase of the security phase. The entry point fu= nction is=0D +# _ModuleEntryPoint in PlatformSecLib. The entry point function will swit= ch to=0D +# protected mode, setup flat memory model, enable temporary memory and=0D +# call into SecStartup().=0D +#=0D +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
=0D +#=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +##=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SecCore=0D + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09=0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + MODULE_UNI_FILE =3D SecCore.uni=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|SecCore.efi=0D + BIN|ResetVec.bin=0D +=0D +[PatchPcd.IA32]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 188=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + ## PRODUCES=0D + gEfiSecPlatformInformationPpiGuid=0D +=0D + ## PRODUCES=0D + gEfiTemporaryRamDonePpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf=0D +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf=0D +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf=0D +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf=0D +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.in= f=0D +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf=0D +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +=0D +[Depex.IA32]=0D +=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/VlvInitPeim.inf @@ -0,0 +1,116 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the VLV Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitPeim=0D + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitPeiEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|VlvInitPeim.efi=0D + PEI_DEPEX|VlvInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2260=0D +=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gVlvPolicyPpiGuid=0D +=0D + gVlvPeiInitPpiGuid=0D +=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiSetupVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf=0D +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf= =0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +=0D +[Depex.IA32]=0D +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT=0D +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.inf @@ -0,0 +1,219 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED.=0D +#=0D +#**/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D Dptf=0D + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D DptfDriverEntry=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|Dptf.efi=0D + DXE_DEPEX|Dptf.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x69F8=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 9F0=0D +=0D +=0D +[Protocols.X64]=0D + # CONSUMED=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiAcpiTableProtocolGuid=0D +=0D + # CONSUMED=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEfiI2cBusProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf=0D +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# DRIVER_BINDING =3D gSampleDrvDriverBinding=0D +# COMPONENT_NAME =3D gSampleDrvComponentName=0D +# COMPONENT_NAME2 =3D gSampleDrvComponentName2=0D +#=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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z9h_txjAd-nAxYLDOnE&SWc9vV(U~5WWF2-Q(q!~qmLJo_Iwq;Vm2^ZG>xiTQ zlFo9_@trMkrhW2 z^azmfMtlzbM_xjfL&iXy;_pY}#q-^N5q3;IY2LFb@hKvot4fckd4fz`iI9|1KT(d0S RI{&(j>yY{1&;Ljd{2zvYJU;*c literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf= b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf new file mode 100644 index 0000000..4e00475 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf @@ -0,0 +1,265 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D GraphicDxeInitSmm=0D + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|GraphicDxeInitSmm.efi=0D + SMM_DEPEX|GraphicDxeInitSmm.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xC618=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 610=0D +=0D +=0D +[Protocols.X64]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEdkiiSmmReadyToBootProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmEndOfDxeProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D +# MdePkg/Library/SmmIoLib/SmmIoLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO 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agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# IspDxe.inf=0D +#=0D +# Abstract:=0D +#=0D +#=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D ISPDxe=0D + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D ISPDxeEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|ISPDxe.efi=0D + DXE_DEPEX|ISPDxe.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x9= 140=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x9148=0D +=0D +=0D +[Protocols.X64]=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFir= mware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64= /MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFirmware-L= icenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK) =0D +PRODUCTION LICENSE AGREEMENT =0D +=0D +IMPORTANT =96 READ BEFORE COPYING, INSTALLING OR USING. =0D +=0D +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement.=0D +=0D +General Terms and Conditions =0D +=0D +This agreement (=93Agreement=94) is by and between Licensee and Intel Corp= oration, a Delaware corporation, having its principal place of business at = 2200 Mission College Boulevard, Santa Clara, California 95054 (=93Intel=94)= and is effective as of the first date Licensee copies, installs, uses or l= oads the software identified in this Agreement or any associated materials = (=93Effective Date=94). =0D +=0D +1.0 DEFINITIONS =0D +=0D +1.1 =93ASL Code=94 means code written in the =91ACPI source language=92 a= nd designed and delivered to Licensee by Intel and designed to be compatibl= e with Intel products. Such ASL Code remains ASL Code regardless of any le= gends in header files of the ASL Code. =0D +1.2 =93Assembly Code=94 means code written in the =91assembly source lang= uage=92 and designed and delivered to Licensee by Intel under this Agreemen= t. =0D +1.3 =93MBM-UDK=94 means the MinnowBoard MAX UEFI Development Kit, which i= s an Intel implementation of the =0D +UEFI specification, and is based on the Intel=AE UEFI Development Kit 2014= (Intel=AE UDK2014), consisting of =0D +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= . =0D +1.4 =93MBM-UDK Libraries=94 means the core library services offered in th= e MinnowBoard MAX UEFI Development =0D +Kit. =0D +1.5 =93Boot Loader=94 means a device and use-case-specific firmware progr= am a computer=92s processor uses to get the computer system started after p= ower-on, with some basic hardware initialization, until handoff to the oper= ating system. =0D +1.6 =93BSD License=94 means the Berkeley Software Distribution License, w= hich is a family of permissive free software licenses created for the origi= nal Berkeley Software Distribution operating system. =0D +1.7 =93C Code=94 means code written in the =91C source language=92 and de= signed and delivered to Licensee by Intel under this Agreement. =0D +1.8 =93Customer=94 means Original Equipment Manufacturer (a company that = makes computer systems for sale under its own brand name), Independent Auth= orized Developer (a company that performs services for Licensee in the deve= lopment of Licensee=92s products), or Original Design Manufacturer (a compa= ny that =0D +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users. =0D +1.9 =93Derived Object Code=94 means the subset of Derivative Works that i= s the Object Code derived from Source Code or Derived Source Code. =0D +1.10 =93Derived Source Code=94 means the subset of Derivative Works that = is the source code derived from Source Code by modifying the Source Code in= any way. =0D +1.11 =93Derivative Works=94 means those bodies of work defined in 17 U.S.= C. =A7101 as =93derivative works=94 of existing copyrighted material. For = purposes of this Agreement, Derivative Works include both Derived Source Co= de and Derived Object Code. =0D +1.12 =93DXE Driver=94 means Driver Execution Environment driver, which is= a hardware device driver compliant with the execution environment as defin= ed in the UEFI specification. =0D +1.13 =93DXE Foundation Code=94 means the foundational Driver Execution En= vironment code that provides the standard function and services that are av= ailable to the DXE Drivers. =0D +1.14 =93End User=94 means a purchaser or recipient or user of Licensee=92= s computer products who does not resell Licensee=92s products in the normal= course of the End User=92s business. =0D +1.15 =93Firmware=94 means the programming code that is inserted into the = programmable read-only memory of a computer system, thus becoming a permane= nt part of a particular computing device. =0D +1.16 =93Intel Processor=94 means processors designed by Intel and release= d by or on behalf of Intel and marketed under Intel=92s (or Intel licensed)= trademarks. =0D +1.17 =93Licensee=94 means the individual accepting these terms or, if the= individual is accepting these terms on behalf of a legal entity (such as a= corporation, partnership, agency, etc.), =93Licensee=94 means the legal en= tity. =0D +1.18 =93Object Code=94 means the binary version of the Source Code, inclu= ding all computer programming code, entirely in binary form, which is direc= tly executable by a computer and includes those help, message, overlay, and= other files necessary for supporting the intended use of the executable co= de. =0D +1.19 =93PEI Foundation Code=94 means Pre-extensible firmware interface (= =93PEFI=94) initialization foundation code, which performs basic hardware i= nitialization in order to load and execute the DXE Foundation Code. =0D +1.20 =93PEI Modules=94 means PEFI initialization modules, which are code = modules that perform basic environmental set up prior to initialization of = DXE Foundation Code. =0D +1.21 =93Peripheral Drivers=94 means code that initializes and operates ha= rdware devices that are peripheral to the Intel Processor. =0D +1.22 =93Reference Drivers=94 means those drivers supplied as part of the= Source Code that are marked or tagged by Intel as =91reference drivers=92.= =0D +1.23 =93Source Code=94 means the source code of the MB-UDK Libraries and = Reference Drivers delivered to Licensee by Intel under this Agreement, alon= g with all Intel-delivered tools, documentation, specifications, and schema= tics related thereto. =0D +1.24 =93Subsidiaries=94 means, with respect to any legally recognizable e= ntity, any entity Controlling, Controlled by, or under common Control with = the entity. =93Control=94 means (i) ownership of fifty percent (50%) or mo= re of the outstanding shares representing the right to vote for members of = the directors or other managing officers of the entity, or (ii) for an enti= ty which does not have outstanding shares, fifty percent (50%) or more of t= he ownership interest representing the right to make decisions for the enti= ty. An entity will be deemed a Subsidiary only so long as the Control exis= ts. =0D +1.25 =93UDK2014=94 means the Intel=AE UEFI Development Kit 2014 (Intel=AE= UDK2014), which is an openly available implementation of the UEFI framewor= k provided by Intel under BSD License terms. =0D +1.26 =93UEFI=94 means the Unified Extensible Firmware Interface, which i= s an industry standard detailing an interface that helps hand off control o= f the system for the pre-boot environment (i.e., after the system is powere= d on, but before the operating system starts) to an operating system. =0D +=0D +2.0 LICENSE RIGHTS AND CONDITIONS =0D +=0D +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=92= s copyrights to: =0D +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=92s own internal use, to design, develop, modify or debug Derivative Wo= rks that operate in or in conjunction only with Intel Chipsets or Intel Pro= cessors as specified in Exhibit A; =0D +Reproduce and distribute MB-UDK internally for Licensee=92s own use in dev= eloping and maintaining products or services supporting Intel Chipsets or I= ntel Processors as specified in Exhibit A; and =0D +Distribute Object Code and Derived Object Code externally to Licensee=92s = End Users, either directly or through Licensee=92s usual distribution chann= els and methods, but only for use with Intel Chipsets or Intel Processors a= s specified in Exhibit A. Licensee will distribute all Licensed Programs un= der an end user license agreement (=93End User License=94) containing at a = minimum the terms and conditions set forth in Exhibit B. =0D +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following =0D +limitations: =0D +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel; =0D +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee. =0D +Licensee will not use Intel's name or trademarks without prior written per= mission; and =0D +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product. =0D +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=92s o= ther internal or business use or for use in association with any other prod= ucts. Licensee will not license MB-UDK to any third party. Licensee will in= clude all copyright notices in all full and partial copies of the MB-UDK, i= ncluding all Derived Source Code, and will not deface, obscure or alter any= copyright notices. =0D +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =93Feedback= =94), then Licensee grants to Intel a non-exclusive, irrevocable, worldwide= , royalty-free license, including the right to sublicense Intel licensees a= nd customers, under Licensee=92s intellectual property rights in the Feedba= ck, and the rights to use and disclose the Feedback in any manner Intel cho= oses and to display, perform, copy, have copied, make, have made, use, sell= , offer to sell, and otherwise dispose of Intel=92s and its sublicenses=92 = products embodying the Feedback in any manner and via any media Intel choos= es, but without reference to the source of the Feedback. =0D +=0D +3.0 DISCLAIMER OF WARRANTY =0D +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= . =0D +=0D +4.0 LIMITATION OF LIABILITY =0D +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=92s use of the= MB-UDK. =0D +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages. =0D +=0D +5.0 PROTECTION AND SECURITY =0D +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=92s part. =0D +=0D +6.0 ASSIGNMENT, SALE OR TRANSFER =0D +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void. =0D +=0D +TERMINATION =0D +=0D +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=92s receipt of written notice. =0D +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity. =0D +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed. =0D +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =0D +=0D +OWNERSHIP =0D +=0D +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =0D +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=92s suppliers as appropriate, subject to Intel=92s underlying ownership = of the MB-UDK. =0D +=0D +9.0 EXPORT CONTROL =0D +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval. =0D +=0D +GENERAL =0D +=0D +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =92s written request to the other, senior executives of both parties will m= eet to attempt to resolve the dispute. If the senior executives cannot reso= lve the dispute, either party may then make a written demand for formal dis= pute resolution by tendering to the other party notice of the dispute and i= ts intent to invoke the terms of this Section 10.1. The parties agree to me= et within ninety (90) days of the demand with an impartial mediator selecte= d by mutual agreement to participate in a one-day, non-binding mediation. I= n the event the parties cannot agree on a mediator, they will each select o= ne nominator, who will not at that time be employed by either party, and th= e two nominators will agree on and appoint the mediator. If the parties hav= e not resolved the dispute or claim within thirty (30) days after the one-d= ay, non-binding mediation, either party may begin litigation proceedings. = =0D +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties. =0D +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the =0D +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement. =0D +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware. =0D +=0D +[END OF GENERAL TERMS AND CONDITIONS] =0D +=0D +EXHIBIT A =0D +SUPPORTED PLATFORMS =0D + =0D +List of supported platforms with which the MB-UDK may be used: =0D + BayTrail-I Atom E3825, E3845, E3815, =0D + E38xx E3826, E3827 =0D +=0D +EXHIBIT B =0D +MINIMUM OBJECT CODE =0D +END-USER LICENSING TERMS =0D + =0D +Licensee will ensure that terms at least as restrictive and protective of = Intel=92s interests as the following minimum terms, as described below, are= included in all End User Licenses. These minimum terms apply to distributi= on of Licensed Programs (object code) only. =0D +=0D +An End User may: =0D +Copy the Licensed Programs and accompanying materials (=93Software=94) ont= o the End User=92s computers for End User=92s internal use solely for devel= opment and maintenance of the End User=92s products supporting Intel Chipse= ts or Intel Processors. =0D +=0D +An End User may not: =0D +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user. =0D +Reverse engineer, decompile, or disassemble the Software. =0D +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B. =0D +Remove any copyright notices from the Software or any copies thereof. =0D +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government. =0D +=0D +An End User will also be made aware of and agree that: =0D +=0D +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws. =0D +=0D +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information. =0D +=0D +The Software is provided =93AS IS=94 without any express or implied warran= ty of any kind, including warranties =0D +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose. =0D +=0D +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind. =0D +=0D +The technical data and Software covered by this license is a =93Commercial= Item,=94 as the term is defined by the FAR 2.101 (48 C.F.R. 2.101) and is = =93commercial computer software=94 and =93commercial computer software docu= mentation=94 as specified under FAR 12.212 (48 C.F.R. 12.212) or DFARS 227.= 7202 (48 C.F.R. 227.7202), as applicable. This commercial computer software= and related documentation is provided to End Users for use by and on behal= f of the U.S. Government, with only those rights as are granted to all othe= r End Users pursuant to the terms and conditions of the End User License. U= se for or on behalf of the U.S. Government is permitted only if the party a= cquiring or using this software is properly authorized by an appropriate U.= S. Government official. This use by or for the U.S. Government clause is in= lieu of, and supersedes, any other FAR, DFARS, or other provision that add= resses Government rights in the computer software or documentation covered = by this license. =0D +=0D +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchBiosWriteProtect.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the PchBiosWriteProtect driver.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchBiosWriteProtect=0D + FILE_GUID =3D B8B8B609-0B6C-4b8c-A731-DE03A6C3F3DC=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InstallPchBiosWriteProtect=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchBiosWriteProtect.efi=0D + SMM_DEPEX|PchBiosWriteProtect.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= E10=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5E18=0D +=0D +=0D +[Protocols.X64]=0D + gDxePchPlatformPolicyProtocolGuid=0D +=0D + gEfiSmmIchnDispatchProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxePchPlatformPolicyProtocolGuid AND gEfiSmmBase2ProtocolGuid = AND gEfiSmmIchnDispatchProtocolGuid AND gEfiSmmSwDispatch2Protoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProt= ocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmBase2ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf b/Sili= con/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf new file mode 100644 index 0000000..4ace397 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf @@ -0,0 +1,278 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchInitDxe.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for Pch Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchInitDxe=0D + FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE823=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchInitEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchInitDxe.efi=0D + DXE_DEPEX|PchInitDxe.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 93C0=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x293C8=0D +=0D +=0D +[Protocols.X64]=0D + ## CONSUMES=0D + gDxePchPlatformPolicyProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPchS3SupportProtocolGuid=0D +=0D + ## PRODUCES=0D + gEfiPchInfoProtocolGuid=0D +=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiPciHostBridgeResourceAllocationProtocolGuid=0D +=0D + ## PRODUCES=0D + gLpssDummyProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiPlatformInfoGuid=0D +=0D + gEfiEventExitBootServicesGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocol= Guid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocol= Guid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AN= D gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTime= rArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArc= hProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProt= ocolGuid AND gEfiAcpiSdtProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= 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terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchInitSmm.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for Pch Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchInitSmm=0D + FILE_GUID =3D D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D PchInitSmmEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchInitSmm.efi=0D + SMM_DEPEX|PchInitSmm.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xF= 010=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xF018=0D +=0D +=0D +[Protocols.X64]=0D + ## CONSUMES=0D + gDxePchPlatformPolicyProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPchS3SupportProtocolGuid=0D +=0D + ## PRODUCES=0D + gEfiPchInfoProtocolGuid=0D +=0D +=0D + gEfiAcpiTableProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiPciHostBridgeResourceAllocationProtocolGuid=0D +=0D + ## PRODUCES=0D + gLpssDummyProtocolGuid=0D +=0D + gEdkiiSmmReadyToBootProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + ## CONSUMES=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + gEfiAcpiSdtProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmEndOfDxeProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiPlatformInfoGuid=0D +=0D + gEfiEventExitBootServicesGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf=0D +# MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Pr= otocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gE= fiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gE= fiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRunti= meArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtoc= olGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGu= id AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AN= D gEfiAcpiSdtProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) 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license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchPcieSmm.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PchPcieSmm driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchPcieSmm=0D + FILE_GUID =3D acaeaa7a-c039-4424-88da-f42212ea0e55=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InitializePchPcieSmm=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchPcieSmm.efi=0D + SMM_DEPEX|PchPcieSmm.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= C10=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xCC18=0D +=0D +=0D +[Protocols.X64]=0D + ## CONSUMES=0D + gEfiSmmIchnDispatchExProtocolGuid=0D +=0D + gDxePchPlatformPolicyProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchExProtocolGuid AND gEf= iPchInfoProtocolGuid AND gDxePchPlatformPolicyProtocolGuid) AND (gEfiPcdPro= tocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGui= d) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetrono= meArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTim= eClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchPro= tocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AN= D gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gE= fiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPolicyInitDxe.depe= x b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPolicyInitDxe.depex new file mode 100644 index 0000000..0dc7ce4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPolicyInitDxe.depex @@ -0,0 +1 @@ +=02=F6=F0=A3=13J&=F0>=F2=E0=DE=C5=124/4=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPolicyInitDxe.efi = b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchPolicyInitDxe.efi new file mode 100644 index 0000000000000000000000000000000000000000..116cde64b2536b7b7728963618d= 7ac58af5ffda0 GIT binary patch literal 23616 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf @@ -0,0 +1,137 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchReset.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for Reset module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchReset=0D + FILE_GUID =3D F5883FC5-F8EE-4e44-B386-6021FB320C9B=0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePchReset=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchReset.efi=0D + DXE_DEPEX|PchReset.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 820=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x6828=0D +=0D +=0D +[Protocols.X64]=0D + gEfiResetArchProtocolGuid=0D +=0D + gEfiPchExtendedResetProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiCapsuleVendorGuid=0D +=0D + ## CONSUMES ## Event=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D + ## CONSUMES ## Event=0D + gEfiEventExitBootServicesGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D +# Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf=0D +=0D +[Depex.X64]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.depex= b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.depex new file mode 100644 index 0000000..0dc7ce4 --- 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +#=0D +# This file contains an 'Intel Peripheral Driver' and is=0D +# licensed for Intel CPUs and chipsets under the terms of your=0D +# license agreement with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +## @file=0D +# Component description file for Pch Initialization driver=0D +#=0D +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
= =0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +##=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchS3SupportDxe=0D + FILE_GUID =3D 14537da0-222a-4bbe-9a5c-212a3cbca9ef=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PchS3SupportEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchS3SupportDxe.efi=0D + DXE_DEPEX|PchS3SupportDxe.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xD= A00=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0xDA08=0D +=0D +=0D +[Protocols.X64]=0D + # PROTOCOL ALWAYS_PRODUCED=0D + gEfiPchS3SupportProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadFileProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadFile2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleFileSystemProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiFileInfoGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +=0D +[Depex.X64]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 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+1,181 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSmiDispatcher.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the Pch SMI Dispatch Handlers module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSmiDispatcher=0D + FILE_GUID =3D 6BE18C9C-BF61-499e-88EC-5CD57430460C=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InitializePchSmmDispatcher=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchSmiDispatcher.efi=0D + SMM_DEPEX|PchSmiDispatcher.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 020=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB028=0D +=0D +=0D +[Protocols.X64]=0D + gEfiPciRootBridgeIoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D +=0D +=0D + gEfiSmmIchnDispatchExProtocolGuid=0D +=0D + gEfiSmmIchnDispatchProtocolGuid=0D +=0D + gEfiSmmSwDispatch2ProtocolGuid=0D +=0D + gEfiSmmPowerButtonDispatch2ProtocolGuid=0D +=0D + gEfiSmmSxDispatch2ProtocolGuid=0D +=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Prot= ocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfi= MetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfi= RealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntime= ArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocol= Guid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid= AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiRuntime.depex b= /Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiRuntime.depex new file mode 100644 index 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licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSpiRuntime.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SPI Runtime driver.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSpiRuntime=0D + FILE_GUID =3D C194C6EA-B68C-4981-B64B-9BD271474B20=0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallPchSpi=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchSpiRuntime.efi=0D + DXE_DEPEX|PchSpiRuntime.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= A20=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xBA28=0D +=0D +=0D +[Protocols.X64]=0D + gEfiSpiProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## CONSUMES ## Event=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## CONSUMES ## Event=0D + gEfiEventExitBootServicesGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/DxeRuntimePciL= ibPciExpress/DxeRuntimePciLibPciExpress.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D +=0D +[Depex.X64]=0D +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent=0D +#=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.depex b/Sil= icon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.depex new file mode 100644 index 0000000..6fa9e99 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.depex @@ -0,0 +1 @@ +=02=B7=BF=CC=F4=E0=F6=FDG=9D=D4=10=A8=F1P=C1=91=02=F6=F0=A3=13J&=F0>=F2=E0= =DE=C5=124/4=02t+p=C2=0C=801A=87F=8F=B5=B8=9C=E4=AC=03=03=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.efi b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.efi new file mode 100644 index 0000000000000000000000000000000000000000..7f25a851dc624793b8c9336c0f7= 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf new file mode 100644 index 0000000..2f06103 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf @@ -0,0 +1,251 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PchSpiSmm.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SPI SMM driver.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PchSpiSmm=0D + FILE_GUID =3D 27F4917B-A707-4aad-9676-26DF168CBF0D=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D InstallPchSpi=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PchSpiSmm.efi=0D + SMM_DEPEX|PchSpiSmm.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 610=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC618=0D +=0D +=0D +[Protocols.X64]=0D + gEfiSmmSpiProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.in= f=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf= =0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoc= olGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBas= e2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGu= id AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMo= notonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gE= fiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArc= hProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoc= olGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGu= id)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent=0D +#=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= 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0000000..2ad6449 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PciHostBridge.inf @@ -0,0 +1,254 @@ +#/*++=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# PciHostBridge.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PciHostBridge module=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PciHostBridge=0D + FILE_GUID =3D 9fd2360e-6b48-11d5-8e71-00902707b35e=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PciHostBridgeEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PciHostBridge.efi=0D + DXE_DEPEX|PciHostBridge.depex=0D +=0D +[PatchPcd.X64]=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB798=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 790=0D +=0D +=0D +[Protocols.X64]=0D + gEfiPciRootBridgeIoProtocolGuid=0D +=0D + gEfiPciHostBridgeResourceAllocationProtocolGuid=0D +=0D + gEfiMetronomeArchProtocolGuid=0D +=0D + gEfiCpuIo2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- /O1=3D/Od=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f 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with Intel or your vendor. This file may=0D +# be modified by the user, subject to additional terms of the=0D +# license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# PlatformCpuPolicy.inf=0D +#=0D +# Abstract:=0D +#=0D +# Platform CPU driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PlatformCpuPolicy=0D + FILE_GUID =3D cb933912-df8f-4305-b1f9-7b44fa11395c=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|PlatformCpuPolicy.efi=0D + DXE_DEPEX|PlatformCpuPolicy.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x7= D80=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x7D88=0D +=0D +=0D +[Protocols.X64]=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiPlatformCpuProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiStatusCodeRuntimeProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gEfiPlatformCpuInfoGuid=0D +=0D + gEfiSetupVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeSpecificDataGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED=0D + gEfiStatusCodeDataTypeDebugGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf= =0D +=0D +[Depex.X64]=0D +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid A= ND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArch= ProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid = AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolG= uid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiS= ecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWrite= ArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArch= ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## 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ziSB{!Bi%>42fNMg6Wu4fwH|j*c27=3D^-s9`>_XK)^Jw{JSPgzezPi;?APfJg0kM@wo G<-Y(^-ZfkR literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf new file mode 100644 index 0000000..ff15e86 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf @@ -0,0 +1,210 @@ +#/*++=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# SmmAccess.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SmmAccess module=0D +# {1323C7F8-DAD5-4126-A54B-7A05FBF4151}=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmAccess=0D + FILE_GUID =3D 326E9CC6-9839-4885-B2ED-275903B668E1=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmAccessDriverEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|SmmAccess.efi=0D + DXE_DEPEX|SmmAccess.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= DE0=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5DE8=0D +=0D +=0D +[Protocols.X64]=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +=0D +[Depex.X64]=0D +# (gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProto= colGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchP= rotocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid A= ND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVaria= bleWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogT= imerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf b/Sili= con/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf new file mode 100644 index 0000000..33f7a05 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf @@ -0,0 +1,259 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitDxe=0D + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|VlvInitDxe.efi=0D + DXE_DEPEX|VlvInitDxe.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 620=0D +=0D + ## CONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC628=0D +=0D +=0D +[Protocols.X64]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D +=0D + gIgdOpRegionProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiCpuIo2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gBmpImageGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf=0D +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf=0D +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid= )=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for=0D +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi= =0D +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy-=0D +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable=0D +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG=0D +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInitPeim.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the VLV Init PEIM.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitPeim=0D + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562=0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitPeiEntryPoint=0D +=0D +[Packages.IA32]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.IA32]=0D + PE32|VlvInitPeim.efi=0D + PEI_DEPEX|VlvInitPeim.depex=0D +=0D +[PatchPcd.IA32]=0D +=0D +[Protocols.IA32]=0D +=0D +[Ppis.IA32]=0D + gVlvPolicyPpiGuid=0D +=0D + gVlvPeiInitPpiGuid=0D +=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D +=0D +=0D +[Guids.IA32]=0D + gEfiSetupVariableGuid=0D +=0D +=0D +[PcdEx.IA32]=0D +=0D +[LibraryClasses.IA32]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +=0D +[Depex.IA32]=0D +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid=0D +=0D +=0D +=0D +[BuildOptions.IA32]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo 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$(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D GraphicDxeInitSmm=0D + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + PI_SPECIFICATION_VERSION =3D 0x0001000A=0D + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|GraphicDxeInitSmm.efi=0D + SMM_DEPEX|GraphicDxeInitSmm.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 000=0D +=0D +=0D +[Protocols.X64]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + gEdkiiSmmReadyToBootProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D + ## CONSUMES=0D + ## CONSUMES=0D + gEfiSmmEndOfDxeProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable=0D + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +# MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D +# MdePkg/Library/SmmIoLib/SmmIoLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for=0D +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd=0D +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data /ALIGN:4096=0D +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SataController.inf = b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SataController.inf new file mode 100644 index 0000000..5779ded --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SataController.inf @@ -0,0 +1,195 @@ +#=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# SataController.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for PCH SATA controller Driver module.=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SataController=0D + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2=0D + MODULE_TYPE =3D UEFI_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializeSataControllerDriver=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|SataController.efi=0D +=0D +[PatchPcd.X64]=0D +=0D +[Protocols.X64]=0D + gEfiIdeControllerInitProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gSataControllerDriverGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +=0D +[Depex.X64]=0D +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for=0D +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd=0D +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTI= ON) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_S= UPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_S= ECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64=0D diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.depex b/S= ilicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.depex new file mode 100644 index 0000000000000000000000000000000000000000..b1a5ceab3b2eb73466f120b95a1= 915810dd0401f GIT binary patch literal 36 scmZSDU00wl<#k1HmIcEEb^C+9Oy52%7WPv6VE5_4y`w@V`Xp9~2N1?0i9=3DXO{%NW85cPV6|?s9BGWalBf zQcn2(&a0^m+`K+Mh^8*krDYrenw@B_kg5BBwN-Ei)%>5h1oPN91MQP7`6xFM_e-HFO}n3`Sc38(d0RW=3Di+egK(p2K*Wc7J?a4Ho;$#J zLKZHrnEhXZA&t`eb*Y&u=3Du$0JH6$;2hO~sSUcGT+DfS0-Xat|Jl@!4JXpT)H=3DZX#Z zKP}4lWjNhqL%8mV6wB*cXc8=3Dwc=3DiP-l|CtR3zbOK%4yqvOc|86X#eGk(`7w4mWn3A73YhY=3DaRB34_PlYixbP+`v|%k3fM~tVox+B zOvwEpfw%_oJJajnW64P_Zi-oW?CmgeNezH9uGZipftZ*-dfl=3D>zZ=3DB)(zt~h+V0F8 zgnt3)F%w26Gab0edGy2t{*>RK!9~--mJw5Zn2TL~Tm*L`mJ$Un8rvzVG-Rr|ve&29 zf<4L&DaA}T6n_H4lSm1k!@ct#!$c4{DqAUqh4&6kO$SnE55MsKjbUpCzZQS?>toaP zuRp{_@7tMcQNw-X>xQ=3D`UwZWD2ifC4o~q>DZ2J+QeICTA(erPTOSM|ZXDJNGz-{*&?-hgYnM literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf b/Sil= icon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf new file mode 100644 index 0000000..234cd77 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf @@ -0,0 +1,198 @@ +#/*++=0D +# This file contains a 'Sample Driver' and is licensed as such=0D +# under the terms of your license agreement with Intel or your=0D +# vendor. This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#--*/=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +#=0D +# Module Name:=0D +#=0D +# SmmAccess.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for the SmmAccess module=0D +# {1323C7F8-DAD5-4126-A54B-7A05FBF4151}=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmAccess=0D + FILE_GUID =3D 326E9CC6-9839-4885-B2ED-275903B668E1=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D SmmAccessDriverEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|SmmAccess.efi=0D + DXE_DEPEX|SmmAccess.depex=0D +=0D +[PatchPcd.X64]=0D +=0D +[Protocols.X64]=0D + gEfiSmmAccess2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiHobListGuid=0D +=0D +=0D +[PcdEx.X64]=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +=0D +[Depex.X64]=0D +# (gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProto= colGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchP= rotocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid A= ND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVaria= bleWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogT= imerArchProtocolGuid)=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for=0D +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd=0D +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D 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This file may be modified by the user, subject to=0D +# the additional terms of the license agreement=0D +#=0D +#/*++=0D +#=0D +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved=0D +# This software and associated documentation (if any) is furnished=0D +# under a license and may only be used or copied in accordance=0D +# with the terms of the license. Except as permitted by such=0D +# license, no part of this software or documentation may be=0D +# reproduced, stored in a retrieval system, or transmitted in any=0D +# form or by any means without the express written consent of=0D +# Intel Corporation.=0D +#=0D +# Module Name:=0D +#=0D +# VlvInit.inf=0D +#=0D +# Abstract:=0D +#=0D +# Component description file for SystemAgent Initialization driver=0D +#=0D +#--*/=0D +=0D +# DO NOT EDIT=0D +# FILE auto-generated=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D VlvInitDxe=0D + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D=0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D VlvInitEntryPoint=0D +=0D +[Packages.X64]=0D + MdePkg/MdePkg.dec=0D + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Vlv2TbltDevicePkg/PlatformPkg.dec=0D +=0D +[Binaries.X64]=0D + PE32|VlvInitDxe.efi=0D + DXE_DEPEX|VlvInitDxe.depex=0D +=0D +[PatchPcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 910=0D +=0D +=0D +[Protocols.X64]=0D + gDxeVlvPlatformPolicyGuid=0D +=0D + ## NOTIFY=0D + gEfiDxeSmmReadyToLockProtocolGuid=0D +=0D +=0D + gIgdOpRegionProtocolGuid=0D +=0D + gEfiGlobalNvsAreaProtocolGuid=0D +=0D + gEfiPciIoProtocolGuid=0D +=0D + gEfiFirmwareVolume2ProtocolGuid=0D +=0D + gEfiCpuIo2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gPcdProtocolGuid=0D +=0D + ## CONSUMES=0D + gEfiPcdProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGetPcdInfoProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiDevicePathProtocolGuid=0D +=0D + ## UNDEFINED=0D + gEfiDebugPortProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmCommunicationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES=0D + gEfiDriverBindingProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSimpleTextOutProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiGraphicsOutputProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiHiiFontProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled=0D + gEfiUgaDrawProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentNameProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiComponentName2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfigurationProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverConfiguration2ProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnosticsProtocolGuid=0D +=0D + ## SOMETIMES_PRODUCES # User chooses to produce it=0D + gEfiDriverDiagnostics2ProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiLoadedImageProtocolGuid=0D +=0D + ## SOMETIMES_CONSUMES=0D + gEfiSmmBase2ProtocolGuid=0D +=0D + ## NOTIFY=0D + gEfiSmmReadyToLockProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmExitBootServicesProtocolGuid=0D +=0D + ## NOTIFY=0D + gEdkiiSmmLegacyBootProtocolGuid=0D +=0D +=0D +[Ppis.X64]=0D +=0D +[Guids.X64]=0D + gBmpImageGuid=0D +=0D + ## CONSUMES ## SystemTable=0D + gEfiDxeServicesTableGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVTUTF8Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100Guid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVT100PlusGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPcAnsiGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiUartDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiSasDevicePathGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualDiskGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID=0D + gEfiPersistentVirtualCdGuid=0D +=0D + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication=0D + gEfiSmmLockBoxCommunicationGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventReadyToBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Event=0D + gEfiEventLegacyBootGuid=0D +=0D + ## SOMETIMES_CONSUMES ## Variable=0D + gEfiGlobalVariableGuid=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid=0D +=0D +=0D +[PcdEx.X64]=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr=0D +=0D + ## CONSUMES=0D + ## SOMETIMES_PRODUCES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr=0D +=0D +=0D +[LibraryClasses.X64]=0D +## @LIB_INSTANCES=0D +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf=0D +# MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +# MdePkg/Library/BaseLib/BaseLib.inf=0D +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf=0D +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf=0D +# MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf=0D +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf=0D +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf=0D +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf=0D +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf= =0D +# MdePkg/Library/UefiLib/UefiLib.inf=0D +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf=0D +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf=0D +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf=0D +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf=0D +=0D +[Depex.X64]=0D +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid= )=0D +=0D +=0D +=0D +[BuildOptions.X64]=0D +## @AsBuilt=0D +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for=0D +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE=0D +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n=0D +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG=0D +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd=0D +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D =0D +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin=0D +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable=0D +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e=0D +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data=0D +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTI= ON) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_S= UPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_S= ECURE_BOOT_BUILD_OPTIONS)=0D +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for=0D +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS =3D /nologo=0D +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny=0D +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64=0D --=20 2.21.0.windows.1