From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Tue, 02 Jul 2019 23:54:45 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Jul 2019 23:54:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,446,1557212400"; d="scan'208";a="247523161" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga001.jf.intel.com with ESMTP; 02 Jul 2019 23:54:44 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Subject: [PATCH v2 0/3] Enable 5 level paging in SMM mode Date: Wed, 3 Jul 2019 14:54:13 +0800 Message-Id: <20190703065416.116816-1-ray.ni@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit v2: Added Laszlo's Regression-tested-by. Updated patch #3 to use PatchInstructionX86 to avoid using DBs in NASM. Ray Ni (3): UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports MdePkg/Include/Library/BaseLib.h | 3 +- .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 20 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 300 ++++++----- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 485 ++++++++++++------ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 12 + .../PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 72 ++- 6 files changed, 577 insertions(+), 315 deletions(-) -- 2.21.0.windows.1