From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmx.net header.s=badeba3b8450 header.b=WOWnJo8f; spf=pass (domain: gmx.fr, ip: 212.227.17.21, mailfrom: coeur@gmx.fr) Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by groups.io with SMTP; Fri, 05 Jul 2019 06:32:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1562333538; bh=TaD2t4QCE4g3p0mQqrxKphJvMpo4CzFI2kq+fLMJpuQ=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date; b=WOWnJo8fPgdHJuzYVjESofvYDgaiakuaiM0xoona62RsMNfMR+Bp4TxNh7RMzp1jH /cEt7DFz+oDQlpc3HY0sVOeXQpwTfh44hWFkGQYnu6p7UhEhRVhUjBuUeSljEoq02H AMuAuQzW5hDPRCZVf+HDRHH5triIJovye1hHhC1g= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([45.32.43.45]) by mail.gmx.com (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MJVHU-1hyjJP3ALY-00JuxF; Fri, 05 Jul 2019 15:32:18 +0200 From: =?UTF-8?B?Q8WTdXI=?= To: devel@edk2.groups.io, ray.ni@intel.com Cc: =?UTF-8?q?Antoine=20C=C5=93ur?= Subject: [PATCH] PcAtChipsetPkg: Fix various typos Date: Fri, 5 Jul 2019 21:31:39 +0800 Message-Id: <20190705133139.65645-1-coeur@gmx.fr> X-Mailer: git-send-email 2.20.1 (Apple Git-117) MIME-Version: 1.0 X-Provags-ID: V03:K1:uYu7gVQiV1rDlNN7RnqgKvR3V/MaOJ/9GPYUjHN+JKUpX6YdSkV Da1bMHHLmBxNGOgMhhlx4+Zanx9PKntwLGMrbgAh8oD2s88n55TrZXtZFWttCAyJINXj26h 8LTOIxvBwD7IM/BrJvFsAtEv0HGiTtWp8Y5Bgm2pBm08WPWHMEFc8IoG93xnZLGhcY7lzeY WlShRhdA7py37tED3RM7w== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:7ZqWAdtDeJI=:Rhjnq6kCgCNNezcLqyjWzC 042+EBITKvBE9I8PdDrzbLV0LvJtKE8jnaAlcKUPGtwtai9e0zEdskRjhRVn1duqfdQpj464O SlPQitHrGQJNoA5nD8uWLCAn2FxMF1viAxrtCIrJduKbynMIyC014gHdQdNzzTz9Fu92A+Kl9 JUxHgd93cevZwBb8AZCkMKQBYqJEgpMbIw2FhMoSJuVOquRYfxKCnwJo0oiLQn2XwA/ARGcPA OfKzPiPIAOZQbRgK8N/tHqNjwaoEEYQZMIO6vJVkzliSkbOFlud8R4f0U9579z+kCU0kDcE2u T6ghb7oRWut8k6soGrO/lGb+/5nA8266x+zHmG/Y+2aGKhc9BIVm4iyOEw2LukxPFh0eOdH37 gB/Dz1SASKCSFD2/l0l9Z44tP1Le0uF6NYdmLQB5JflSVXluKnTNOvLrPR0JrcX1TMG7Or7a3 9BqS1UDsvIANuGWTqvjvXocJw33CIdy79mMQ3m9bYkHhq9EovDH6GRV1VwAO5QhNXFgaFKY0T cMW4A9hKZ0VpQYUpbEN/1GpHkzl6nDaZMwwc6bfwrqtZrPWm9Y8L8aSq0BLjYF8RZBY5wNPdx dCL682H4I7lU5Ret7t3id2oLpn+fwuq+jPhMC3eIgyfr/ZHjP41pcQFbg5qzb0lrdKfvD4GyK fvf5LweMm7ksKafE4irMOIuE1FsTc2yZ6tPgY9bxOHlgh72O5RFgqjDzih48gn+pnTG5c8WzH elHln1+WmGRcwCHkx9WITC3eq1qh+EVR2yHaRCWn9wX5i9MeNSuZ/aeqjPLZ7MeLUC9nniulH ZoeVTM1hrUdZnoZuKb/DEqmbqiNfhsELzlc6ffZIy5GQ8iLLu3tGcV3DwWtNkCbgStyXIsOkJ s74aNDfaG+zi3axa9Os5Ii9uUXRL1O7zAqCNo+fSijIg2cIESp81Al4yWFYQ5B11PC9d/bKI1 vozJU0RrSVyLWcOPqG6nfd2MMkJhSWQAugP8Aa5SaFz8LcAlN5ZlNpwV7V66B0T3F0YV5K+fe n/YRpsHl3WBQo+p6pHEmRx4/WwWh57bIvIYKjJH+A093ZYtPbVyjTf9jSr5O5N7b9Q== Content-Transfer-Encoding: quoted-printable Fix various typos in PcAtChipsetPkg. =2D-- PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c | 4 ++-- PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf | 2 +- PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni | 2 +- PcAtChipsetPkg/Include/Library/IoApicLib.h | 2 +- PcAtChipsetPkg/Library/AcpiTimerLib/AcpiTimerLib.c | 2 +- PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c | 2 +- PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c | 14 +++++++------- PcAtChipsetPkg/PcAtChipsetPkg.dec | 2 +- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c b/PcAtChipsetPkg/Hpet= TimerDxe/HpetTimer.c index ded3b53619..1a1ed29e9c 100644 =2D-- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c @@ -1,5 +1,5 @@ /** @file - Timer Architectural Protocol module using High Precesion Event Timer (H= PET) + Timer Architectural Protocol module using High Precision Event Timer (H= PET) Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -246,7 +246,7 @@ HpetRead ( /** Write a 64-bit HPET register. - @param Offset Specifies the ofsfert of the HPET register to write. + @param Offset Specifies the offset of the HPET register to write. @param Value Specifies the value to write to the HPET register speci= fied by Offset. @return The 64-bit value written to HPET register specified by Offset. diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf b/PcAtChipsetPkg= /HpetTimerDxe/HpetTimerDxe.inf index ba2e075118..125eea0aab 100644 =2D-- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf @@ -1,5 +1,5 @@ ## @file -# Timer Architectural Protocol module using High Precesion Event Timer (H= PET). +# Timer Architectural Protocol module using High Precision Event Timer (H= PET). # # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni b/PcAtChipsetPkg= /HpetTimerDxe/HpetTimerDxe.uni index e2320653b6..7d1797b1df 100644 =2D-- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni @@ -1,5 +1,5 @@ // /** @file -// Timer Architectural Protocol module using High Precesion Event Timer (= HPET). +// Timer Architectural Protocol module using High Precision Event Timer (= HPET). // // Timer Architectural Protocol module using High Precision Event Timer (= HPET). // diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/I= nclude/Library/IoApicLib.h index 200ef731fb..4ee092c0f2 100644 =2D-- a/PcAtChipsetPkg/Include/Library/IoApicLib.h +++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h @@ -63,7 +63,7 @@ IoApicEnableInterrupt ( Configures an I/O APIC interrupt. Configure an I/O APIC Redirection Table Entry to deliver an interrupt i= n physical - mode to the Local APIC of the currntly executing CPU. The default stat= e of the + mode to the Local APIC of the currently executing CPU. The default sta= te of the entry is for the interrupt to be disabled (masked). IoApicEnableInterr= upts() must be used to enable(unmask) the I/O APIC Interrupt. diff --git a/PcAtChipsetPkg/Library/AcpiTimerLib/AcpiTimerLib.c b/PcAtChip= setPkg/Library/AcpiTimerLib/AcpiTimerLib.c index 7dc11014a5..0a49093dbf 100644 =2D-- a/PcAtChipsetPkg/Library/AcpiTimerLib/AcpiTimerLib.c +++ b/PcAtChipsetPkg/Library/AcpiTimerLib/AcpiTimerLib.c @@ -59,7 +59,7 @@ AcpiTimerLibConstructor ( // // If the register offset to the BAR for the ACPI I/O Port Base Address= is 0x0000, then - // no PCI register programming is required to enable access to the the = ACPI registers + // no PCI register programming is required to enable access to the ACPI= registers // specified by PcdAcpiIoPortBaseAddress // if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) =3D=3D 0x0000) { diff --git a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c b/PcAtChipse= tPkg/Library/BaseIoApicLib/IoApicLib.c index 7a3c9aca8d..9e4a58049e 100644 =2D-- a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c +++ b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c @@ -94,7 +94,7 @@ IoApicEnableInterrupt ( Configures an I/O APIC interrupt. Configure an I/O APIC Redirection Table Entry to deliver an interrupt i= n physical - mode to the Local APIC of the currntly executing CPU. The default stat= e of the + mode to the Local APIC of the currently executing CPU. The default sta= te of the entry is for the interrupt to be disabled (masked). IoApicEnableInterr= upts() must be used to enable(unmask) the I/O APIC Interrupt. diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChip= setPkg/Library/SerialIoLib/SerialPortLib.c index 93affe151e..aa5657a7fd 100644 =2D-- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c +++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c @@ -58,7 +58,7 @@ UINT8 gBreakSet =3D 0; If the serial device could not be initialized, then return RETURN_DEVIC= E_ERROR. @retval RETURN_SUCCESS The serial device was initialized. - @retval RETURN_DEVICE_ERROR The serail device could not be initialize= d. + @retval RETURN_DEVICE_ERROR The serial device could not be initialize= d. **/ RETURN_STATUS @@ -139,7 +139,7 @@ SerialPortWrite ( while ((NumberOfBytes--) !=3D 0) { // - // Wait for the serail port to be ready. + // Wait for the serial port to be ready. // do { Data =3D IoRead8 ((UINT16) gUartBase + LSR_OFFSET); @@ -180,7 +180,7 @@ SerialPortRead ( while ((NumberOfBytes--) !=3D 0) { // - // Wait for the serail port to be ready. + // Wait for the serial port to be ready. // do { Data =3D IoRead8 ((UINT16) gUartBase + LSR_OFFSET); @@ -195,7 +195,7 @@ SerialPortRead ( /** Polls a serial device to see if there is any data waiting to be read. - Polls aserial device to see if there is any data waiting to be read. + Polls a serial device to see if there is any data waiting to be read. If there is data waiting to be read from the serial device, then TRUE i= s returned. If there is no data waiting to be read from the serial device, then FAL= SE is returned. @@ -339,13 +339,13 @@ SerialPortGetControl ( } /** - Sets the baud rate, receive FIFO depth, transmit/receice time out, pari= ty, + Sets the baud rate, receive FIFO depth, transmit/receive time out, pari= ty, data bits, and stop bits on a serial device. @param BaudRate The requested baud rate. A BaudRate value of = 0 will use the device's default interface speed. On output, the value actually set. - @param ReveiveFifoDepth The requested depth of the FIFO on the receiv= e side of the + @param ReceiveFifoDepth The requested depth of the FIFO on the receiv= e side of the serial interface. A ReceiveFifoDepth value of= 0 will use the device's default FIFO depth. On output, the value actually set. @@ -358,7 +358,7 @@ SerialPortGetControl ( DefaultParity will use the device's default p= arity value. On output, the value actually set. @param DataBits The number of data bits to use on the serial = device. A DataBits - vaule of 0 will use the device's default data= bit setting. + value of 0 will use the device's default data= bit setting. On output, the value actually set. @param StopBits The number of stop bits to use on this serial= device. A StopBits value of DefaultStopBits will use the device'= s default number of diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipse= tPkg.dec index d99d91496b..130c8e3723 100644 =2D-- a/PcAtChipsetPkg/PcAtChipsetPkg.dec +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec @@ -50,7 +50,7 @@ # @Prompt HPET local APIC vector. gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x00000= 00A - ## This PCD specifies the defaut period of the HPET Timer in 100 ns uni= ts. + ## This PCD specifies the default period of the HPET Timer in 100 ns un= its. # The default value of 100000 100 ns units is the same as 10 ms. # @Prompt Default period of HPET timer. gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0= x0000000B diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChip= setPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index 038482d04d..3c78c37d54 100644 =2D-- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -110,7 +110,7 @@ typedef struct { UINT8 Uf : 1; // Update End Interrupt Flag UINT8 Af : 1; // Alarm Interrupt Flag UINT8 Pf : 1; // Periodic Interrupt Flag - UINT8 Irqf : 1; // Iterrupt Request Flag =3D PF & PIE | AF & AIE | = UF & UIE + UINT8 Irqf : 1; // Interrupt Request Flag =3D PF & PIE | AF & AIE |= UF & UIE } RTC_REGISTER_C_BITS; typedef union { =2D- 2.20.1 (Apple Git-117)