From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@amazon.com header.s=amazon201209 header.b=uHSDBI48; spf=pass (domain: amazon.com, ip: 207.171.184.29, mailfrom: prvs=087a6d762=graf@amazon.com) Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) by groups.io with SMTP; Wed, 10 Jul 2019 07:53:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1562770408; x=1594306408; h=from:to:cc:subject:date:message-id:mime-version; bh=j54gSHeCGc6jHwnabN55w1U0SVa05KeSRtdzMmIbrvw=; b=uHSDBI48jpYTkWyhT71Ak9Uut0J6RIAFV3TvgJtKqBEU3gOpTxgOzi14 OFyF18h4UcvZz4BXwBx2qyeamlomjZ/BpFtsKExhqLnk8UlSOQWcMbv9z xwEblC8ynyZVPYc0GGfGYfzWIEI6NJYyicmlZZpDxkCgYp6L8fxRC9bUq 0=; X-IronPort-AV: E=Sophos;i="5.62,474,1554768000"; d="scan'208";a="684741737" Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1d-2c665b5d.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP; 10 Jul 2019 14:53:22 +0000 Received: from EX13MTAUWC001.ant.amazon.com (iad55-ws-svc-p15-lb9-vlan3.iad.amazon.com [10.40.159.166]) by email-inbound-relay-1d-2c665b5d.us-east-1.amazon.com (Postfix) with ESMTPS id 73BEEA1C62; Wed, 10 Jul 2019 14:53:20 +0000 (UTC) Received: from EX13D20UWC001.ant.amazon.com (10.43.162.244) by EX13MTAUWC001.ant.amazon.com (10.43.162.135) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 10 Jul 2019 14:53:19 +0000 Received: from u79c5a0a55de558.ant.amazon.com (10.43.162.106) by EX13D20UWC001.ant.amazon.com (10.43.162.244) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 10 Jul 2019 14:53:18 +0000 From: "Alexander Graf" To: CC: Leif Lindholm Subject: [PATCH] PL031: Actually disable interrupts Date: Wed, 10 Jul 2019 16:53:11 +0200 Message-ID: <20190710145311.12184-1-graf@amazon.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.43.162.106] X-ClientProxiedBy: EX13D01UWA001.ant.amazon.com (10.43.160.60) To EX13D20UWC001.ant.amazon.com (10.43.162.244) Precedence: Bulk Content-Type: text/plain The PL031 interrupt mask register (IMSC) is not very clearly documented in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether interrupts are enabled, not disabled. So before this commit, we were actually *enabling* interrupts for the RTC. This patch changes the logic to instead disable interrupts when they are not disabled already. Signed-off-by: Alexander Graf --- .../Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index b630a5cfbf..75c95985d4 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -80,8 +80,8 @@ InitializePL031 ( } // Ensure interrupts are masked. We do not want RTC interrupts in UEFI - if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) { - MmioOr32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK); + if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != 0) { + MmioWrite32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, 0); } // Clear any existing interrupts -- 2.17.1