From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=H5Oz7E7q; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Wed, 10 Jul 2019 10:13:35 -0700 Received: by mail-wr1-f67.google.com with SMTP id p13so3273349wru.10 for ; Wed, 10 Jul 2019 10:13:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=I9aYExW+re37YTOeW7vOQXd5ED02eSizsLOdCJfK8PU=; b=H5Oz7E7qtpFOJVgAiaDW6V26pyzg/eemLf6yZP8epwUwy6uPBdYcttsg5vYEbgfPfR WF3L04A2Uy0KewAgnyC/ZpY7foUii+ayn5UWjLuTeLbQd1WE38dnldlBtD7qQ9eGCm0I PrcJAttZP8E/ygnnbJ/R78k32K+FSvpsGJE0jXAWDxQnmgEQtCsAe2wf3zCQkR/g6Scr DQPdhmA3BSmj7A//fwYAafHS3ZTI3UeF1/MNsQziLjrFFF98AO4tlnmH6ZhSPI2ZvXBM tBlZ1dXSL6IsVKP1XcBGK9y9ZqqHS9Bt63TMdIVsydoner/S0PlZGQv5yeIG7yFOKaby 0uJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=I9aYExW+re37YTOeW7vOQXd5ED02eSizsLOdCJfK8PU=; b=kfTQZMl8/15ZBJOVqQQdCmors/oqhBbo81tcjYqHobfr7V1Q4Ni/wIVFV5yJmI0O66 33aC73KSjlZcPErPLAQdiMe0nxSsrGEImmcRdnhPQK0OtX5jvlodjMixVawm+gwtf1CF HxCkXaRdsRrfrvWyy/zklQsTZIW9TlHBjHkT0kGlbb2Di3RlPHv+SEP0VHyH2AZUDfjc 9lgJlr1+LBlU2dv3BhqmlSHyBXZk7wbE8XpVDNu34BggV2S4XCp59UUVQ6GOAuGrKwp4 L4pBYfA/AKKuc+4E1p1xvGuKAZO9hgUUC0nIZRMZHnrCGnYxA6PCGh2mE79q/FHM4PE4 MkJw== X-Gm-Message-State: APjAAAXwiv199yxLodCz6hIQhgOiNYA4ErwPlo0PuTfZVvueS2M7FjBv gZtH8N/KsAcg/mST5FT9BLfheSbLUro= X-Google-Smtp-Source: APXvYqyz0HF55Wr+Emz0uM7xwLcbxtyBDXO6VVI7ASasdBJcF5ZpjFjpa/tw3WmI+53FYzcFhUtiSw== X-Received: by 2002:a5d:5647:: with SMTP id j7mr20805554wrw.191.1562778813763; Wed, 10 Jul 2019 10:13:33 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m7sm2847472wrx.65.2019.07.10.10.13.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Jul 2019 10:13:33 -0700 (PDT) Date: Wed, 10 Jul 2019 18:13:31 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, graf@amazon.com Subject: Re: [edk2-devel] [PATCH] PL031: Actually disable interrupts Message-ID: <20190710171331.aj2smigjmtok4buz@bivouac.eciton.net> References: <20190710145311.12184-1-graf@amazon.com> MIME-Version: 1.0 In-Reply-To: <20190710145311.12184-1-graf@amazon.com> User-Agent: NeoMutt/20170113 (1.7.2) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jul 10, 2019 at 04:53:11PM +0200, Alexander Graf via Groups.Io wrote: > The PL031 interrupt mask register (IMSC) is not very clearly documented > in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether > interrupts are enabled, not disabled. 3.3.5. Interrupt Mask Set or Clear register, RTCIMSC ... Writing 1 sets the mask. ... 3.6. Interrupts ... This interrupt is enabled or disabled by changing the mask bit in RTCIMSC. To enable the interrupt, set bit[0] HIGH. ... *boggle* > So before this commit, we were actually *enabling* interrupts for the RTC. > > This patch changes the logic to instead disable interrupts when they > are not disabled already. Thanks for finding/fixing this. > Signed-off-by: Alexander Graf Reviewed-by: Leif Lindholm I took the liberty to change the subject line to "ArmPlatformPkg: Actually disable PL031 interrupts" (We tend to start with the top-level directory.) Pushed as 8df52631e53c. / Leif > --- > .../Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c > index b630a5cfbf..75c95985d4 100644 > --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c > +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c > @@ -80,8 +80,8 @@ InitializePL031 ( > } > > // Ensure interrupts are masked. We do not want RTC interrupts in UEFI > - if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) { > - MmioOr32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK); > + if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != 0) { > + MmioWrite32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, 0); > } > > // Clear any existing interrupts > -- > 2.17.1 > > > >