From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmx.net header.s=badeba3b8450 header.b=OtSgNllY; spf=pass (domain: gmx.fr, ip: 212.227.15.15, mailfrom: coeur@gmx.fr) Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by groups.io with SMTP; Thu, 11 Jul 2019 02:37:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1562837855; bh=yNxCP+927I0eZWlGVpwuSHi2d5inUBkr+uaCuJPtROw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=OtSgNllYgGDRAPyw8yrkw8Obbd7jxfswTAupETAYxKja91RYjfncPZ3viLz7O77Z9 0RqNq6HZ0CzFWTfakZcP9lJUHBGXpq5VFEB2jOYiESHOfw63ttFORNIcDhNn5atC56 aJGNenJ9amwgTe2z2ac0MhrHMO2SVcusBGYYIP6A= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([128.1.125.180]) by mail.gmx.com (mrgmx002 [212.227.17.190]) with ESMTPSA (Nemesis) id 0MbgWb-1i1nqa32M1-00J22Q; Thu, 11 Jul 2019 11:37:35 +0200 From: =?UTF-8?B?Q8WTdXI=?= To: devel@edk2.groups.io Cc: =?UTF-8?q?Antoine=20C=C5=93ur?= , Star Zeng , Chasel Chiu Subject: [PATCH] Revert "FmpDevicePkg: Fix various typos" Date: Thu, 11 Jul 2019 17:36:59 +0800 Message-Id: <20190711093659.45166-1-coeur@gmx.fr> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4A6537@SHSMSX104.ccr.corp.intel.com> References: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4A6537@SHSMSX104.ccr.corp.intel.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:QwYNG7zjm/MWC9vvOje/dfz7yksD2Sdc3Nau2tfMe2zx2OcB1ma 7tq+0qShvpFKcaSs4BXzSKO5OIaKVCY1pAosEVxF3oAtY5QsMb05pNhaTVijKX0YV8Ov3RC nxohM0aw3wV3q2P9FQtzRM9JSyC8yBDxG07FakJDsDHRwBuL2PuoGzFEeQJ4pKeMz1CK6DS +TZY0zoEKBOhvGTgHZVdg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:vcwBM1kYEEs=:b9R+cxo3ukiE2xIrf8NQuE abdH6yuDcHei3r4PaBHcVTFDUtbFrukfAMU9hZBFiAUEqWz2FkY/BeA3bJ/xCFMJDcNILbfSD X1vg1F1JNK8PXdisrmI3KfA71gbbgE1o0dzIGR0+blJqLx5csQKM3uS8gGOqDbxezvsHiDYeS +NxUnQzGj8K7faQRSxkLyepSJr545/oj3tnVKlMGyTzCTh4E/s9JG4ORcgdiv9bV8217I1orx uPmJoOp4/WqcQ5orOniC8j216D0ydiMHLEez0pCqYMOrXE6j5vaUClpjCCk7jfdUuq5y8VU18 N8L1Vz3hBkQmkdIuftFPwAQ1qNYe031uagQH2NoHe81YEE9VBh0ip1tGDahslJg21zTAw6gyI qZGCdJGZM6htQ4+xY7ImDJ6La65EUUHT2j4YbhsocK7PgLCbqV1D5+6CYgW+o38C+cNH86Du8 3yVgfkk2bQV2RMK4al1XvzeM+0yKy/GBVAm3zst0V8HpkvIXvUo3BmR0tLEi6Ii/T+nz4AzUR qRSF8c/mCKO0G+y1NaoyeJ8uaI2xRXmXh6NtS6/PoikpFsl1C4XIG36zTOQeYbTfbyzteVGMx 6dLTMsVQQ1XEDU3tXyKikQj645yvPhVl+XE3EHsNJdEMw+iTNfzvrDR+NBfjWkvhXmzCR7J0d ndfUU16taKzy6OU4C9URUN4yFljr9ARJhWSQrY0CYZ2j+/sI0dT56TC0rw1iV5qxc7YlR8vpW ncXEtdsfUvbDWLgPOo6iHpQWSanldbpEPrJgOA9VhgDF/wqge3LSrQFY0YrhErdZTktNeaMdn BV9UHGhKsI/P43JQQiMIXDJJ4+KyKLktUKx3Mf/W2w7Z0m6P6FFixFIzIZq6aOyCkwW4yAPvK Jp+Wj5G/Pj6AwbPKPevOZ5tnNie8pjKxhv19gub1DvLVe35RLV2hecI0xZL1+oOV3Zh7uukVA mw3TMA8JmCESVJ5LNSzWcZ68OFcUPgh4pXgZ8uzPSMD0BHfh+9hWIF1mq2eTEQi+tHYEJLv8z ZaaqpDLrWWwn5dSqzqLt1FlXBMLfp/HHkYPe8o6xbPzjXkb0n11J9NqiqJzBGSTbbQ== Content-Transfer-Encoding: quoted-printable This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. Commit message was incorrect. Signed-off-by: Coeur =2D-- .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- .../FspSecCore/Ia32/InitializeFpu.nasm | 4 +-- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 +-- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- .../Include/Library/FspSecPlatformLib.h | 4 +-- IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++---- .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +++++++++---------- .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- .../PlatformSecLibNull.c | 4 +-- IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- IntelFsp2Pkg/Tools/PatchFv.py | 2 +- .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- .../Tools/UserManuals/PatchFvUserManual.md | 2 +- 18 files changed, 52 insertions(+), 52 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg= /FspSecCore/Ia32/FspApiEntryM.nasm index e7261b41cd..f14c18c7b9 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ; ; Pass BFV into the PEI Core - ; It uses relative address to calculate the actual boot FV base + ; It uses relative address to calucate the actual boot FV base ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase a= nd - ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, ; they are different. The code below can handle both cases. ; call ASM_PFX(AsmGetFspBaseAddress) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/InitializeFpu.nasm index ebc91c41e4..e1886ea11b 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw [ASM_PFX(mFpuControlWord)] ; - ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFs= p2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..b257deb76c 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord] ; - ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to = test + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to= test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSec= Core/Ia32/Stack.nasm index 5a7e27c240..d72212ed45 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to perm= anent memory ; - ; Fixup the ebp point to permanent memory + ; Fixup the ebp point to permenent memory ; mov eax, ebp sub eax, ebx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Se= cFsp.c index 446d1730e9..6497c88ebe 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -169,7 +169,7 @@ FspGlobalDataInit ( SerialPortInitialize (); // - // Ensure the global data pointer is valid + // Ensure the golbal data pointer is valid // ASSERT (GetFspGlobalDataPointer () =3D=3D PeiFspData); diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/S= ecMain.c index a63d1336e4..cd3ab46ce2 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/SecMain.c +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c @@ -110,7 +110,7 @@ SecStartup ( // |-------------------|----> // | | // | | - // | Heap | PeiTemporaryRamSize + // | Heap | PeiTemporayRamSize // | | // | | // |-------------------|----> TempRamBase diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2P= kg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 index c519874809..f25de0206a 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 @@ -2,7 +2,7 @@ ; Reset Vector Data structure ; This structure is located at 0xFFFFFFC0 ; -; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2014, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;; @@ -61,7 +61,7 @@ ApStartup: ; ; Jmp Rel16 instruction ; Use machine code directly in case of the assembler optimization - ; SEC entry point relative address will be fixed up by some build too= l. + ; SEC entry point relatvie address will be fixed up by some build too= l. ; ; Typically, SEC entry point is the function _ModuleEntryPoint() defi= ned in ; SecEntry.asm diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/F= spEas/FspApi.h index dcf489dbe6..1d38e639e6 100644 =2D-- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -2,7 +2,7 @@ Intel FSP API definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -211,12 +211,12 @@ EFI_STATUS each FSP release. After FspMemInit completes its execution, it passes the pointer to the = HobList and returns to the boot loader from where it was called. BootLoader is resp= onsible to - migrate its stack and data to Memory. + migrate it's stack and data to Memory. FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate= method to complete the silicon initialization and provides bootloader an opportun= ity to get control after system memory is available and before the temporary RAM i= s torn down. - @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data struct= ure. + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data sructu= re. @param[out] HobListPtr Pointer to receive the address of t= he HOB list. @retval EFI_SUCCESS FSP execution environment was initi= alized successfully. @@ -271,7 +271,7 @@ EFI_STATUS @retval EFI_INVALID_PARAMETER Input parameters are invalid. @retval EFI_UNSUPPORTED The FSP calling conditions were not= met. @retval EFI_DEVICE_ERROR FSP initialization failed. - @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status c= odes will not be returned during S3. + @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status co= des will not be returned during S3. **/ typedef EFI_STATUS diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2P= kg/Include/Library/FspSecPlatformLib.h index 4d01b5f6d9..48b04c5a90 100644 =2D-- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -66,7 +66,7 @@ SecCarInit ( ); /** - This function check the signature of UPD. + This function check the signture of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c b/IntelFsp2Pkg/L= ibrary/BaseCacheLib/CacheLib.c index 17e895c345..927cee13d3 100644 =2D-- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -52,8 +52,8 @@ IsDefaultType ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Aligned. - @retval Non-Zero Not aligned. + @retval Zero Alligned. + @retval Non-Zero Not alligned. **/ UINT32 @@ -217,7 +217,7 @@ Power2MaxMemory ( } // - // Compute initial power of 2 size to return + // Compute inital power of 2 size to return // Result =3D GetPowerOfTwo64(MemoryLength); @@ -247,8 +247,8 @@ Power2MaxMemory ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Aligned. - @retval Non-Zero Not aligned. + @retval Zero Alligned. + @retval Non-Zero Not alligned. **/ UINT32 diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c b/I= ntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c index b34905365d..17688c7fcb 100644 =2D-- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c +++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c @@ -186,7 +186,7 @@ DebugBPrint ( } /** - Convert an UINT32 value into HEX string specified by Buffer. + Convert an UINT32 value into HEX string sepcified by Buffer. @param Value The HEX value to convert to string @param Buffer The pointer to the target buffer to be filled with HEX = string @@ -211,8 +211,8 @@ FillHex ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLE= D bit of - PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, = if - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is s= et then + PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, i= f + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is se= t then CpuDeadLoop() is called. If neither of these bits are set, then this f= unction returns immediately after the message is printed to the debug output de= vice. DebugAssert() must actively prevent recursion. If DebugAssert() is cal= led while @@ -265,8 +265,8 @@ DebugAssertInternal ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLE= D bit of - PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, = if - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is s= et then + PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, i= f + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is se= t then CpuDeadLoop() is called. If neither of these bits are set, then this f= unction returns immediately after the message is printed to the debug output de= vice. DebugAssert() must actively prevent recursion. If DebugAssert() is cal= led while @@ -322,10 +322,10 @@ DebugClearMemory ( Returns TRUE if ASSERT() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED b= it of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gProperyMask is clear. **/ BOOLEAN @@ -342,10 +342,10 @@ DebugAssertEnabled ( Returns TRUE if DEBUG() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bi= t of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= PropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= PropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= ProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= ProperyMask is clear. **/ BOOLEAN @@ -361,10 +361,10 @@ DebugPrintEnabled ( Returns TRUE if DEBUG_CODE() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit= of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= ropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= ropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= roperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= roperyMask is clear. **/ BOOLEAN @@ -381,10 +381,10 @@ DebugCodeEnabled ( Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED b= it of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gProperyMask is clear. **/ BOOLEAN diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm b/= IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm index 6599901906..45cc974788 100644 =2D-- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2016, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: ; -; Switch the stack from temporary memory to permanent memory. +; Switch the stack from temporary memory to permenent memory. ; ;------------------------------------------------------------------------= ------ diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nas= m b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm index aef7f96d1d..dc4af7c078 100644 =2D-- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm @@ -2,7 +2,7 @@ ; This is the code that goes from real-mode to protected mode. ; It consumes the reset vector, configures the stack. ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; @@ -54,7 +54,7 @@ ASM_PFX(SecPlatformInit): ; esp ; ; Description: -; Perform any essential early platform initialisation +; Perform any essential early platform initilaisation ; Setup a stack ; ;------------------------------------------------------------------------= ---- diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibN= ull.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c index f7945b5240..50cb3142d2 100644 =2D-- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c @@ -1,7 +1,7 @@ /** @file Null instance of Platform Sec Lib. - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -10,7 +10,7 @@ #include /** - This function check the signature of UPD. + This function check the signture of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOp= t.py index a42717caae..c4e1e6239d 100644 =2D-- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -535,7 +535,7 @@ EndList Offset =3D 0 else: if DscLine.startswith('!'): - print("ERROR: Unrecognized di= rective for line '%s'" % DscLine) + print("ERROR: Unrecoginized d= irective for line '%s'" % DscLine) raise SystemExit if not Handle: continue diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py index edb30c816b..2173984dea 100644 =2D-- a/IntelFsp2Pkg/Tools/PatchFv.py +++ b/IntelFsp2Pkg/Tools/PatchFv.py @@ -160,7 +160,7 @@ class Symbols: # def createDicts (self, fvDir, fvNames): # - # If the fvDir is not a directory, then raise an exception + # If the fvDir is not a dirctory, then raise an exception # if not os.path.isdir(fvDir): raise Exception ("'%s' is not a valid directory!" % FvDir) diff --git a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md b/Intel= Fsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md index 0a0f592801..938c18416d 100644 =2D-- a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md @@ -213,7 +213,7 @@ in the third. ```@Bsf NAME:{Variable 1} TYPE:{Combo}``` There is a special **None** type that puts the variable in the **StructDe= f** -region of the BSF, but doesn't put it in any **Page** section. This makes= the +region of the BSF, but doesn?t put it in any **Page** section. This makes= the variable visible to BCT, but not to the end user. ###HELP diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md b/IntelFs= p2Pkg/Tools/UserManuals/PatchFvUserManual.md index 5f1031e729..becaf96b21 100644 =2D-- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md @@ -30,7 +30,7 @@ FSP tree. The example used contains Windows batch script %VARIABLES%. -#FvFileBaseNames (Argument 2: Optional Part 1) +#FvFileBaseNames (Argument 2: 0ptional Part 1) The firmware volume file base names (**_FvFileBaseNames_**) are the indep= endent Fv?s that are to be patched within the FD. (0 or more in the form **FVFILEBASENAME:**) The colon **:** is used for delimiting the single =2D- 2.20.1 (Apple Git-117) =46rom bee5866c09bd18f9c3d40aeb56c5595be0a07bfe Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?Antoine=3D20C=3DC5=3D93ur?=3D Date: Thu, 11 Jul 2019 17:30:10 +0800 Subject: [PATCH] IntelFsp2Pkg: Fix various typos Fix various typos in IntelFsp2Pkg. Signed-off-by: Coeur Reviewed-by: Star Zeng Reviewed-by: Chasel Chiu =2D-- .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- .../FspSecCore/Ia32/InitializeFpu.nasm | 4 +-- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 +-- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- .../Include/Library/FspSecPlatformLib.h | 4 +-- IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++---- .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +++++++++---------- .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- .../PlatformSecLibNull.c | 4 +-- IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- IntelFsp2Pkg/Tools/PatchFv.py | 2 +- .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- .../Tools/UserManuals/PatchFvUserManual.md | 2 +- 18 files changed, 52 insertions(+), 52 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg= /FspSecCore/Ia32/FspApiEntryM.nasm index f14c18c7b9..e7261b41cd 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ; ; Pass BFV into the PEI Core - ; It uses relative address to calucate the actual boot FV base + ; It uses relative address to calculate the actual boot FV base ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase a= nd - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, ; they are different. The code below can handle both cases. ; call ASM_PFX(AsmGetFspBaseAddress) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/InitializeFpu.nasm index e1886ea11b..ebc91c41e4 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw [ASM_PFX(mFpuControlWord)] ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFs= p2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index b257deb76c..4c321cbece 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord] ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to= test + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to = test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSec= Core/Ia32/Stack.nasm index d72212ed45..5a7e27c240 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2015, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to perm= anent memory ; - ; Fixup the ebp point to permenent memory + ; Fixup the ebp point to permanent memory ; mov eax, ebp sub eax, ebx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Se= cFsp.c index 6497c88ebe..446d1730e9 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -169,7 +169,7 @@ FspGlobalDataInit ( SerialPortInitialize (); // - // Ensure the golbal data pointer is valid + // Ensure the global data pointer is valid // ASSERT (GetFspGlobalDataPointer () =3D=3D PeiFspData); diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/S= ecMain.c index cd3ab46ce2..a63d1336e4 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/SecMain.c +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c @@ -110,7 +110,7 @@ SecStartup ( // |-------------------|----> // | | // | | - // | Heap | PeiTemporayRamSize + // | Heap | PeiTemporaryRamSize // | | // | | // |-------------------|----> TempRamBase diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2P= kg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 index f25de0206a..c519874809 100644 =2D-- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 @@ -2,7 +2,7 @@ ; Reset Vector Data structure ; This structure is located at 0xFFFFFFC0 ; -; Copyright (c) 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;; @@ -61,7 +61,7 @@ ApStartup: ; ; Jmp Rel16 instruction ; Use machine code directly in case of the assembler optimization - ; SEC entry point relatvie address will be fixed up by some build too= l. + ; SEC entry point relative address will be fixed up by some build too= l. ; ; Typically, SEC entry point is the function _ModuleEntryPoint() defi= ned in ; SecEntry.asm diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/F= spEas/FspApi.h index 1d38e639e6..dcf489dbe6 100644 =2D-- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -2,7 +2,7 @@ Intel FSP API definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -211,12 +211,12 @@ EFI_STATUS each FSP release. After FspMemInit completes its execution, it passes the pointer to the = HobList and returns to the boot loader from where it was called. BootLoader is resp= onsible to - migrate it's stack and data to Memory. + migrate its stack and data to Memory. FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate= method to complete the silicon initialization and provides bootloader an opportun= ity to get control after system memory is available and before the temporary RAM i= s torn down. - @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data sructu= re. + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data struct= ure. @param[out] HobListPtr Pointer to receive the address of t= he HOB list. @retval EFI_SUCCESS FSP execution environment was initi= alized successfully. @@ -271,7 +271,7 @@ EFI_STATUS @retval EFI_INVALID_PARAMETER Input parameters are invalid. @retval EFI_UNSUPPORTED The FSP calling conditions were not= met. @retval EFI_DEVICE_ERROR FSP initialization failed. - @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status co= des will not be returned during S3. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status c= odes will not be returned during S3. **/ typedef EFI_STATUS diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2P= kg/Include/Library/FspSecPlatformLib.h index 48b04c5a90..4d01b5f6d9 100644 =2D-- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -66,7 +66,7 @@ SecCarInit ( ); /** - This function check the signture of UPD. + This function check the signature of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c b/IntelFsp2Pkg/L= ibrary/BaseCacheLib/CacheLib.c index 927cee13d3..17e895c345 100644 =2D-- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -52,8 +52,8 @@ IsDefaultType ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Alligned. - @retval Non-Zero Not alligned. + @retval Zero Aligned. + @retval Non-Zero Not aligned. **/ UINT32 @@ -217,7 +217,7 @@ Power2MaxMemory ( } // - // Compute inital power of 2 size to return + // Compute initial power of 2 size to return // Result =3D GetPowerOfTwo64(MemoryLength); @@ -247,8 +247,8 @@ Power2MaxMemory ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Alligned. - @retval Non-Zero Not alligned. + @retval Zero Aligned. + @retval Non-Zero Not aligned. **/ UINT32 diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c b/I= ntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c index 17688c7fcb..b34905365d 100644 =2D-- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c +++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c @@ -186,7 +186,7 @@ DebugBPrint ( } /** - Convert an UINT32 value into HEX string sepcified by Buffer. + Convert an UINT32 value into HEX string specified by Buffer. @param Value The HEX value to convert to string @param Buffer The pointer to the target buffer to be filled with HEX = string @@ -211,8 +211,8 @@ FillHex ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLE= D bit of - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, i= f - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is se= t then + PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, = if + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is s= et then CpuDeadLoop() is called. If neither of these bits are set, then this f= unction returns immediately after the message is printed to the debug output de= vice. DebugAssert() must actively prevent recursion. If DebugAssert() is cal= led while @@ -265,8 +265,8 @@ DebugAssertInternal ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLE= D bit of - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, i= f - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is se= t then + PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, = if + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is s= et then CpuDeadLoop() is called. If neither of these bits are set, then this f= unction returns immediately after the message is printed to the debug output de= vice. DebugAssert() must actively prevent recursion. If DebugAssert() is cal= led while @@ -322,10 +322,10 @@ DebugClearMemory ( Returns TRUE if ASSERT() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED b= it of - PcdDebugProperyMask is set. Otherwise FALSE is returned. + PcdDebugPropertyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gProperyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gProperyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gPropertyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebu= gPropertyMask is clear. **/ BOOLEAN @@ -342,10 +342,10 @@ DebugAssertEnabled ( Returns TRUE if DEBUG() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bi= t of - PcdDebugProperyMask is set. Otherwise FALSE is returned. + PcdDebugPropertyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= ProperyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= ProperyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= PropertyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebug= PropertyMask is clear. **/ BOOLEAN @@ -361,10 +361,10 @@ DebugPrintEnabled ( Returns TRUE if DEBUG_CODE() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit= of - PcdDebugProperyMask is set. Otherwise FALSE is returned. + PcdDebugPropertyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= roperyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= roperyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= ropertyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugP= ropertyMask is clear. **/ BOOLEAN @@ -381,10 +381,10 @@ DebugCodeEnabled ( Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED b= it of - PcdDebugProperyMask is set. Otherwise FALSE is returned. + PcdDebugPropertyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gProperyMask is set. - @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gProperyMask is clear. + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gPropertyMask is set. + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebu= gPropertyMask is clear. **/ BOOLEAN diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm b/= IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm index 45cc974788..6599901906 100644 =2D-- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------= ------ ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: ; -; Switch the stack from temporary memory to permenent memory. +; Switch the stack from temporary memory to permanent memory. ; ;------------------------------------------------------------------------= ------ diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nas= m b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm index dc4af7c078..aef7f96d1d 100644 =2D-- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm @@ -2,7 +2,7 @@ ; This is the code that goes from real-mode to protected mode. ; It consumes the reset vector, configures the stack. ; -; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; @@ -54,7 +54,7 @@ ASM_PFX(SecPlatformInit): ; esp ; ; Description: -; Perform any essential early platform initilaisation +; Perform any essential early platform initialisation ; Setup a stack ; ;------------------------------------------------------------------------= ---- diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibN= ull.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c index 50cb3142d2..f7945b5240 100644 =2D-- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c @@ -1,7 +1,7 @@ /** @file Null instance of Platform Sec Lib. - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -10,7 +10,7 @@ #include /** - This function check the signture of UPD. + This function check the signature of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOp= t.py index c4e1e6239d..a42717caae 100644 =2D-- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -535,7 +535,7 @@ EndList Offset =3D 0 else: if DscLine.startswith('!'): - print("ERROR: Unrecoginized d= irective for line '%s'" % DscLine) + print("ERROR: Unrecognized di= rective for line '%s'" % DscLine) raise SystemExit if not Handle: continue diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py index 2173984dea..edb30c816b 100644 =2D-- a/IntelFsp2Pkg/Tools/PatchFv.py +++ b/IntelFsp2Pkg/Tools/PatchFv.py @@ -160,7 +160,7 @@ class Symbols: # def createDicts (self, fvDir, fvNames): # - # If the fvDir is not a dirctory, then raise an exception + # If the fvDir is not a directory, then raise an exception # if not os.path.isdir(fvDir): raise Exception ("'%s' is not a valid directory!" % FvDir) diff --git a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md b/Intel= Fsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md index 938c18416d..0a0f592801 100644 =2D-- a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md @@ -213,7 +213,7 @@ in the third. ```@Bsf NAME:{Variable 1} TYPE:{Combo}``` There is a special **None** type that puts the variable in the **StructDe= f** -region of the BSF, but doesn?t put it in any **Page** section. This makes= the +region of the BSF, but doesn't put it in any **Page** section. This makes= the variable visible to BCT, but not to the end user. ###HELP diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md b/IntelFs= p2Pkg/Tools/UserManuals/PatchFvUserManual.md index becaf96b21..5f1031e729 100644 =2D-- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md @@ -30,7 +30,7 @@ FSP tree. The example used contains Windows batch script %VARIABLES%. -#FvFileBaseNames (Argument 2: 0ptional Part 1) +#FvFileBaseNames (Argument 2: Optional Part 1) The firmware volume file base names (**_FvFileBaseNames_**) are the indep= endent Fv?s that are to be patched within the FD. (0 or more in the form **FVFILEBASENAME:**) The colon **:** is used for delimiting the single =2D- 2.20.1 (Apple Git-117)