From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ashraf.javeed@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Sun, 21 Jul 2019 23:26:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jul 2019 23:26:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,294,1559545200"; d="scan'208";a="196649268" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.253]) by fmsmga002.fm.intel.com with ESMTP; 21 Jul 2019 23:26:53 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Ray Ni , Hao A Wu Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Date: Mon, 22 Jul 2019 11:56:27 +0530 Message-Id: <20190722062627.12276-1-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007 The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI features like - LN system CLS, 10b Tag completer/requester register fields, emergency power reduction support and initialization requirement, and FRS support. The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the - emergency power reduction request enabling and also the 10b Extended Tag enabling. Needs macro definitions for all the ranges of Maximum Payload Sizes and Maximum Read Request Sizes defined Needs macro definitions for all the ranges of Completion Timeout range needs to be defined. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Hao A Wu --- MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index d4003de74c..e652e77a1e 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -91,6 +91,24 @@ typedef union { UINT16 Uint16; } PCI_REG_PCIE_DEVICE_CONTROL; +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 + +#define PCIE_MAX_READ_REQ_SIZE_128B 0 +#define PCIE_MAX_READ_REQ_SIZE_256B 1 +#define PCIE_MAX_READ_REQ_SIZE_512B 2 +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 + typedef union { struct { UINT16 CorrectableError : 1; @@ -250,16 +268,30 @@ typedef union { UINT32 NoRoEnabledPrPrPassing : 1; UINT32 LtrMechanism : 1; UINT32 TphCompleter : 2; - UINT32 Reserved : 4; + UINT32 LnSystemCLS : 2; + UINT32 TenBitTagCompleterSupported : 1; + UINT32 TenBitTagRequesterSupported : 1; UINT32 Obff : 2; UINT32 ExtendedFmtField : 1; UINT32 EndEndTlpPrefix : 1; UINT32 MaxEndEndTlpPrefixes : 2; - UINT32 Reserved2 : 8; + UINT32 EmergencyPowerReductionSupported : 2; + UINT32 EmergencyPowerReductionInitializationRequired : 1; + UINT32 Reserved : 4; + UINT32 FrsSupported : 1; } Bits; UINT32 Uint32; } PCI_REG_PCIE_DEVICE_CAPABILITY2; +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 + #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 @@ -273,7 +305,8 @@ typedef union { UINT16 IdoRequest : 1; UINT16 IdoCompletion : 1; UINT16 LtrMechanism : 2; - UINT16 Reserved : 2; + UINT16 EmergencyPowerReductionRequest : 1; + UINT16 TenBitTagRequesterEnable : 1; UINT16 Obff : 2; UINT16 EndEndTlpPrefixBlocking : 1; } Bits; -- 2.21.0.windows.1