From: "Ni, Ray" <ray.ni@intel.com>
To: devel@edk2.groups.io
Cc: Eric Dong <eric.dong@intel.com>, Laszlo Ersek <lersek@redhat.com>
Subject: [PATCH 2/4] UefiCpuPkg/CpuDxe: Support parsing 5-level page table
Date: Mon, 22 Jul 2019 16:15:45 +0800 [thread overview]
Message-ID: <20190722081547.56100-3-ray.ni@intel.com> (raw)
In-Reply-To: <20190722081547.56100-1-ray.ni@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
---
UefiCpuPkg/CpuDxe/CpuPageTable.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index c369b44f12..8e959eb2b7 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -1,7 +1,7 @@
/** @file
Page table management support.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -276,25 +276,43 @@ GetPageTableEntry (
UINTN Index2;
UINTN Index3;
UINTN Index4;
+ UINTN Index5;
UINT64 *L1PageTable;
UINT64 *L2PageTable;
UINT64 *L3PageTable;
UINT64 *L4PageTable;
+ UINT64 *L5PageTable;
UINT64 AddressEncMask;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
ASSERT (PagingContext != NULL);
+ Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;
Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;
Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;
Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+
// Make sure AddressEncMask is contained to smallest supported address field.
//
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {
- L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
+ if (Enable5LevelPaging) {
+ L5PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
+ if (L5PageTable[Index5] == 0) {
+ *PageAttribute = PageNone;
+ return NULL;
+ }
+
+ L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);
+ } else {
+ L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
+ }
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
return NULL;
--
2.21.0.windows.1
next prev parent reply other threads:[~2019-07-22 8:16 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-22 8:15 [PATCH 0/4] Support 5-level paging in DXE long mode Ni, Ray
2019-07-22 8:15 ` [PATCH 1/4] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled Ni, Ray
2019-07-23 9:15 ` [edk2-devel] " Laszlo Ersek
2019-07-24 7:02 ` Ni, Ray
2019-07-22 8:15 ` Ni, Ray [this message]
2019-07-23 9:22 ` [edk2-devel] [PATCH 2/4] UefiCpuPkg/CpuDxe: Support parsing 5-level page table Laszlo Ersek
2019-07-24 7:03 ` Ni, Ray
2019-07-25 17:19 ` Laszlo Ersek
2019-07-22 8:15 ` [PATCH 3/4] MdeModulePkg/DxeIpl: Introduce PCD PcdUse5LevelPageTable Ni, Ray
2019-07-23 2:05 ` [edk2-devel] " Wu, Hao A
2019-07-23 14:20 ` Ni, Ray
2019-07-24 2:02 ` Dong, Eric
2019-07-22 8:15 ` [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode Ni, Ray
2019-07-23 2:05 ` [edk2-devel] " Wu, Hao A
2019-07-23 7:48 ` Laszlo Ersek
2019-07-23 19:45 ` Singh, Brijesh
2019-07-23 9:46 ` Laszlo Ersek
2019-07-23 15:29 ` Ni, Ray
2019-07-23 19:20 ` Laszlo Ersek
2019-07-23 23:54 ` Michael D Kinney
2019-07-24 1:40 ` Ni, Ray
[not found] ` <15B3ACB4E8DDF416.7925@groups.io>
2019-07-22 8:28 ` [edk2-devel] [PATCH 3/4] MdeModulePkg/DxeIpl: Introduce PCD PcdUse5LevelPageTable Ni, Ray
[not found] ` <15B3ACB536E52165.29669@groups.io>
2019-07-22 8:28 ` [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode Ni, Ray
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