From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=EU+I+tCI; spf=pass (domain: linaro.org, ip: 209.85.215.196, mailfrom: masahisa.kojima@linaro.org) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by groups.io with SMTP; Mon, 22 Jul 2019 04:57:44 -0700 Received: by mail-pg1-f196.google.com with SMTP id f20so8323432pgj.0 for ; Mon, 22 Jul 2019 04:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SMzsXQhTkIqiF/0tNdvrYnvaVlFnPLQ3IBWe8MkmBNk=; b=EU+I+tCI+4qMY7T+LzRW3h89VTVVYoEBsXlnIaY7X4kQkRO1JG2i22kDFeJpC15H3a czFwJ9zsvOSc+kXhVsJGmX81LPaeF9ZdtCq0UciNPshSkQ+/ZSPVUAlSShTKHWqpDZ8R nE7AF04viHJwNC95JmIJ/wHZo3VAmk5HhJc8nJPYpYGdxV7UuiDyKxI/kqlADM8pVK0K r9cAtBeuUVPHjwmhyBMrKFOgJYQz8GCjI4XYEkFaJ8je3N5mSf6xPe6llShEvmvFTxRu lEsh5OFp5Hsd9M62L9DKOcAOetD7uftJZPO0JWIDIe8hI+ImcRhYNdPvhKdTd8xir+F7 XLZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SMzsXQhTkIqiF/0tNdvrYnvaVlFnPLQ3IBWe8MkmBNk=; b=gGEfvN7IIgR+AXhDdqGmOySwciG47TMVkM+AC4KoYLP3UcPgh8Ms8blVjjXfKLwzVD RbJOmJDA17YXkaCRvygRGIA/blJOEn3Uda56drAHGW5qdNnPfSddzUEIjDFVYjaTANGr dK7JgHrhkFREHYBAV/V1OltCe5EVTdgUMNSZmr98XpNIR7P5/CmCjgjs7paBPaFzVBcZ ZLgp0xN7gQxWMCjEsxn4uz8F+Zy7R+OrpdN+7YbTFlU5D1T0ZBhnr0uRL5SaOVMez0Fa pCxD67RReTtnJQ72MUrutJGqqQIwfyK26nxRfWctNPkNrVFuZiI1TT9KD4WxyXbOyhw/ 6hsQ== X-Gm-Message-State: APjAAAVaxYiOvBaEZwj5tQFV4nLcEEqY8Z2UXTv0tps/QkINbuqeU2fR Gom6xZFn4S/DwcUWnEkapc9ZOgrflCM= X-Google-Smtp-Source: APXvYqxL7YiobXkzV52iCkrAMItE6tcfrWfEpVvrhYAQ++gBKdfFafABMuhKzD/0jsydEax3lOUQqw== X-Received: by 2002:a63:2807:: with SMTP id o7mr41533063pgo.131.1563796663526; Mon, 22 Jul 2019 04:57:43 -0700 (PDT) Return-Path: Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id 64sm41174145pfe.128.2019.07.22.04.57.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jul 2019 04:57:42 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-platforms PATCH v1 2/3] NetsecDxe: put phy in loopback mode in order to guarantee stable RXCLK input Date: Mon, 22 Jul 2019 20:56:35 +0900 Message-Id: <20190722115636.3413-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190722115636.3413-1-masahisa.kojima@linaro.org> References: <20190722115636.3413-1-masahisa.kojima@linaro.org> NETSEC hardware requires stable RXCLK input upon initialization triggered with DISCORE = 0. However, RXCLK input could be unstable depending on phy chipset and deployed network environment, which could cause NETSEC to hang up during initialization. We solve this platform/environment dependent issue by temporarily putting phy in loopback mode, then we can expect the stable RXCLK input. Signed-off-by: Masahisa Kojima Signed-off-by: Satoru Okamoto --- .../netsec_sdk/src/ogma_misc.c | 72 ++++++++++++++++++- .../netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 4 ++ 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 7481d2da2d24..07308d38a5c2 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c @@ -35,7 +35,6 @@ static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = }; - /* Internal function definition*/ #ifndef OGMA_CONFIG_DISABLE_CLK_CTRL STATIC void ogma_set_clk_en_reg ( @@ -327,6 +326,60 @@ STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param ( return param; } +STATIC +void +ogma_pre_init_microengine ( + ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Remove dormant settings */ + Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE)); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE))) != 0); + + /* Put phy in loopback mode to guarantee RXCLK input */ + Data |= (1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) == 0); +} + +STATIC +void +ogma_post_init_microengine ( + IN ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Get phy back to normal operation */ + Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) != 0); + + Data |= (1U << OGMA_PHY_CONTROL_REG_RESET); + + /* Apply software reset */ + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_RESET)) != 0); +} + ogma_err_t ogma_init ( void *base_addr, pfdep_dev_handle_t dev_handle, @@ -551,6 +604,16 @@ ogma_err_t ogma_init ( ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL, ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) ); + /* + * Do pre-initialization tasks for microengine + * + * In particular, we put phy in loopback mode + * in order to make sure RXCLK keeps provided to mac + * irrespective of phy link status, + * which is required for microengine intialization. + */ + ogma_pre_init_microengine (ctrl_p); + /* start microengines */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0); @@ -573,6 +636,13 @@ ogma_err_t ogma_init ( goto err; } + /* + * Do post-initialization tasks for microengine + * + * We put phy in normal mode and apply reset. + */ + ogma_post_init_microengine (ctrl_p); + /* clear microcode load end status */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS, OGMA_TOP_IRQ_REG_ME_START); diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h index 30c716352b37..ca769084cb31 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h @@ -138,8 +138,12 @@ /* bit fields for PHY CONTROL Register */ #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6) #define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8) +#define OGMA_PHY_CONTROL_REG_ISOLATE (10) +#define OGMA_PHY_CONTROL_REG_POWER_DOWN (11) #define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12) #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13) +#define OGMA_PHY_CONTROL_REG_LOOPBACK (14) +#define OGMA_PHY_CONTROL_REG_RESET (15) /* bit fields for PHY STATUS Register */ #define OGMA_PHY_STATUS_REG_LINK_STATUS (2) -- 2.17.1