From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: michael.d.kinney@intel.com) Received: from mga02.intel.com (mga02.intel.com []) by groups.io with SMTP; Mon, 22 Jul 2019 15:59:07 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 15:59:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,296,1559545200"; d="scan'208";a="169386493" Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.83.213]) by fmsmga008.fm.intel.com with ESMTP; 22 Jul 2019 15:59:05 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Zailiang Sun , Yi Qian , Gary Lin Subject: [edk2-platforms Patch V3 06/12] Vlv2TbltDevicePkg: Remove non ASCII characters from source files Date: Mon, 22 Jul 2019 15:58:53 -0700 Message-Id: <20190722225859.24724-7-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190722225859.24724-1-michael.d.kinney@intel.com> References: <20190722225859.24724-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove non-ASCII characters from comments in source files. These are preventing the build tool from generating report files on Linux systems. Cc: Zailiang Sun Cc: Yi Qian Cc: Gary Lin Signed-off-by: Michael D Kinney --- .../Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c | 2 +- Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c index 4a51a47e36..71d6cb7c15 100644 --- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c @@ -461,7 +461,7 @@ UARTInit ( if (SystemConfiguration->LpssHsuart0Enabled == 1){ // //Valleyview BIOS Specification Vol2,17.2 - //LPSS_UART1 ¨C set each pad PAD_CONF0.Func_Pin_Mux to function 1: + //LPSS_UART1 C set each pad PAD_CONF0.Func_Pin_Mux to function 1: // MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07); MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01); diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c index 4c0e660b7f..2061b8d559 100644 --- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c @@ -205,9 +205,9 @@ GetSleepTypeAfterWakeup ( // VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration" // // When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost. - // This bit is in the SUS Well and defaults to 1’b1 based on RSMRST# assertion (not cleared by any type of reset). + // This bit is in the SUS Well and defaults to 1'b1 based on RSMRST# assertion (not cleared by any type of reset). // System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]), - // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1’b1 + // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1'b1 // regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field. // GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1); -- 2.21.0.windows.1