Re: [edk2-platforms Patch V3 06/12] Vlv2TbltDevicePkg: Remove non ASCII characters from source files

["Gary Lin" <glin@suse.com>]

On Mon, Jul 22, 2019 at 03:58:53PM -0700, Michael D Kinney wrote:
> Remove non-ASCII characters from comments in source files.  These
> are preventing the build tool from generating report files on
> Linux systems.
> 
I see the report file now. Thanks for fixing those characters.

Reviewed-by: Gary Lin <glin@suse.com>

> Cc: Zailiang Sun <zailiang.sun@intel.com>
> Cc: Yi Qian <yi.qian@intel.com>
> Cc: Gary Lin <glin@suse.com>
> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
> ---
>  .../Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c     | 2 +-
>  Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c       | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> index 4a51a47e36..71d6cb7c15 100644
> --- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> @@ -461,7 +461,7 @@ UARTInit (
>        if (SystemConfiguration->LpssHsuart0Enabled == 1){
>          //
>          //Valleyview BIOS Specification Vol2,17.2
> -        //LPSS_UART1 �C set each pad PAD_CONF0.Func_Pin_Mux to function 1:
> +        //LPSS_UART1 C set each pad PAD_CONF0.Func_Pin_Mux to function 1:
>          //
>          MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
>          MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> index 4c0e660b7f..2061b8d559 100644
> --- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> @@ -205,9 +205,9 @@ GetSleepTypeAfterWakeup (
>    // VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration"
>    //
>    // When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.
> -  // This bit is in the SUS Well and defaults to 1�b1 based on RSMRST# assertion (not cleared by any type of reset).
> +  // This bit is in the SUS Well and defaults to 1'b1 based on RSMRST# assertion (not cleared by any type of reset).
>    // System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]),
> -  // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1�b1
> +  // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1'b1
>    // regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.
>    //
>    GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
> -- 
> 2.21.0.windows.1
> 
>