From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: chasel.chiu@intel.com) Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Mon, 29 Jul 2019 04:07:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jul 2019 04:07:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,322,1559545200"; d="scan'208";a="165445397" Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.67]) by orsmga008.jf.intel.com with ESMTP; 29 Jul 2019 04:07:55 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Ankit Sinha , Nate DeSimone , Liming Gao Subject: [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD Date: Mon, 29 Jul 2019 19:07:15 +0800 Message-Id: <20190729110715.2312-5-chasel.chiu@intel.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20190729110715.2312-1-chasel.chiu@intel.com> References: <20190729110715.2312-1-chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863 PcdFsp*BaseAddress now will be updated in FDF basing on flash map. DSC will only define types of those PCDs and always having 0 as default. Test: interanl platform booted with this patch. Cc: Michael Kubacki Cc: Ankit Sinha Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++ Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index da498ad379..c425e4b280 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize ################################################################################ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc index c6bce19856..83cbd18557 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc @@ -109,8 +109,11 @@ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 !endif - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss @@ -201,7 +204,10 @@ !endif [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 # Platform will pre-allocate UPD buffer and pass it to FspWrapper # Those dummy address will be patched before FspWrapper executing gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF -- 2.13.3.windows.1