From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: eric.dong@intel.com) Received: from mga14.intel.com (mga14.intel.com []) by groups.io with SMTP; Wed, 07 Aug 2019 23:25:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 23:25:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="198923313" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga004.fm.intel.com with ESMTP; 07 Aug 2019 23:25:09 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: "Ni, Ray" , Jiewen Yao , Laszlo Ersek Subject: [Patch v6 3/9] UefiCpuPkg/CpuDxe: Remove unnecessary macros Date: Thu, 8 Aug 2019 14:24:54 +0800 Message-Id: <20190808062500.26996-4-eric.dong@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190808062500.26996-1-eric.dong@intel.com> References: <20190808062500.26996-1-eric.dong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Ni, Ray" Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when checking whether individual bits are set in CR0 or CR4 register. The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined in MdePkg/Include/Library/BaseLib.h so that the module local macros can be removed. There is no functionality impact to this change. Signed-off-by: Ray Ni Cc: Jiewen Yao Reviewed-by: Eric Dong Regression-tested-by: Laszlo Ersek --- UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c index c369b44f12..16a2528b55 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -1,7 +1,7 @@ /** @file Page table management support. - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -21,14 +21,6 @@ #include "CpuDxe.h" #include "CpuPageTable.h" -/// -/// Paging registers -/// -#define CR0_WP BIT16 -#define CR0_PG BIT31 -#define CR4_PSE BIT4 -#define CR4_PAE BIT5 - /// /// Page Table Entry /// @@ -161,6 +153,8 @@ GetCurrentPagingContext ( UINT32 RegEax; CPUID_EXTENDED_CPU_SIG_EDX RegEdx; MSR_IA32_EFER_REGISTER MsrEfer; + IA32_CR4 Cr4; + IA32_CR0 Cr0; // // Don't retrieve current paging context from processor if in SMM mode. @@ -172,21 +166,24 @@ GetCurrentPagingContext ( } else { mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386; } - if ((AsmReadCr0 () & CR0_PG) != 0) { + + Cr0.UintN = AsmReadCr0 (); + Cr4.UintN = AsmReadCr4 (); + + if (Cr0.Bits.PG != 0) { mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } else { mPagingContext.ContextData.X64.PageTableBase = 0; } - - if ((AsmReadCr4 () & CR4_PSE) != 0) { + if (Cr0.Bits.WP != 0) { + mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; + } + if (Cr4.Bits.PSE != 0) { mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE; } - if ((AsmReadCr4 () & CR4_PAE) != 0) { + if (Cr4.Bits.PAE != 0) { mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE; } - if ((AsmReadCr0 () & CR0_WP) != 0) { - mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; - } AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); if (RegEax >= CPUID_EXTENDED_CPU_SIG) { @@ -581,12 +578,14 @@ IsReadOnlyPageWriteProtected ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { - return ((AsmReadCr0 () & CR0_WP) != 0); + Cr0.UintN = AsmReadCr0 (); + return (BOOLEAN) (Cr0.Bits.WP != 0); } return FALSE; } @@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); + Cr0.UintN = AsmReadCr0 (); + Cr0.Bits.WP = 0; + AsmWriteCr0 (Cr0.UintN); } } @@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { - AsmWriteCr0 (AsmReadCr0 () | CR0_WP); + Cr0.UintN = AsmReadCr0 (); + Cr0.Bits.WP = 1; + AsmWriteCr0 (Cr0.UintN); } } -- 2.21.0.windows.1