* [edk2-platforms: PATCH v2] Marvell/Drivers: XenonDxe: Explicitly disable HS400
@ 2019-08-07 19:46 Marcin Wojtas
2019-08-08 10:55 ` Leif Lindholm
0 siblings, 1 reply; 2+ messages in thread
From: Marcin Wojtas @ 2019-08-07 19:46 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
On another SoC revision, the capability register marks HS400 support
as enabled. However in case the interface itself is powered with 3.3V
this flag must be unset by the SdMmcOverride protocol callback -
otherwise the generic EmmcSwitchToHS400 () would be executed
with a failure.
Ensure that in case of SlowMode or 3.3V operation, the HS400 capability
will be disabled in the SdMmc driver, along with other highest-speed
modes.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 +
Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
index afc2b2f..2ad23e2 100644
--- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
+++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
@@ -55,6 +55,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define SDHC_CAP_SDR50 BIT32
#define SDHC_CAP_SDR104 BIT33
#define SDHC_CAP_DDR50 BIT34
+#define SDHC_CAP_HS400 BIT63
#define SDHC_MAX_CURRENT_CAP 0x0048
#define SDHC_FORCE_EVT_AUTO_CMD 0x0050
#define SDHC_FORCE_EVT_ERR_INT 0x0052
diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
index 3b54459..afd650b 100644
--- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
+++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
@@ -330,7 +330,8 @@ XenonSdMmcCapability (
Capability &= ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30);
} else {
Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 |
- SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18);
+ SDHC_CAP_SDR50 | SDHC_CAP_HS400 |
+ SDHC_CAP_VOLTAGE_18);
}
if (!SdMmcDesc.Xenon8BitBusEnabled) {
@@ -338,7 +339,7 @@ XenonSdMmcCapability (
}
if (SdMmcDesc.XenonSlowModeEnabled) {
- Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50);
+ Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_HS400);
}
Capability &= ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK);
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [edk2-platforms: PATCH v2] Marvell/Drivers: XenonDxe: Explicitly disable HS400
2019-08-07 19:46 [edk2-platforms: PATCH v2] Marvell/Drivers: XenonDxe: Explicitly disable HS400 Marcin Wojtas
@ 2019-08-08 10:55 ` Leif Lindholm
0 siblings, 0 replies; 2+ messages in thread
From: Leif Lindholm @ 2019-08-08 10:55 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: devel, ard.biesheuvel, jsd, jaz, kostap
On Wed, Aug 07, 2019 at 09:46:12PM +0200, Marcin Wojtas wrote:
> On another SoC revision, the capability register marks HS400 support
> as enabled. However in case the interface itself is powered with 3.3V
> this flag must be unset by the SdMmcOverride protocol callback -
> otherwise the generic EmmcSwitchToHS400 () would be executed
> with a failure.
>
> Ensure that in case of SlowMode or 3.3V operation, the HS400 capability
> will be disabled in the SdMmc driver, along with other highest-speed
> modes.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Pushed as ca4f575fd63b.
Thanks!
> ---
> Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 +
> Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
> index afc2b2f..2ad23e2 100644
> --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
> +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h
> @@ -55,6 +55,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define SDHC_CAP_SDR50 BIT32
> #define SDHC_CAP_SDR104 BIT33
> #define SDHC_CAP_DDR50 BIT34
> +#define SDHC_CAP_HS400 BIT63
> #define SDHC_MAX_CURRENT_CAP 0x0048
> #define SDHC_FORCE_EVT_AUTO_CMD 0x0050
> #define SDHC_FORCE_EVT_ERR_INT 0x0052
> diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
> index 3b54459..afd650b 100644
> --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
> +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c
> @@ -330,7 +330,8 @@ XenonSdMmcCapability (
> Capability &= ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30);
> } else {
> Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 |
> - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18);
> + SDHC_CAP_SDR50 | SDHC_CAP_HS400 |
> + SDHC_CAP_VOLTAGE_18);
> }
>
> if (!SdMmcDesc.Xenon8BitBusEnabled) {
> @@ -338,7 +339,7 @@ XenonSdMmcCapability (
> }
>
> if (SdMmcDesc.XenonSlowModeEnabled) {
> - Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50);
> + Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_HS400);
> }
>
> Capability &= ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK);
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-08-08 10:55 ` Leif Lindholm
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