From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=t87sW+k3; spf=pass (domain: linaro.org, ip: 209.85.210.196, mailfrom: masahisa.kojima@linaro.org) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by groups.io with SMTP; Thu, 08 Aug 2019 05:23:54 -0700 Received: by mail-pf1-f196.google.com with SMTP id r1so44014590pfq.12 for ; Thu, 08 Aug 2019 05:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AJJKo1D44FQMAQcMNFqwtKsDRC5E/Nb4p+7RlfMzlPQ=; b=t87sW+k33ZTGh0ko2GdJDdDrhC9uG/k6TXEVi65fnH3PYPKhSmNiKTJPIsJoYWySMX IE0qvtt2WNu8FFj+3ehfsOfpMvHANLk1f9fvAqHwW6cG1o5ReVDL9jrv573/kI2f5QyM Rkieshh23H4h3exP4Cav6zr4uuK4egM5ORVnhIYkdr3sXclDsOufFW8oyLZb0UacNukq Wwurf3fYOh/mgG0QvctP4iz8dZ7kf8CN6yq8PQY7zaEWljrA7k09xSnC0gNZ9uhuK1Kh JSlr2UtsksdUYJDJM7v96CjstCE6dwzxCFOdBhuvE0hMGu/KMzXBBBaBGwInlfzIvDT0 9a+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AJJKo1D44FQMAQcMNFqwtKsDRC5E/Nb4p+7RlfMzlPQ=; b=k2RVSxFcQSWTEameMX1U+g5RhCvA6CRg36CZ1fca8ApE8swPOvu7NyRd0V6NZboL2y NJ+Rg1GeB3JSQkY+svoSoMc+pTaF601ebrzl4ANTD2R0Pr81y+S0ADU+nns8ua1/sA1w SfzI9bFtVLR03qzLQDPGH9daes0PhYlTEtyIviTbo3CLCe1Frb/yTykJKH6G2O4byV6g sSevXqAH6gsls6ExGBQlYpAYNjq5YOQSB5B0mKMfbNJKWtDJsE5fy22WxRODa3VmiqtZ fYEHnkApgd5RKtINvtnVIVPX+hwNt9ElfPqWFNDlrJs711MK+iaXiW7VSi03C/Fc1kZS vIag== X-Gm-Message-State: APjAAAWtLXplMJJS3DXCOowWuU9ODv2lEPZuQJblHUYoUdjiHWKltBBf kWC6GY94KXkt+mfzrjVRW7my8f9N74U= X-Google-Smtp-Source: APXvYqxjGL+Kd2uyttXPZ3l4zlWtyJEtyS6A13OUuUEVNHS66znudjmmKpZP268dbJqe+NEwoBgnKg== X-Received: by 2002:a63:a66:: with SMTP id z38mr12891885pgk.247.1565267033160; Thu, 08 Aug 2019 05:23:53 -0700 (PDT) Return-Path: Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id f88sm2195424pjg.5.2019.08.08.05.23.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 05:23:52 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [PATCH edk2-platforms v3 2/3] NetsecDxe: put phy in loopback mode to guarantee stable RXCLK input Date: Thu, 8 Aug 2019 21:23:34 +0900 Message-Id: <20190808122335.11883-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808122335.11883-1-masahisa.kojima@linaro.org> References: <20190808122335.11883-1-masahisa.kojima@linaro.org> From: Satoru Okamoto NETSEC hardware requires stable RXCLK input upon initialization triggered with DISCORE = 0. However, RXCLK input could be unstable depending on phy chipset and deployed network environment, which could cause NETSEC to hang up during initialization. We solve this platform/environment dependent issue by temporarily putting phy in loopback mode, then we can expect the stable RXCLK input. Signed-off-by: Masahisa Kojima --- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 72 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 4 ++ 2 files changed, 76 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 7481d2da2d24..5f6ddc0c745e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c @@ -327,6 +327,60 @@ STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param ( return param; } +STATIC +void +ogma_pre_init_microengine ( + ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Remove dormant settings */ + Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE)); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE))) != 0); + + /* Put phy in loopback mode to guarantee RXCLK input */ + Data |= (1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) == 0); +} + +STATIC +void +ogma_post_init_microengine ( + IN ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Get phy back to normal operation */ + Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) != 0); + + Data |= (1U << OGMA_PHY_CONTROL_REG_RESET); + + /* Apply software reset */ + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_RESET)) != 0); +} + ogma_err_t ogma_init ( void *base_addr, pfdep_dev_handle_t dev_handle, @@ -551,6 +605,17 @@ ogma_err_t ogma_init ( ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL, ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) ); + /* + * Do pre-initialization tasks for microengine + * + * In particular, we put phy in loopback mode + * in order to make sure RXCLK keeps provided to mac + * irrespective of phy link status, + * which is required for microengine intialization. + * This will be disabled once microengine initialization complete. + */ + ogma_pre_init_microengine (ctrl_p); + /* start microengines */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0); @@ -573,6 +638,13 @@ ogma_err_t ogma_init ( goto err; } + /* + * Do post-initialization tasks for microengine + * + * We put phy in normal mode and apply reset. + */ + ogma_post_init_microengine (ctrl_p); + /* clear microcode load end status */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS, OGMA_TOP_IRQ_REG_ME_START); diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h index 30c716352b37..ca769084cb31 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h @@ -138,8 +138,12 @@ /* bit fields for PHY CONTROL Register */ #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6) #define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8) +#define OGMA_PHY_CONTROL_REG_ISOLATE (10) +#define OGMA_PHY_CONTROL_REG_POWER_DOWN (11) #define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12) #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13) +#define OGMA_PHY_CONTROL_REG_LOOPBACK (14) +#define OGMA_PHY_CONTROL_REG_RESET (15) /* bit fields for PHY STATUS Register */ #define OGMA_PHY_STATUS_REG_LINK_STATUS (2) -- 2.17.1