From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: eric.dong@intel.com) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:34 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590663" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:31 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [Patch v4 0/6] Add "test then write" mechanism Date: Fri, 16 Aug 2019 11:57:24 +0800 Message-Id: <20190816035730.3252-1-eric.dong@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit v4 changes: 1. Split Reserved field and use one byte as TestThenWrite field. v3 changes: 1. Avoid changing exist API CpuRegisterTableWrite, add new API CpuRegisterTableTestThenWrite which align new adds macros. Only 1/6 patch been changed in v3. V2 changes: 1. Split CR read/write action in to one discrete patch 2. Keep the old logic which continue the process if error found. Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock == 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } With below steps, the Bits.Lock bit will lose its value: 1. Trig normal boot, the Bits.Lock is 0. 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table during normal boot phase. so it's still 0 after resume. This is not an expect behavior. The expect result is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. So the insert action may be skip after warm reboot. The solution for this issue is: 1. Always add "Test then Set" action for above referred MSRs. 2. Detect current value before set new value. Only set new value when current value not same as new value. Cc: Ray Ni Cc: Laszlo Ersek Eric Dong (6): UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros. UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action. UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic. UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action. UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic. UefiCpuPkg/CpuCommonFeaturesLib: Use new macros. UefiCpuPkg/Include/AcpiCpuData.h | 1 + .../Include/Library/RegisterCpuFeaturesLib.h | 91 +++++++++++ .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 -- .../CpuCommonFeaturesLib.c | 8 +- .../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------ .../CpuCommonFeaturesLib/MachineCheck.c | 23 ++- .../CpuFeaturesInitialize.c | 139 +++++++++++------ .../RegisterCpuFeaturesLib.c | 45 +++++- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 133 +++++++++++------ 9 files changed, 375 insertions(+), 221 deletions(-) -- 2.21.0.windows.1