From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: imammedo@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 16 Aug 2019 04:24:17 -0700 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BBB813090FCE; Fri, 16 Aug 2019 11:24:16 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id AF17C43FF3; Fri, 16 Aug 2019 11:24:14 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Cc: "Chen, Yingwen" , edk2-devel-groups-io , Phillip Goerl , "Yao, Jiewen" , "Nakajima, Jun" , Boris Ostrovsky , edk2-rfc-groups-io , Laszlo Ersek , Joao Marcal Lemos Martins , pbonzini@redhat.com Subject: [PATCH QEMU 1/1] q35: use dedicated SMRAM at default SMM_BASE Date: Fri, 16 Aug 2019 07:24:06 -0400 Message-Id: <20190816112407.28180-2-imammedo@redhat.com> In-Reply-To: <20190816112407.28180-1-imammedo@redhat.com> References: <20190816112407.28180-1-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Fri, 16 Aug 2019 11:24:16 +0000 (UTC) it will allow us to hide sensetive SMM_BASE area from non SMM running env, that will allow us to ensure that hotplugged CPU will run trusted SMM BASE relocation code and we won't need to force all present CPUs into SMM mode since we don not care about about 0x30000 content in normal RAM address space. it's a obviously a hack only to demo approach. for easy SMI initialization on SMI entry point SMRAM is aliased in to hajaked normal RAM address space at a0000. Patch should be used with supplied SMBIOS patch, that drops save/restore sequence and just inits SMI entry point. to test to run: qemu-system-x86_64 -M q35 -bios /path_to_seabios/out/bios.bin \ -nodefaults \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios Signed-off-by: Igor Mammedov --- include/hw/pci-host/q35.h | 1 + hw/pci-host/q35.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 5ed77facd0..556ecb835a 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -55,6 +55,7 @@ typedef struct MCHPCIState { MemoryRegion smram_region, open_high_smram; MemoryRegion smram, low_smram, high_smram; MemoryRegion tseg_blackhole, tseg_window; + MemoryRegion smbase, smram_alias; Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0a010be4cf..6c4c0f308c 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -574,6 +574,16 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_set_enabled(&mch->tseg_window, false); memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, &mch->tseg_window); + + memory_region_init_ram(&mch->smm_base, OBJECT(mch), "SMM BASE", MCH_HOST_BRIDGE_SMRAM_C_SIZE, &error_fatal); + memory_region_set_enabled(&mch->smm_base, true); + memory_region_add_subregion(&mch->smram, 0x30000, &mch->smm_base); + + memory_region_init_alias(&mch->smm_base_alias, OBJECT(mch), "smim_base_alias", + &mch->smm_base, 0, MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_set_enabled(&mch->smm_base_alias, true); + memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, &mch->smm_base_alias, 1); + object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&mch->smram), &error_abort); -- 2.18.1