From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: imammedo@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 16 Aug 2019 04:24:19 -0700 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1709AC0272DE; Fri, 16 Aug 2019 11:24:19 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0B9B943FEA; Fri, 16 Aug 2019 11:24:16 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Cc: "Chen, Yingwen" , edk2-devel-groups-io , Phillip Goerl , "Yao, Jiewen" , "Nakajima, Jun" , Boris Ostrovsky , edk2-rfc-groups-io , Laszlo Ersek , Joao Marcal Lemos Martins , pbonzini@redhat.com Subject: [POC Seabios PATCH] seabios: use isolated SMM address space for relocation Date: Fri, 16 Aug 2019 07:24:07 -0400 Message-Id: <20190816112407.28180-3-imammedo@redhat.com> In-Reply-To: <20190816112407.28180-1-imammedo@redhat.com> References: <20190816112407.28180-1-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 16 Aug 2019 11:24:19 +0000 (UTC) for purpose of demo SMRAM (at 0x30000) is aliased at a0000 in system address space for easy initialization of SMI entry point. Here is resulting debug output showing that RAM at 0x30000 is not affected by SMM and only RAM in SMM adderss space is modified: init smm smm_relocate: before relocaten smm_relocate: RAM codeentry 0 smm_relocate: RAM cpu.i64.smm_base 0 smm_relocate: SMRAM codeentry f000c831eac88c smm_relocate: SMRAM cpu.i64.smm_base 0 handle_smi cmd=0 smbase=0x00030000 smm_relocate: after relocaten smm_relocate: RAM codeentry 0 smm_relocate: RAM cpu.i64.smm_base 0 smm_relocate: SMRAM codeentry f000c831eac88c smm_relocate: SMRAM cpu.i64.smm_base a0000 Patch depends on QEMU POC patch that adds SMRAM at 0x30000 in SMM address space PS: configure bios with level 9 debugging and debug port Signed-off-by: Igor Mammedov --- src/fw/smm.c | 43 +++++++++++++++++++------------------------ 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/src/fw/smm.c b/src/fw/smm.c index d90e43a9..27f9747e 100644 --- a/src/fw/smm.c +++ b/src/fw/smm.c @@ -140,21 +140,22 @@ extern void entry_smi(void); | ((u64)((u32)entry_smi - BUILD_BIOS_ADDR) << 24)) static void -smm_save_and_copy(void) +smm_relocate(void) { - // save original memory content struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR; struct smm_layout *smm = (void*)BUILD_SMM_ADDR; - memcpy(&smm->cpu, &initsmm->cpu, sizeof(smm->cpu)); - memcpy(&smm->codeentry, &initsmm->codeentry, sizeof(smm->codeentry)); - // Setup code entry point. - initsmm->codeentry = SMI_INSN; -} + dprintf(3, "smm_relocate: before relocaten\n"); + dprintf(3, "smm_relocate: RAM codeentry %llx\n", initsmm->codeentry); + dprintf(3, "smm_relocate: RAM cpu.i64.smm_base %lx\n", initsmm->cpu.i64.smm_base); + + + /* BUILD_SMM_ADDR aliased to BUILD_SMM_INIT_ADDR in SMM AS + * so we could set SMI entry point there */ + smm->codeentry = SMI_INSN; + dprintf(3, "smm_relocate: SMRAM codeentry %llx\n", smm->codeentry); + dprintf(3, "smm_relocate: SMRAM cpu.i64.smm_base %lx\n", smm->cpu.i64.smm_base); -static void -smm_relocate_and_restore(void) -{ /* init APM status port */ outb(0x01, PORT_SMI_STATUS); @@ -165,15 +166,13 @@ smm_relocate_and_restore(void) while (inb(PORT_SMI_STATUS) != 0x00) ; - /* restore original memory content */ - struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR; - struct smm_layout *smm = (void*)BUILD_SMM_ADDR; - memcpy(&initsmm->cpu, &smm->cpu, sizeof(initsmm->cpu)); - memcpy(&initsmm->codeentry, &smm->codeentry, sizeof(initsmm->codeentry)); - - // Setup code entry point. - smm->codeentry = SMI_INSN; wbinvd(); + + dprintf(3, "smm_relocate: after relocaten\n"); + dprintf(3, "smm_relocate: RAM codeentry %llx\n", initsmm->codeentry); + dprintf(3, "smm_relocate: RAM cpu.i64.smm_base %lx\n", initsmm->cpu.i64.smm_base); + dprintf(3, "smm_relocate: SMRAM codeentry %llx\n", smm->codeentry); + dprintf(3, "smm_relocate: SMRAM cpu.i64.smm_base %lx\n", smm->cpu.i64.smm_base); } // This code is hardcoded for PIIX4 Power Management device. @@ -187,8 +186,6 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf) /* enable the SMM memory window */ pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48); - smm_save_and_copy(); - /* enable SMI generation when writing to the APMC register */ pci_config_writel(isabdf, PIIX_DEVACTB, value | PIIX_DEVACTB_APMC_EN); @@ -196,7 +193,7 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf) value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL); outl(value | PIIX_PMIO_GLBCTL_SMI_EN, acpi_pm_base + PIIX_PMIO_GLBCTL); - smm_relocate_and_restore(); + smm_relocate(); /* close the SMM memory window and enable normal SMM */ pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08); @@ -213,8 +210,6 @@ void ich9_lpc_apmc_smm_setup(int isabdf, int mch_bdf) /* enable the SMM memory window */ pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48); - smm_save_and_copy(); - /* enable SMI generation when writing to the APMC register */ outl(value | ICH9_PMIO_SMI_EN_APMC_EN | ICH9_PMIO_SMI_EN_GLB_SMI_EN, acpi_pm_base + ICH9_PMIO_SMI_EN); @@ -224,7 +219,7 @@ void ich9_lpc_apmc_smm_setup(int isabdf, int mch_bdf) pci_config_writel(isabdf, ICH9_LPC_GEN_PMCON_1, value | ICH9_LPC_GEN_PMCON_1_SMI_LOCK); - smm_relocate_and_restore(); + smm_relocate(); /* close the SMM memory window and enable normal SMM */ pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08); -- 2.18.1