From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ft8y2boy; spf=pass (domain: linaro.org, ip: 209.85.221.65, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by groups.io with SMTP; Fri, 16 Aug 2019 10:31:38 -0700 Received: by mail-wr1-f65.google.com with SMTP id c3so2257990wrd.7 for ; Fri, 16 Aug 2019 10:31:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=A5c0fkWYsrz0exMLtG8Y50F/npYkdVuuZpbnc/f/SNU=; b=ft8y2boyyPZabGLuvnO1ObCpuFEVDtKuvd2rIyzag+rf/+u0V2BZPnsTnXGA9Y8fRQ 5UoefR76gX83sp7nTpEcZ+YfLJ4/7DyghcL5+GKgvcM81bLOoKHlKk8YO4yCB1LVodEh kDzeA/ewUe6VnmZLha5lim5A3vQCNgmxnYkzwtF+AGrg2+P3Mpbi7j/mcuMD3wiksC4T wiocSOTAipAWZD9A86LoNb+3wbk+zpgTWk8xUSQlZeJv4kaWWSl69pwVFnXgd7WiFE8+ 7USzzzCUxiAfgsfBo1VcFarF5glQVFgHoNl4lszWZgt09LzVkq/2kck9ZE4Ll7EuQSvj qucA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=A5c0fkWYsrz0exMLtG8Y50F/npYkdVuuZpbnc/f/SNU=; b=EfpKEbFrv2yZfkqXqqXIa5cr7z+MuycOqq0VVoSJBgOOUi+eQwEFD6xZOAhbkRI2Tt eOcJw3BAd8vy/v6aiznVehFIF8oCztlvQPJywg6nBNQcD8sJw+1OZZuGFd+fyjMfikAz jntBvP2GzjG1ARXr0H9s/SEfnsjRdkqaM06QWQUgG2kM+YNh7e6AxnCzs1ZpfKXnhAP1 eXSYqNmpDdZQs2pmrbVkLL25dyOHe/D8PBZwnOVbEIBtPtl+HiVojfA2rCT/Ug32IO8y vLBnuHnmeCgRa/l3l1Z7RVgjgxZoUFhfJNdMhxElG9Ps5YzFfkBuh0xGPiIpREWBGI2z wkFw== X-Gm-Message-State: APjAAAV35QNuE0fcB9uRE08MdrC4jSHo+exhK1Lh8kenlHwSRWvcm1ay xfAOl4Rdh0KtlGALr19+i552yg== X-Google-Smtp-Source: APXvYqzEDYrETFD9sFN61dIvP9MUn8b3Lr+izhD/oksMrqmYK+DyQ8ei4cyQ0nIODnR3sSx69FKjcQ== X-Received: by 2002:a5d:568e:: with SMTP id f14mr11938538wrv.167.1565976696116; Fri, 16 Aug 2019 10:31:36 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a17sm6409857wmm.47.2019.08.16.10.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2019 10:31:35 -0700 (PDT) Date: Fri, 16 Aug 2019 18:31:33 +0100 From: "Leif Lindholm" To: Marcin Wojtas Cc: devel@edk2.groups.io, ard.biesheuvel@linaro.org, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: Re: [edk2-platforms: PATCH v2 04/10] Marvell/Cn9130Db: Introduce board support Message-ID: <20190816173133.GW29255@bivouac.eciton.net> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> <1565837654-13258-5-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1565837654-13258-5-git-send-email-mw@semihalf.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Aug 15, 2019 at 04:54:08AM +0200, Marcin Wojtas wrote: > This patch introduces all necessary components required > for building EDK2 firmware for CN9130-DB setup A. > Because the board is modular and can be extended to support > also CN9131 and CN9132 SoC variants, extract common part into > .dsc.inc file, which will be included by them. > > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 +++++++++++++++ > Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 46 +++++++ > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 ++++ > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 +++++ > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 19 +++ > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++++++++++++++ > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 144 ++++++++++++++++++++ > Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 18 +++ > 8 files changed, 526 insertions(+) > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > > diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > new file mode 100644 > index 0000000..33fb7cc > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > @@ -0,0 +1,107 @@ > +## @file > +# Component description file for the CN9130 Development Board (variant A) > +# > +# Copyright (c) 2019 Marvell International Ltd.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +################################################################################ > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +################################################################################ > +[PcdsFixedAtBuild.common] > + # CP115 count > + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 > + > + # MPP > + gMarvellTokenSpaceGuid.PcdMppChipCount|2 > + > + # APN807 MPP > + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 > + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 > + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } > + > + # CP115 #0 MPP > + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 > + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 > + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } > + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + > + # I2C > + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } > + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } > + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } > + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 > + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 > + > + # SPI > + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 > + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 > + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 > + > + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 > + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 > + > + # ComPhy > + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } > + # ComPhy0 > + # 0: PCIE0 5 Gbps > + # 1: PCIE0 5 Gbps > + # 2: PCIE0 5 Gbps > + # 3: PCIE0 5 Gbps > + # 4: SFI 10.31 Gbps > + # 5: SATA1 5 Gbps > + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} > + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } > + > + # UtmiPhy > + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } > + > + # MDIO > + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } > + > + # PHY > + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } > + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE > + > + # NET > + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) } > + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) } > + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } > + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } > + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } > + > + # NonDiscoverableDevices > + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } > + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } > + > + # PCIE > + gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 > + > + # RTC > + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 > + > + # SoC Configuration Space > + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 > + > + # Variable store > + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE > diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > new file mode 100644 > index 0000000..d77785d > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > @@ -0,0 +1,46 @@ > +## @file > +# Component description file for the CN9130 Development Board (variant A) > +# > +# Copyright (c) 2019 Marvell International Ltd.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +################################################################################ > +# > +# Defines Section - statements that will be processed to create a Makefile. > +# > +################################################################################ > +[Defines] > + PLATFORM_NAME = Cn9130DbA I'll mention in here, but could just as well mention it at the point where you add Cn9131 - I think it would be better to always mandate setting the command line option. Otherwise you risk building the wrong platform based on a typo, and I would prefer for the build to fail in that case. > + PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7 > + PLATFORM_VERSION = 0.1 > + DSC_SPECIFICATION = 0x0001000B > + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) > + SUPPORTED_ARCHITECTURES = AARCH64|ARM > + BUILD_TARGETS = DEBUG|RELEASE|NOOPT > + SKUID_IDENTIFIER = DEFAULT > + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > + BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > + > + # > + # Network definition > + # > + DEFINE NETWORK_IP6_ENABLE = FALSE > + DEFINE NETWORK_TLS_ENABLE = FALSE > + DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE > + DEFINE NETWORK_ISCSI_ENABLE = FALSE > + > +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > +!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > + > +[Components.common] > + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf > + > +[Components.AARCH64] > + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf > + > +[LibraryClasses.common] > + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf > + NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf > diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf > new file mode 100644 > index 0000000..dfbdc84 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf > @@ -0,0 +1,29 @@ > +## @file > +# > +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = Cn9130DbABoardDescLib > + FILE_GUID = d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmadaBoardDescLib > + > +[Sources] > + Cn9130DbABoardDescLib.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Marvell/Marvell.dec > + > +[LibraryClasses] > + DebugLib > + IoLib > diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf > new file mode 100644 > index 0000000..f7cfb36 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf > @@ -0,0 +1,37 @@ > +## @file > +# > +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = Cn9130DbANonDiscoverableInitLib > + FILE_GUID = 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = NonDiscoverableInitLib > + > +[Sources] > + NonDiscoverableInitLib.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Silicon/Marvell/Marvell.dec > + > +[LibraryClasses] > + DebugLib > + IoLib > + MvGpioLib > + > +[Protocols] > + gEmbeddedGpioProtocolGuid > + > +[Depex] > + gMarvellPlatformInitCompleteProtocolGuid > diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > new file mode 100644 > index 0000000..2533c35 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > @@ -0,0 +1,19 @@ > +/** > +* > +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > +#ifndef __NON_DISCOVERABLE_INIT_LIB_H__ > +#define __NON_DISCOVERABLE_INIT_LIB_H__ No leading __ for include guards. / Leif > + > +#define CN9130_DB_IO_EXPANDER0 0 > +#define CN9130_DB_VBUS0_PIN 0 > +#define CN9130_DB_VBUS0_LIMIT_PIN 4 > +#define CN9130_DB_VBUS1_PIN 1 > +#define CN9130_DB_VBUS1_LIMIT_PIN 5 > +#define CN9130_DB_SDMMC_VCC_PIN 14 > +#define CN9130_DB_SDMMC_VCCQ_PIN 15 > + > +#endif > diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c > new file mode 100644 > index 0000000..2b46d14 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c > @@ -0,0 +1,126 @@ > +/** > +* > +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +// > +// GPIO Expander > +// > +STATIC MV_GPIO_EXPANDER mGpioExpander = { > + PCA9555_ID, > + 0x21, > + 0x0, > +}; > + > + > +EFI_STATUS > +EFIAPI > +ArmadaBoardGpioExpanderGet ( > + IN OUT MV_GPIO_EXPANDER **GpioExpanders, > + IN OUT UINTN *GpioExpanderCount > + ) > +{ > + *GpioExpanderCount = 1; > + *GpioExpanders = &mGpioExpander; > + > + return EFI_SUCCESS; > +} > + > +// > +// PCIE > +// > +STATIC > +MV_PCIE_CONTROLLER mPcieController[] = { > + { /* PCIE0 @0xF2640000 */ > + .PcieDbiAddress = 0xF2600000, > + .ConfigSpaceAddress = 0xD0000000, > + .HaveResetGpio = FALSE, > + .PcieResetGpio = { 0 }, > + .PcieBusMin = 0, > + .PcieBusMax = 0xFE, > + .PcieIoTranslation = 0xDFF00000, > + .PcieIoWinBase = 0x0, > + .PcieIoWinSize = 0x10000, > + .PcieMmio32Translation = 0, > + .PcieMmio32WinBase = 0xC0000000, > + .PcieMmio32WinSize = 0x10000000, > + .PcieMmio64Translation = 0, > + .PcieMmio64WinBase = MAX_UINT64, > + .PcieMmio64WinSize = 0, > + } > +}; > + > +/** > + Return the number and description of PCIE controllers used on the platform. > + > + @param[in out] **PcieControllers Array containing PCIE controllers' > + description. > + @param[in out] *PcieControllerCount Amount of used PCIE controllers. > + > + @retval EFI_SUCCESS The data were obtained successfully. > + @retval other Return error status. > + > +**/ > +EFI_STATUS > +EFIAPI > +ArmadaBoardPcieControllerGet ( > + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, > + IN OUT UINTN *PcieControllerCount > + ) > +{ > + *PcieControllers = mPcieController; > + *PcieControllerCount = ARRAY_SIZE (mPcieController); > + > + return EFI_SUCCESS; > +} > + > +// > +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib > +// > +STATIC > +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = { > + { /* eMMC 0xF06E0000 */ > + 0, /* SOC will be filled by MvBoardDescDxe */ > + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ > + FALSE, /* Xenon1v8Enabled */ > + TRUE, /* Xenon8BitBusEnabled */ > + FALSE, /* XenonSlowModeEnabled */ > + 0x40, /* XenonTuningStepDivisor */ > + EmbeddedSlot /* SlotType */ > + }, > + { /* SD/MMC 0xF2780000 */ > + 0, /* SOC will be filled by MvBoardDescDxe */ > + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ > + FALSE, /* Xenon1v8Enabled */ > + FALSE, /* Xenon8BitBusEnabled */ > + FALSE, /* XenonSlowModeEnabled */ > + 0x19, /* XenonTuningStepDivisor */ > + EmbeddedSlot /* SlotType */ > + } > +}; > + > +EFI_STATUS > +EFIAPI > +ArmadaBoardDescSdMmcGet ( > + OUT UINTN *SdMmcDevCount, > + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc > + ) > +{ > + *SdMmcDesc = mSdMmcDescTemplate; > + *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > new file mode 100644 > index 0000000..598c649 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > @@ -0,0 +1,144 @@ > +/** > +* > +* Copyright (c) 2017, Linaro Ltd. All rights reserved. > +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "NonDiscoverableInitLib.h" > + > +STATIC > +EFI_STATUS > +EFIAPI > +ConfigurePins ( > + IN CONST MV_GPIO_PIN *VbusPin, > + IN UINTN PinCount, > + IN MV_GPIO_DRIVER_TYPE DriverType > + ) > +{ > + EMBEDDED_GPIO_MODE Mode; > + EMBEDDED_GPIO_PIN Gpio; > + EMBEDDED_GPIO *GpioProtocol; > + EFI_STATUS Status; > + UINTN Index; > + > + Status = MvGpioGetProtocol (DriverType, &GpioProtocol); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__)); > + return Status; > + } > + > + for (Index = 0; Index < PinCount; Index++) { > + Mode = VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0; > + Gpio = GPIO (VbusPin->ControllerId, VbusPin->PinNumber); > + GpioProtocol->Set (GpioProtocol, Gpio, Mode); > + VbusPin++; > + } > + > + return EFI_SUCCESS; > +} > + > +STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] = { > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_VBUS0_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_VBUS0_LIMIT_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_VBUS1_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_VBUS1_LIMIT_PIN, > + TRUE, > + }, > +}; > + > +STATIC > +EFI_STATUS > +EFIAPI > +Cp0XhciInit ( > + IN NON_DISCOVERABLE_DEVICE *This > + ) > +{ > + return ConfigurePins (mCp0XhciVbusPins, > + ARRAY_SIZE (mCp0XhciVbusPins), > + MV_GPIO_DRIVER_TYPE_PCA95XX); > +} > + > +STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = { > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_SDMMC_VCC_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_PCA95XX, > + CN9130_DB_IO_EXPANDER0, > + CN9130_DB_SDMMC_VCCQ_PIN, > + FALSE, > + }, > +}; > + > +STATIC > +EFI_STATUS > +EFIAPI > +Cp0SdMmcInit ( > + IN NON_DISCOVERABLE_DEVICE *This > + ) > +{ > + return ConfigurePins (mCp0SdMmcPins, > + ARRAY_SIZE (mCp0SdMmcPins), > + MV_GPIO_DRIVER_TYPE_PCA95XX); > +} > + > +NON_DISCOVERABLE_DEVICE_INIT > +EFIAPI > +NonDiscoverableDeviceInitializerGet ( > + IN NON_DISCOVERABLE_DEVICE_TYPE Type, > + IN UINTN Index > + ) > +{ > + if (Type == NonDiscoverableDeviceTypeXhci) { > + switch (Index) { > + case 0: > + case 1: > + return Cp0XhciInit; > + } > + } > + > + if (Type == NonDiscoverableDeviceTypeSdhci) { > + switch (Index) { > + case 1: > + return Cp0SdMmcInit; > + } > + } > + > + return NULL; > +} > diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > new file mode 100644 > index 0000000..0c321d1 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > @@ -0,0 +1,18 @@ > +# > +# Copyright (C) 2019 Marvell International Ltd. and its affiliates > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > +# Per-board additional content of the DXE phase firmware volume > + > + INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf > + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf > + > + # DTB > + INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf > + > +!if $(ARCH) == AARCH64 > + # ACPI support > + INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf > +!endif > -- > 2.7.4 >