From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: michael.a.kubacki@intel.com) Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319372" Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:59 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add library instances Date: Fri, 16 Aug 2019 17:16:00 -0700 Message-Id: <20190817001603.30632-35-michael.a.kubacki@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083 WhiskeylakeURvp library instances. * BaseFuncLib - Board-specific VBT update routines. * BaseGpioCheckConflictLib - Identifies GPIO pad conflicts. * BaseGpioCheckConflictLibNull - NULL library instance. * BasePlatformHookLib - Serial port initialization support. * DxePolicyBoardConfigLib - Board-specific silicon policy configuration in DXE. * PeiBoardInitPostMemLib - PEI post-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiPlatformHookLib - PEI board instance-specifc GPIO init. * PeiPolicyBoardConfigLib - Board instance-specific policy init in PEI. * SmmBoardAcpiEnableLib - Board instance-specific SMM ACPI enable support. * SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/BaseFuncLib.inf | 33 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 116 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 202 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 296 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf | 44 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf | 94 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf | 70 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h | 18 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardInitLib.h | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h | 90 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h | 225 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h | 284 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h | 59 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PchHdaVerbTables.h | 3014 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/Gop.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c | 137 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c | 156 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 82 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.c | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c | 27 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c | 398 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c | 282 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 106 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c | 63 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c | 432 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c | 636 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpHsioPtssTables.c | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c | 299 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c | 27 + 55 files changed, 8499 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/BaseFuncLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/BaseFuncLib.inf new file mode 100644 index 0000000000..0ccc73b99f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/BaseFuncLib.inf @@ -0,0 +1,33 @@ +## @file +# Component information file for Board Functions Library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BaseBoardFuncInitLib + FILE_GUID = 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL|PEIM + +[LibraryClasses] + BaseLib + DebugLib + +[Packages] + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + Gop.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf new file mode 100644 index 0000000000..5014faf664 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf @@ -0,0 +1,35 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BaseGpioCheckConflictLib + FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLib.c + +[Guids] + gGpioCheckConflictHobGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf new file mode 100644 index 0000000000..d9b242b3fc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf @@ -0,0 +1,32 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BaseGpioCheckConflictLibNull + FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLibNull.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..143bb89c63 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,53 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BasePlatformHookLib + FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PlatformHookLib +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciSegmentLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSUMES + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..8ad32a55dc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,50 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmBoardAcpiEnableLib + FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmWhiskeylakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..27001c3b7f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,50 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmWhiskeylakeURvpMultiBoardAcpiSupportLib + FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL + CONSTRUCTOR = SmmWhiskeylakeURvpMultiBoardAcpiSupportLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + PmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmWhiskeylakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmMultiBoardAcpiSupportLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..a8c4869e96 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,53 @@ +## @file +# Component information file for WhiskeylakeURvpInitLib in PEI post memory phase. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardPostMemInitLib + FILE_GUID = 7fcc3900-d38d-419f-826b-72481e8b5509 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + HdaVerbTableLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPostMemLib.c + PeiBoardInitPostMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..9361c3df3e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,116 @@ +## @file +# Component information file for PEI WhiskeylakeURvp Board Init Pre-Mem Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardInitPreMemLib + FILE_GUID = ec3675bc-1470-417d-826e-37378140213d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpDetect.c + PeiWhiskeylakeURvpInitPreMemLib.c + WhiskeylakeURvpHsioPtssTables.c + PeiBoardInitPreMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..4831735dc5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,202 @@ +## @file +# Component information file for WhiskeylakeURvpInitLib in PEI post memory phase. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiWhiskeylakeURvpMultiBoardInitLib + FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiWhiskeylakeURvpMultiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + MultiBoardInitSupportLib + HdaVerbTableLib + PeiPlatformHookLib + PeiPolicyInitLib + PchInfoLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPostMemLib.c + PeiMultiBoardInitPostMemLib.c + BoardFunc.c + BoardFuncInit.c + +[FixedPcd] + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + #=========================================================== + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + # Board Init Table List + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # WWAN Full Card Power Off and reset pins + gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev + gBoardModuleTokenSpaceGuid.PcdRootPortFunc + gBoardModuleTokenSpaceGuid.PcdRootPortIndex + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 + gBoardModuleTokenSpaceGuid.PcdPcieClock1 + gBoardModuleTokenSpaceGuid.PcdPcieClock2 + gBoardModuleTokenSpaceGuid.PcdPcieClock3 + gBoardModuleTokenSpaceGuid.PcdPcieClock4 + gBoardModuleTokenSpaceGuid.PcdPcieClock5 + gBoardModuleTokenSpaceGuid.PcdPcieClock6 + gBoardModuleTokenSpaceGuid.PcdPcieClock7 + gBoardModuleTokenSpaceGuid.PcdPcieClock8 + gBoardModuleTokenSpaceGuid.PcdPcieClock9 + gBoardModuleTokenSpaceGuid.PcdPcieClock10 + gBoardModuleTokenSpaceGuid.PcdPcieClock11 + gBoardModuleTokenSpaceGuid.PcdPcieClock12 + gBoardModuleTokenSpaceGuid.PcdPcieClock13 + gBoardModuleTokenSpaceGuid.PcdPcieClock14 + gBoardModuleTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + + + gBoardModuleTokenSpaceGuid.PcdSpdPresent + gBoardModuleTokenSpaceGuid.PcdBoardRev + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable + # TPM interrupt + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + +[Guids] + gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES + gCnlPchLpChipsetInitTableDxGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..6affc3180e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,296 @@ +## @file +# Component information file for PEI WhiskeylakeURvp Board Init Pre-Mem Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiWhiskeylakeURvpMultiBoardInitPreMemLib + FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiWhiskeylakeURvpMultiBoardInitPreMemLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + MultiBoardInitSupportLib + StallPpiLib + PchResetLib + PeiPlatformHookLib + PlatformHookLib + PeiPolicyInitLib + OcWdtLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPreMemLib.c + WhiskeylakeURvpHsioPtssTables.c + PeiMultiBoardInitPreMemLib.c + PeiWhiskeylakeURvpDetect.c + BoardSaInitPreMemLib.c + BoardPchInitPreMemLib.c + BoardFuncInitPreMem.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES + gEfiPeiResetPpiGuid ## PRODUCES + +[Guids] + gPchGeneralPreMemConfigGuid ## CONSUMES + gTcoWdtHobGuid ## CONSUMES + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + #=========================================================== + # Board Init Table List + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # WWAN Full Card Power Off and reset pins + gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev + gBoardModuleTokenSpaceGuid.PcdRootPortFunc + gBoardModuleTokenSpaceGuid.PcdRootPortIndex + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport + + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 + gBoardModuleTokenSpaceGuid.PcdPcieClock1 + gBoardModuleTokenSpaceGuid.PcdPcieClock2 + gBoardModuleTokenSpaceGuid.PcdPcieClock3 + gBoardModuleTokenSpaceGuid.PcdPcieClock4 + gBoardModuleTokenSpaceGuid.PcdPcieClock5 + gBoardModuleTokenSpaceGuid.PcdPcieClock6 + gBoardModuleTokenSpaceGuid.PcdPcieClock7 + gBoardModuleTokenSpaceGuid.PcdPcieClock8 + gBoardModuleTokenSpaceGuid.PcdPcieClock9 + gBoardModuleTokenSpaceGuid.PcdPcieClock10 + gBoardModuleTokenSpaceGuid.PcdPcieClock11 + gBoardModuleTokenSpaceGuid.PcdPcieClock12 + gBoardModuleTokenSpaceGuid.PcdPcieClock13 + gBoardModuleTokenSpaceGuid.PcdPcieClock14 + gBoardModuleTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + + + gBoardModuleTokenSpaceGuid.PcdSpdPresent + gBoardModuleTokenSpaceGuid.PcdBoardRev + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable + gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdMchMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf new file mode 100644 index 0000000000..2c9af5b9a3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf @@ -0,0 +1,44 @@ +## @file +# Module Information file for DxePolicyBoardConfigLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxePolicyBoardConfigLib + FILE_GUID = 17836E9F-7188-4640-80A3-B4441585FFE9 + VERSION_STRING = 1.0 + MODULE_TYPE = DXE_DRIVER + LIBRARY_CLASS = DxePolicyUpdateLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + DxeSaPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + BaseMemoryLib + PcdLib + DebugLib + HobLib + ConfigBlockLib + +[Guids] + gMemoryDxeConfigGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..079fb70ecb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf @@ -0,0 +1,94 @@ +## @file +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiPlatformHookLib + FILE_GUID = AD901798-B0DA-4B20-B90C-283F886E76D0 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC + +[LibraryClasses] + DebugLib + BaseMemoryLib + IoLib + HobLib + PcdLib + TimerLib + PchCycleDecodingLib + GpioLib + CpuPlatformLib + PeiServicesLib + ConfigBlockLib + PeiSaPolicyLib + GpioExpanderLib + PmcLib + PchPcrLib + PciSegmentLib + GpioCheckConflictLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable + gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround + +[Sources] + PeiPlatformHooklib.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + +[Guids] + gSaDataHobGuid ## CONSUMES + gEfiGlobalVariableGuid ## CONSUMES + gGpioCheckConflictHobGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf new file mode 100644 index 0000000000..65e66ccb62 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf @@ -0,0 +1,70 @@ +## @file +# Module Information file for PeiPolicyBoardConfigLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiPolicyBoardConfigLib + FILE_GUID = B1E959E3-9DCA-4D6F-938C-420C3BF5D820 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC + +[Sources] + PeiCpuPolicyBoardConfigPreMem.c + PeiCpuPolicyBoardConfig.c + PeiMePolicyBoardConfigPreMem.c + PeiMePolicyBoardConfig.c + PeiPchPolicyBoardConfigPreMem.c + PeiPchPolicyBoardConfig.c + PeiSaPolicyBoardConfigPreMem.c + PeiSaPolicyBoardConfig.c + PeiSiPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + PcdLib + DebugLib + HobLib + ConfigBlockLib + IoLib + BaseCryptLib + BaseMemoryLib + +[Guids] + gCpuSecurityPreMemConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gEfiTpmDeviceInstanceTpm20DtpmGuid + gEfiTpmDeviceInstanceTpm12Guid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h new file mode 100644 index 0000000000..eca492e72d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h @@ -0,0 +1,18 @@ +/** @file + Header file for Board Hook function intance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_FUNC_H_ +#define _BOARD_FUNC_H_ + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ); + +#endif // _BOARD_FUNC_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardInitLib.h new file mode 100644 index 0000000000..5435b4a6e3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardInitLib.h @@ -0,0 +1,20 @@ +/** @file + Header file for board Init function for Post Memory Init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_LIB_H_ +#define _PEI_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include + +#endif // _PEI_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h new file mode 100644 index 0000000000..41c798a082 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h @@ -0,0 +1,90 @@ +/** @file + PEI Boards Configurations for PreMem phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_ +#define _BOARD_SA_CONFIG_PRE_MEM_H_ + +#include +#include // for MRC Configuration +#include // for PCIE RTD3 GPIO +#include // for GPIO definition +#include +#include // for Root Port number +#include // for Root Port number + +// +// The following section contains board-specific CMD/CTL/CLK and DQ/DQS mapping, needed for LPDDR3/LPDDR4 +// + +// +// DQByteMap[0] - ClkDQByteMap: +// If clock is per rank, program to [0xFF, 0xFF] +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] +// If clock is shared by 2 ranks but does not go to all bytes, +// Entry[i] defines which DQ bytes Group i services +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB +// For DDR, DQByteMap[3:1] = [0xFF, 0] +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank +// Variable only exists to make the code easier to use +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref +// Variable only exists to make the code easier to use +// +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for WHL RVP3, WHL SDS - used by WHL/WHL MRC +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapWhlUDdr4Rvp[2][6][2] = { + // Channel 0: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4] + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4] + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + }, + // Channel 1: + { + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4] + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4] + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + } +}; + +// +// DQS byte swizzling between CPU and DRAM +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramWhlUDdr4Rvp[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 +}; + +// +// DQS byte swizzling between CPU and DRAM +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqsMapCpu2DramWhlUmDvp[2][8] = { + { 0, 3, 1, 2, 7, 5, 6, 4 }, // Channel 0 + { 0, 2, 1, 3, 6, 4, 7, 5 } // Channel 1 +}; + +// +// Reference RCOMP resistors on motherboard +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorCflUDdr4Interposer[SA_MRC_MAX_RCOMP] = { 121, 81, 100 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetWhlUDdr4Interposer[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20, 26 }; + +#endif // _BOARD_SA_CONFIG_PRE_MEM_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h new file mode 100644 index 0000000000..a943d5bd04 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h @@ -0,0 +1,225 @@ +/** @file + GPIO definition table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_TABLE_DEFAULT_H_ +#define _GPIO_TABLE_DEFAULT_H_ + +#include +#include +#include + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +// +// CNL U DRR4 Board GPIO table configuration is used as default +// + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] = +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPPC_A6_SERIRQ + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL_SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPKR_PD_N + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WFCAM_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SD_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //ACCEL_INT + //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //ALS_INT + //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //HUMAN_PRESENCE_INT + //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //HALL_SENSOR_INT + //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_WAKE + //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock } }, //BT_UART_WAKE + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock} }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_PWR_EN + //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //NFC_DFU + { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock } }, //FPS_INT_N + { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock} }, //FPS_RESET_N + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}}, //EC_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone }}, //WIFI_RF_KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K } }, //CODEC_INT_N + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //TBT_FORCE_PWR + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //NFC_RST_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWREN + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL_RST_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //NFC_INT_N + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_0 + {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO2 + {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Reserved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone}}, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_DATA + //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F0_COEX3 + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SATA_HDD_PWREN + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_CLK_EN + //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB + //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD + //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD + //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB + {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_MFUART2_RXD + {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //BIOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpd20K }}, //GPP_G_7_SD3_WP + //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_0_SSP2_SCLK + //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_1_SSP2_SFRM + //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_2_SSP2_TXD + //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_RECOVERY + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IRIS_STROBE + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //UF_CAM_PRIVACY_LED + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL1 + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT_WF_CAM + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H21 + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_CAM_RST + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd20K }}, // 20K PD for PECI +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemDefault[] = +{ + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table +}; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h new file mode 100644 index 0000000000..86b7cb3717 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h @@ -0,0 +1,284 @@ +/** @file + GPIO definition table for WhiskeyLake U Ddr4 RVP + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ +#define _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ + +#include +#include +#include + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] = +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPPC_A6_SERIRQ + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL_SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPKR_PD_N + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K, GpioPadUnlock }}, //WFCAM_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SD_PWREN + //A18-A23 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_A18, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //ACCEL_INT + {GPIO_CNL_LP_GPP_A19, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //ALS_INT + {GPIO_CNL_LP_GPP_A20, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //HUMAN_PRESENCE_INT + {GPIO_CNL_LP_GPP_A21, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //HALL_SENSOR_INT + {GPIO_CNL_LP_GPP_A22, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //IVCAM_WAKE + {GPIO_CNL_LP_GPP_A23, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, GpioPadUnlock } }, //BT_UART_WAKE + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioOutputStateUnlock} }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_PWR_EN + //B15 -Unused pin -> Under GPIO table for GPIO Termination - Input sensing disable + {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //Former NFC_DFU + {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock } }, //FPS_INT_N + {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock} }, //FPS_RESET_N + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone, GpioPadUnlock }}, //EC_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioOutputStateUnlock }}, //WIFI_RF_KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi , GpioDirIn , GpioOutDefault , GpioIntLevel | GpioIntApic , GpioPlatformReset, GpioTermWpu20K } }, //CODEC_INT_N + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //TBT_FORCE_PWR + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N + //move to premem phase for early power turn on + // {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N + // {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N + // {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N + // {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + + //Only clear Reset pins in Post-Mem + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N + //{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Former NFC_RST_N + //{GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWREN + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL_RST_N + //(Not used) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Former NFC_INT_N + //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_0 + //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO2 + //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Reserved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone, GpioPadUnlock}}, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_DATA + //F0- unused pin-Input Sensing disable F4-F7 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //GPP_F0_COEX3 + //{GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //SATA_HDD_PWREN + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K, GpioPadUnlock }}, //WF_CLK_EN + {GPIO_CNL_LP_GPP_F4, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_BRI_DT_UART0_RTSB + {GPIO_CNL_LP_GPP_F5, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_BRI_RSP_UART0_RXD + {GPIO_CNL_LP_GPP_F6, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_RGI_DT_UART0_TXD + {GPIO_CNL_LP_GPP_F7, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_RGI_RSP_UART0_CTSB + //{GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_MFUART2_RXD + //{GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K}}, //BIOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpd20K }}, //GPP_G_7_SD3_WP + //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_H0, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_H_0_SSP2_SCLK + {GPIO_CNL_LP_GPP_H1, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_H_1_SSP2_SFRM + {GPIO_CNL_LP_GPP_H2, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_H_2_SSP2_TXD + {GPIO_CNL_LP_GPP_H3, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_RECOVERY + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IRIS_STROBE + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //UF_CAM_PRIVACY_LED + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL1 + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT_WF_CAM + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H21 + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //WF_CAM_RST + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd20K }}, // 20K PD for PECI +}; + +static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = { + // Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, Term, + // WiGig start + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //M.2_WIGIG_RF_KILL_N / IVCAM_WAKE_N on CNL U + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutHigh, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIGIG_PEWAKE_R_N / WF_CAM_RST on CNL U + //WiGig end + // Camera start + {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / RC Control on CNL U + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / IRIS_STROBE on CNL U + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / UF_CAM_PRIVACY_LED on CNL U + {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / RC Control on CNL U + // Camera end + // Touch start + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + // Touch end + {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SMC_RUNTIME_SCI_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock } }, //SPI_TPM_INT_N // Unused start + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K }}, //Unused so disabled / WF_CLK_EN on CNL U + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / Not used on CNL U + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }} //Unused so disabled / Not used on CNL U + // Unused end +}; + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = { + // Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, Term, + // WiGig start + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //M.2_WIGIG_RF_KILL_N / IVCAM_WAKE_N on CNL U + // WiGig end + // Camera start + {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / RC Control on CNL U + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / IRIS_STROBE on CNL U + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / UF_CAM_PRIVACY_LED on CNL U + {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //Camera / RC Control on CNL U + // Camera end + // Touch start + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + // Touch end + {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SMC_RUNTIME_SCI_N + // TBT start + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN + // TBT end + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + // Unused start + {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K }} //Unused so disabled / WF_CLK_EN on CNL U + // Unused end +}; + + +#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h new file mode 100644 index 0000000000..01a6599564 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h @@ -0,0 +1,59 @@ +/** @file + GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ +#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ + +#include +#include +#include + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] = +{ + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N +}; + +static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] = +{ + // do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume. + //{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N +}; + + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] = +{ + // Turn on WWAN power and de-assert reset pins by default + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}}, //WWAN_WAKE_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_FCP_OFF + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N +}; + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] = +{ + // Assert reset pins and then turn off WWAN power + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}}, //WWAN_WAKE_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_FCP_OFF + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N +}; + +#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PchHdaVerbTables.h new file mode 100644 index 0000000000..0d26e8ad7a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PchHdaVerbTables.h @@ -0,0 +1,3014 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_VERB_TABLES_H_ +#define _PCH_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: CFL Display Audio Codec + // Revision ID = 0xFF + // Codec Vendor: 0x8086280B + // + 0x8086, 0x280B, + 0xFF, 0xFF, + // + // Display Audio Verb Table + // + // For GEN9, the Vendor Node ID is 08h + // Port to be exposed to the inbox driver in the vanilla mode: PORT C - BIT[7:6] = 01b + 0x00878140, + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + // Disable the third converter and third Pin (NID 08h) + 0x00878140 +); + +// +//codecs verb tables +// +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) + // Revision ID = 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40622005 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D20, + 0x01D71E62, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + // + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +); // HdaVerbTableAlc700 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC701) + // Revision ID = 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0701 + // + 0x10EC, 0x0701, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC701 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40610041 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC1124 + 0x00172024, + 0x00172111, + 0x001722EC, + 0x00172310, + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C41, + 0x01D71D00, + 0x01D71E61, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B +); // HdaVerbTableAlc701 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC274) + // Revision ID = 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0274 + // + 0x10EC, 0x0274, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC274 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 + //The number of verb command block : 16 + + // NID 0x12 : 0x40000000 + // NID 0x13 : 0x411111F0 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x411111F0 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11020 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40451B05 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211010 + + + //===== HDA Codec Subsystem ID Verb-table ===== + //,DA Codec Subsystem ID : 0x10EC10F6 + 0x001720F6, + 0x00172110, + 0x001722EC, + 0x00172310, + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + //Pin widget 0x14 - NPC + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S_OUT2 + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S_OUT1 + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + //Pin widget 0x18 - I2S_IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D1B, + 0x01D71E45, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C10, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205006F, + 0x02042C0B, + //Widget node 0x20 - 1 : + 0x02050035, + 0x02048968, + 0x05B50001, + 0x05B48540, + //Widget node 0x20 - 2 : + 0x05850000, + 0x05843888, + 0x05850000, + 0x05843888, + //Widget node 0x20 - 3 : + 0x0205004A, + 0x0204201B, + 0x0205004A, + 0x0204201B +); //HdaVerbTableAlc274 + +// +// CFL S Audio Codec +// +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) CFL S RVP + // Revision ID = 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C + //The number of verb command block : 17 + + // NID 0x12 : 0x90A60130 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x03011010 + // NID 0x17 : 0x90170120 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A1103E + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x03A11040 + // NID 0x1D : 0x40600001 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x0421102F + // NID 0x29 : 0x411111F0 + + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC112C + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C30, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671C10, + 0x01671D10, + 0x01671E01, + 0x01671F03, + //Pin widget 0x17 - I2S-OUT + 0x01771C20, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C3E, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71C40, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F03, + //Pin widget 0x1D - PC-BEEP + 0x01D71C01, + 0x01D71D00, + 0x01D71E60, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) + 0x0205006B, + 0x02044260, + 0x0205006B, + 0x02044260, + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent control + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 4 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC1305 EQ setting + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x02042213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); + + +// +// WHL codecs verb tables +// +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) WHL RVP + // Revision ID = 0xff + // Codec Verb Table for WHL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x02A19040 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40638029 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x02211020 + // NID 0x29 : 0x411111F0 + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C29, + 0x01D71D80, + 0x01D71E63, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 bypass DAC02 DRE(NID5B bit14) + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + + //Widget node 0x20 -2: + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + + //Widget node 0x20 - 3 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x0204E213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204422E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); // WhlHdaVerbTableAlc700 + +#endif // _PCH_HDA_VERB_TABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h new file mode 100644 index 0000000000..89c780cc0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ +#define _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern const UINT8 mDqByteMapSklRvp3[2][6][2]; +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; +extern const UINT8 mSkylakeRvp3Spd110[]; +extern const UINT16 mSkylakeRvp3Spd110Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size; + +extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[]; +extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize; + +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; +extern UINT16 mGpioTableIoExpanderSize; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[]; +extern UINT16 mGpioTableLpDdr3Rvp3Size; + +#endif // _PEI_Whiskeylake_RVP3_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h new file mode 100644 index 0000000000..a6d48e906d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h @@ -0,0 +1,20 @@ +/** @file + Header file for DxePolicyBoardConfig library instance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_POLICY_BOARD_CONFIG_H_ +#define _DXE_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include +#include + + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h new file mode 100644 index 0000000000..03c27f2a41 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h @@ -0,0 +1,23 @@ +/** @file + Header file for PeiPolicyBoardConfig library instance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_BOARD_CONFIG_H_ +#define _PEI_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/Gop.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/Gop.c new file mode 100644 index 0000000000..01b3df984a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib/Gop.c @@ -0,0 +1,41 @@ +/** @file + Others Board's PCD function hook. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +// +// Null function for nothing GOP VBT update. +// +VOID +EFIAPI +GopVbtSpecificUpdateNull ( + IN CHILD_STRUCT **ChildStructPtr + ) +{ + return; +} + +// +// for CFL U DDR4 +// +VOID +EFIAPI +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +) +{ + ChildStructPtr[1]->DeviceClass = DISPLAY_PORT_ONLY; + ChildStructPtr[1]->DVOPort = DISPLAY_PORT_B; + ChildStructPtr[2]->DeviceClass = DISPLAY_PORT_HDMI_DVI_COMPATIBLE; + ChildStructPtr[2]->DVOPort = DISPLAY_PORT_C; + ChildStructPtr[2]->AUX_Channel = AUX_CHANNEL_C; + ChildStructPtr[3]->DeviceClass = NO_DEVICE; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c new file mode 100644 index 0000000000..7ebf8f8fdc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c @@ -0,0 +1,137 @@ +/** @file + Implementation of BaseGpioCheckConflictLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Check Gpio PadMode conflict and report it. + + @retval none. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GpioCheckConflictHob; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT32 HobDataSize; + UINT32 GpioCount; + UINT32 GpioIndex; + GPIO_CONFIG GpioActualConfig; + + GpioCheckConflictHob = NULL; + GpioCheckConflictHobData = NULL; + + DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n")); + + // + //Use Guid to find HOB. + // + GpioCheckConflictHob = (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCheckConflictHobGuid); + if (GpioCheckConflictHob == NULL) { + DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n")); + } else { + while (GpioCheckConflictHob != NULL) { + // + // Find the Data area pointer and Data size from the Hob + // + GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DATA (GpioCheckConflictHob); + HobDataSize = GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob); + + GpioCount = HobDataSize / sizeof (GPIO_PAD_MODE_INFO); + DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount = %d\n", GpioCount)); + + // + // Probe Gpio entries in Hob and compare which are conflicted + // + for (GpioIndex = 0; GpioIndex < GpioCount ; GpioIndex++) { + GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &GpioActualConfig); + if (GpioCheckConflictHobData[GpioIndex].GpioPadMode != GpioActualConfig.PadMode) { + DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad))); + } + } + // + // Find next Hob and return the Hob pointer by the specific Hob Guid + // + GpioCheckConflictHob = GET_NEXT_HOB (GpioCheckConflictHob); + GpioCheckConflictHob = GetNextGuidHob (&gGpioCheckConflictHobGuid, GpioCheckConflictHob); + } + + DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n")); + } + + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + + @retval none. +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + + UINT32 Index; + UINT32 GpioIndex; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT16 GpioCount; + + GpioCount = 0; + GpioIndex = 0; + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n")); + + for (Index = 0; Index < GpioTableCount ; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) { + continue; + } else { + // + // Calculate how big size the Hob Data needs + // + GpioCount++; + } + } + + // + // Build a HOB tagged with a GUID for identification and returns + // the start address of GUID HOB data. + // + GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpioCheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO)); + + // + // Record Non Default Gpio entries to the Hob + // + for (Index = 0; Index < GpioTableCount; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) { + continue; + } else { + GpioCheckConflictHobData[GpioIndex].GpioPad = GpioDefinition[Index].GpioPad; + GpioCheckConflictHobData[GpioIndex].GpioPadMode = GpioDefinition[Index].GpioConfig.PadMode; + GpioIndex++; + } + } + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n")); + return; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c new file mode 100644 index 0000000000..178ce1a124 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c @@ -0,0 +1,37 @@ +/** @file + Implementation of BaseGpioCheckConflicLibNull. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Check Gpio PadMode conflict and report it. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + return; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..24c6fa6277 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -0,0 +1,156 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F + +#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55 +#define IT8628_EXIT_CONFIG 0x2 +#define IT8628_CHIPID_BYTE1 0x86 +#define IT8628_CHIPID_BYTE2 0x28 + +typedef struct { + UINT8 Register; + UINT8 Value; +} EFI_SIO_TABLE; + +// +// IT8628 +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = { + {0x023, 0x09}, // Clock Selection register + {0x007, 0x01}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select + {0x030, 0x01}, // Serial Port 1 Activate + {0x007, 0x02}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select + {0x030, 0x01} // Serial Port 2 Activate +}; + +/** + Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports +**/ +STATIC +VOID +It8628SioSerialPortInit ( + VOID + ) +{ + UINT8 ChipId0; + UINT8 ChipId1; + UINT16 LpcIoDecondeRangeSet; + UINT16 LpcIoDecoodeSet; + UINT8 Index; + UINT64 LpcBaseAddr; + + ChipId0 = 0; + ChipId1 = 0; + LpcIoDecondeRangeSet = 0; + LpcIoDecoodeSet = 0; + + // + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh. + // + LpcBaseAddr = PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + LpcIoDecondeRangeSet = (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOD); + LpcIoDecoodeSet = (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOE); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet | ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8))); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE))); + + // + // Enter MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3); + + // + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); + ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); + ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + // + // Enable Serial Port 1, Port 2 + // + if ((ChipId0 == IT8628_CHIPID_BYTE1) && (ChipId1 == IT8628_CHIPID_BYTE2)) { + for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value); + } + } + + // + // Exit MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + + return; +} + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + // Configure Sio IT8628 + It8628SioSerialPortInit (); + + return RETURN_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..e7acbda03a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,63 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return WhiskeylakeURvpBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return WhiskeylakeURvpBoardDisableAcpi (DisableSci); +} + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..978e367cda --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,82 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return WhiskeylakeURvpBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return WhiskeylakeURvpBoardDisableAcpi (DisableSci); +} + +BOARD_ACPI_ENABLE_FUNC mWhiskeylakeURvpBoardAcpiEnableFunc = { + WhiskeylakeURvpMultiBoardEnableAcpi, + WhiskeylakeURvpMultiBoardDisableAcpi, +}; + +EFI_STATUS +EFIAPI +SmmWhiskeylakeURvpMultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () == BoardIdWhiskeyLakeRvp) { + return RegisterBoardAcpiEnableFunc (&mWhiskeylakeURvpBoardAcpiEnableFunc); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..9daceaa25c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,170 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + + UINT32 OutputValue; + UINT32 SmiEn; + UINT32 SmiSts; + UINT32 ULKMC; + UINTN LpcBaseAddress; + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + // + // Get the ACPI Base Address + // + AcpiBaseAddr = PmcGetAcpiBase(); + // + // BIOS must also ensure that CF9GR is cleared and locked before handing control to the + // OS in order to prevent the host from issuing global resets and resetting ME + // + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset + // MmioWrite32 ( + // PmcBaseAddress + R_PCH_PMC_ETR3), + // PmInit); + + // + // Clear Port 80h + // + IoWrite8 (0x80, 0); + + // + // Disable SW SMI Timer and clean the status + // + SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN); + SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB); + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn); + + SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); + SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts); + + // + // Disable port 60/64 SMI trap if they are enabled + // + ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN); + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC); + + // + // Disable PM sources except power button + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN); + + // + // Clear PM status except Power Button status for RapidStart Resume + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD); + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0); + + // + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) + // + OutputValue = IoRead32 (AcpiBaseAddr + 0x38); + OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition)); + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); + + // + // Enable SCI + // + if (EnableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + // + // Get the ACPI Base Address + // + AcpiBaseAddr = PmcGetAcpiBase(); + // + // Disable SCI + // + if (DisableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c new file mode 100644 index 0000000000..97a3fae51b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c @@ -0,0 +1,40 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.c new file mode 100644 index 0000000000..7a2fed9904 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.c @@ -0,0 +1,19 @@ +/** @file + Board's PCD function hook. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c new file mode 100644 index 0000000000..5104329825 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c @@ -0,0 +1,27 @@ +/** @file + Source code for the board configuration init function in Post Memory init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include "BoardFunc.h" + +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInit ( + IN UINT16 BoardId +) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c new file mode 100644 index 0000000000..3a42a9bd03 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c @@ -0,0 +1,41 @@ +/** @file + Source code for the board configuration init function in Post Memory init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include +// +// Null function for nothing GOP VBT update. +// +VOID +GopVbtSpecificUpdateNull( + IN CHILD_STRUCT **ChildStructPtr +); +// +// for CFL U DDR4 +// +VOID +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +); +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInitPreMem ( + IN UINT16 BoardId + ) +{ + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c new file mode 100644 index 0000000000..458a73f892 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c @@ -0,0 +1,398 @@ +/** @file + Source code for the board PCH configuration Pcd init functions for Pre-Mmeory Init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include +#include +#include // for USB 20 AFE & Root Port Clk Info. +#include "GpioTableWhlUDdr4PreMem.h" +#include + +/** + Board Root Port Clock Info configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +RootPortClkInfoInit ( + IN UINT16 BoardId + ) +{ + PCD64_BLOB *Clock; + UINT32 Index; + + Clock = AllocateZeroPool (16 * sizeof (PCD64_BLOB)); + ASSERT (Clock != NULL); + if (Clock == NULL) { + return EFI_OUT_OF_RESOURCES; + } + // + // The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified + // This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board, + // the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will + // continue to draw power. To prevent this, remember to provide port-clock map for every board. + // + for (Index = 0; Index < 16; Index++) { + Clock[Index].PcieClock.ClkReqSupported = TRUE; + Clock[Index].PcieClock.ClockUsage = FREE_RUNNING; + } + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port. + /// + switch (BoardId) { + // CLKREQ + case BoardIdWhiskeyLakeRvp: + Clock[0].PcieClock.ClockUsage = PCIE_PCH + 1; + Clock[1].PcieClock.ClockUsage = PCIE_PCH + 8; + Clock[2].PcieClock.ClockUsage = LAN_CLOCK; + Clock[3].PcieClock.ClockUsage = PCIE_PCH + 13; + Clock[4].PcieClock.ClockUsage = PCIE_PCH + 4; + Clock[5].PcieClock.ClockUsage = PCIE_PCH + 14; + break; + + default: + break; + } + + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); + PcdSet64S (PcdPcieClock10, Clock[10].Blob); + PcdSet64S (PcdPcieClock11, Clock[11].Blob); + PcdSet64S (PcdPcieClock12, Clock[12].Blob); + PcdSet64S (PcdPcieClock13, Clock[13].Blob); + PcdSet64S (PcdPcieClock14, Clock[14].Blob); + PcdSet64S (PcdPcieClock15, Clock[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board USB related configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +UsbConfigInit ( + IN UINT16 BoardId + ) +{ + PCD32_BLOB *UsbPort20Afe; + + UsbPort20Afe = AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BLOB)); + ASSERT (UsbPort20Afe != NULL); + if (UsbPort20Afe == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // USB2 AFE settings. + // + UsbPort20Afe[0].Info.Petxiset = 7; + UsbPort20Afe[0].Info.Txiset = 5; + UsbPort20Afe[0].Info.Predeemp = 3; + UsbPort20Afe[0].Info.Pehalfbit = 0; + + UsbPort20Afe[1].Info.Petxiset = 7; + UsbPort20Afe[1].Info.Txiset = 5; + UsbPort20Afe[1].Info.Predeemp = 3; + UsbPort20Afe[1].Info.Pehalfbit = 0; + + UsbPort20Afe[2].Info.Petxiset = 7; + UsbPort20Afe[2].Info.Txiset = 5; + UsbPort20Afe[2].Info.Predeemp = 3; + UsbPort20Afe[2].Info.Pehalfbit = 0; + + UsbPort20Afe[3].Info.Petxiset = 7; + UsbPort20Afe[3].Info.Txiset = 5; + UsbPort20Afe[3].Info.Predeemp = 3; + UsbPort20Afe[3].Info.Pehalfbit = 0; + + UsbPort20Afe[4].Info.Petxiset = 7; + UsbPort20Afe[4].Info.Txiset = 5; + UsbPort20Afe[4].Info.Predeemp = 3; + UsbPort20Afe[4].Info.Pehalfbit = 0; + + UsbPort20Afe[5].Info.Petxiset = 7; + UsbPort20Afe[5].Info.Txiset = 5; + UsbPort20Afe[5].Info.Predeemp = 3; + UsbPort20Afe[5].Info.Pehalfbit = 0; + + UsbPort20Afe[6].Info.Petxiset = 7; + UsbPort20Afe[6].Info.Txiset = 5; + UsbPort20Afe[6].Info.Predeemp = 3; + UsbPort20Afe[6].Info.Pehalfbit = 0; + + UsbPort20Afe[7].Info.Petxiset = 7; + UsbPort20Afe[7].Info.Txiset = 5; + UsbPort20Afe[7].Info.Predeemp = 3; + UsbPort20Afe[7].Info.Pehalfbit = 0; + + UsbPort20Afe[8].Info.Petxiset = 7; + UsbPort20Afe[8].Info.Txiset = 5; + UsbPort20Afe[8].Info.Predeemp = 3; + UsbPort20Afe[8].Info.Pehalfbit = 0; + + UsbPort20Afe[9].Info.Petxiset = 7; + UsbPort20Afe[9].Info.Txiset = 5; + UsbPort20Afe[9].Info.Predeemp = 3; + UsbPort20Afe[9].Info.Pehalfbit = 0; + + // + // USB Port Over Current Pin + // + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax); + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip); + + // USB2.0 AFE settings + UsbPort20Afe[0].Info.Petxiset = 6; + UsbPort20Afe[0].Info.Txiset = 0; + UsbPort20Afe[0].Info.Predeemp = 3; + UsbPort20Afe[0].Info.Pehalfbit = 0; + + UsbPort20Afe[1].Info.Petxiset = 6; + UsbPort20Afe[1].Info.Txiset = 0; + UsbPort20Afe[1].Info.Predeemp = 3; + UsbPort20Afe[1].Info.Pehalfbit = 0; + + UsbPort20Afe[2].Info.Petxiset = 6; + UsbPort20Afe[2].Info.Txiset = 0; + UsbPort20Afe[2].Info.Predeemp = 3; + UsbPort20Afe[2].Info.Pehalfbit = 0; + + UsbPort20Afe[3].Info.Petxiset = 6; + UsbPort20Afe[3].Info.Txiset = 0; + UsbPort20Afe[3].Info.Predeemp = 3; + UsbPort20Afe[3].Info.Pehalfbit = 0; + + UsbPort20Afe[4].Info.Petxiset = 6; + UsbPort20Afe[4].Info.Txiset = 0; + UsbPort20Afe[4].Info.Predeemp = 3; + UsbPort20Afe[4].Info.Pehalfbit = 0; + + UsbPort20Afe[5].Info.Petxiset = 6; + UsbPort20Afe[5].Info.Txiset = 0; + UsbPort20Afe[5].Info.Predeemp = 3; + UsbPort20Afe[5].Info.Pehalfbit = 0; + + UsbPort20Afe[6].Info.Petxiset = 6; + UsbPort20Afe[6].Info.Txiset = 0; + UsbPort20Afe[6].Info.Predeemp = 3; + UsbPort20Afe[6].Info.Pehalfbit = 0; + + UsbPort20Afe[7].Info.Petxiset = 6; + UsbPort20Afe[7].Info.Txiset = 0; + UsbPort20Afe[7].Info.Predeemp = 3; + UsbPort20Afe[7].Info.Pehalfbit = 0; + + UsbPort20Afe[8].Info.Petxiset = 6; + UsbPort20Afe[8].Info.Txiset = 0; + UsbPort20Afe[8].Info.Predeemp = 3; + UsbPort20Afe[8].Info.Pehalfbit = 0; + + UsbPort20Afe[9].Info.Petxiset = 6; + UsbPort20Afe[9].Info.Txiset = 0; + UsbPort20Afe[9].Info.Predeemp = 3; + UsbPort20Afe[9].Info.Pehalfbit = 0; + break; + } + + // + // Save USB2.0 AFE blobs + // + PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob); + PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob); + PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob); + PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob); + PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob); + PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob); + PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob); + PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob); + PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob); + PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob); + PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob); + PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob); + PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob); + PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob); + PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob); + PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board GPIO Group Tier configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioGroupTierInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Group Tier + // + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G); + PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI); + PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E); + break; + + default: + PcdSet32S (PcdGpioGroupToGpeDw0, 0); + PcdSet32S (PcdGpioGroupToGpeDw1, 0); + PcdSet32S (PcdGpioGroupToGpeDw2, 0); + break; + } + + return EFI_SUCCESS; +} + +/** + GPIO init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioTablePreMemInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableWhlUDdr4PreMem); + PcdSet16S (PcdBoardGpioTablePreMemSize, sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet32S (PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOnEarlyPreMem); + PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet32S (PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOffEarlyPreMem); + PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + +/** + PmConfig init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PchPmConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0# is asserted based on board HW design + // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport) + // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeControl) + // Only applys to board with PCH-LP. Board with Discrete PCH doesn't need this setting. + // + switch (BoardId) { + // Discrete VR solution + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE); + break; + + default: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE); + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c new file mode 100644 index 0000000000..17f12c117d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c @@ -0,0 +1,282 @@ +/** @file + Source code for the board SA configuration Pcd init functions in Pre-Memory init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include "BoardSaConfigPreMem.h" +#include +#include +#include "SaPolicyCommon.h" + +// +// Display DDI settings for WHL ERB +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = { + DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI + DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD + DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD + DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD + DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD + DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC + DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC + DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC + DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC +}; + +/** + MRC configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaMiscConfigInit ( + IN UINT16 BoardId + ) +{ + // + // UserBd + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + // + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms. + // This is required to skip Memory voltage programming based on GPIO's in MRC + // + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform + break; + + default: + // MiscPeiPreMemConfig.UserBd = 0 by default. + break; + } + + PcdSet16S (PcdSaDdrFreqLimit, 0); + + return EFI_SUCCESS; +} + +/** + Board Memory Init related configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +MrcConfigInit ( + IN UINT16 BoardId + ) +{ + CPU_FAMILY CpuFamilyId; + CPU_STEPPING CpuStepping; + + CpuFamilyId = GetCpuFamily(); + CpuStepping = GetCpuStepping(); + + if (CpuFamilyId == EnumCpuCflDtHalo) { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE); + } else { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE); + } + + // + // Example policy for DIMM slots implementation boards: + // 1. Assign Smbus address of DIMMs and SpdData will be updated later + // by reading from DIMM SPD. + // 2. No need to apply hardcoded SpdData buffers here for such board. + // + // Whiskey Lake U RVP has removable DIMM slots. + // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0. + // Example: + // PcdMrcSpdData = 0 + // PcdMrcSpdDataSize = 0 + // PcdMrcSpdAddressTable0 = 0xA0 + // PcdMrcSpdAddressTable1 = 0xA2 + // PcdMrcSpdAddressTable2 = 0xA4 + // PcdMrcSpdAddressTable3 = 0xA6 + // + // If a board has soldered down memory. It should use the following settings. + // Example: + // PcdMrcSpdAddressTable0 = 0 + // PcdMrcSpdAddressTable1 = 0 + // PcdMrcSpdAddressTable2 = 0 + // PcdMrcSpdAddressTable3 = 0 + // PcdMrcSpdData = static data buffer + // PcdMrcSpdDataSize = sizeof (static data buffer) + // + + // + // SPD Address Table + // + PcdSet32S (PcdMrcSpdData, 0); + PcdSet16S (PcdMrcSpdDataSize, 0); + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); + + // + // DRAM SPD Data & related configuration + // + // Setting the PCD's to default value (WHL RVP3). It will be overriden to board specific settings below. + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapWhlUDdr4Rvp); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapWhlUDdr4Rvp)); + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramWhlUDdr4Rvp); + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramWhlUDdr4Rvp)); + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorCflUDdr4Interposer); + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetWhlUDdr4Interposer); + PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE); + break; + + default: + break; + } + + // + // CA Vref routing: board-dependent + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L) + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used) + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4) + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards + break; + + default: + PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards + break; + } + + return EFI_SUCCESS; +} + +/** + Board SA related GPIO configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaGpioConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update board's GPIO for PEG slot reset + // + PcdSetBoolS (PcdPegGpioResetControl, TRUE); + PcdSetBoolS (PcdPegGpioResetSupoort, FALSE); + PcdSet32S (PcdPeg0ResetGpioPad, 0); + PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE); + PcdSet32S (PcdPeg3ResetGpioPad, 0); + PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE); + + // + // PCIE RTD3 GPIO + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S(PcdRootPortIndex, 4); + PcdSet8S (PcdPcie0GpioSupport, PchGpio); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + + default: + PcdSet8S(PcdRootPortIndex, 0xFF); + PcdSet8S (PcdPcie0GpioSupport, NotSupported); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** + SA Display DDI configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaDisplayConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update Display DDI Config + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConfig); + PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdiConfig)); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..c52d4eceed --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + WhiskeylakeURvpBoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..1283a4c80a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,106 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + WhiskeylakeURvpBoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + WhiskeylakeURvpBoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return WhiskeylakeURvpBoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + WhiskeylakeURvpBoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..965110a5a5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,41 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mWhiskeylakeURvpBoardInitFunc = { + WhiskeylakeURvpBoardInitBeforeSiliconInit, + NULL, // BoardInitAfterSiliconInit +}; + +EFI_STATUS +EFIAPI +PeiWhiskeylakeURvpMultiBoardInitLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () == BoardIdWhiskeyLakeRvp) { + return RegisterBoardPostMemInit (&mWhiskeylakeURvpBoardInitFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..a2a6efe506 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,83 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ); + +BOARD_DETECT_FUNC mWhiskeylakeURvpBoardDetectFunc = { + WhiskeylakeURvpMultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mWhiskeylakeURvpBoardPreMemInitFunc = { + WhiskeylakeURvpBoardDebugInit, + WhiskeylakeURvpBoardBootModeDetect, + WhiskeylakeURvpBoardInitBeforeMemoryInit, + NULL, // BoardInitAfterMemoryInit + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDetect ( + VOID + ) +{ + WhiskeylakeURvpBoardDetect (); + if (LibPcdGetSku () == BoardIdWhiskeyLakeRvp) { + RegisterBoardPreMemInit (&mWhiskeylakeURvpBoardPreMemInitFunc); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiWhiskeylakeURvpMultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mWhiskeylakeURvpBoardDetectFunc); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c new file mode 100644 index 0000000000..0adbed7f53 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiWhiskeylakeURvpInitLib.h" + +#include +#include + +BOOLEAN +WhiskeylakeURvp( + VOID + ) +{ + return TRUE; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ) +{ + if (LibPcdGetSku () != 0) { + return EFI_SUCCESS; + } + + DEBUG ((EFI_D_INFO, "WhiskeylakeURvpDetectionCallback\n")); + + if (WhiskeylakeURvp()) { + LibPcdSetSku (BoardIdWhiskeyLakeRvp); + + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + ASSERT (LibPcdGetSku() == BoardIdWhiskeyLakeRvp); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c new file mode 100644 index 0000000000..80b0a97612 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c @@ -0,0 +1,432 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PeiWhiskeylakeURvpInitLib.h" +#include "GpioTableDefault.h" +#include "GpioTableWhlUDdr4.h" +#include +#include +#include +#include +#include + +EFI_STATUS +BoardFunctionInit( + IN UINT16 BoardId +); + +/** +GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardGpioInit( + IN UINT16 BoardId +) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableWhlUDdr4_0); + PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableWhlUDdr4_0) / sizeof(GPIO_INIT_CONFIG)); + PcdSet32S(PcdBoardGpioTable2, (UINTN)mGpioTableWhlUDdr4); + PcdSet16S(PcdBoardGpioTable2Size, sizeof(mGpioTableWhlUDdr4) / sizeof(GPIO_INIT_CONFIG)); + break; + + default: + DEBUG((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n")); + PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableDefault); + PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableDefault) / sizeof(GPIO_INIT_CONFIG)); + break; + } + + return EFI_SUCCESS; +} + +/** +Touch panel GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +TouchPanelGpioInit( + IN UINT16 BoardId +) +{ + switch (BoardId) { + default: + PcdSet32S(PcdBoardGpioTableTouchPanel, 0); + break; + } + return EFI_SUCCESS; +} + +/** +Misc. init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInit( + IN UINT16 BoardId +) +{ + PcdSetBoolS(PcdDebugUsbUartEnable, FALSE); + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + + PcdSetBoolS(PcdMipiCamGpioEnable, TRUE); + break; + + default: + PcdSetBoolS(PcdMipiCamGpioEnable, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** +Security GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardSecurityInit ( + IN UINT16 BoardId +) +{ + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + + // TPM interrupt connects to GPIO_CNL_H_GPP_A_7 + PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F); + break; + + } + + return EFI_SUCCESS; +} + +/** +WhiskeyLake board configuration init function for PEI post memory phase. + +@param[in] Content pointer to the buffer contain init information for board init. + +@retval EFI_SUCCESS The function completed successfully. +@retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +BoardConfigInit( + VOID +) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId = BoardIdWhiskeyLakeRvp; + + Status = BoardGpioInit(BoardId); + Status = TouchPanelGpioInit(BoardId); + Status = HdaVerbTableInit(BoardId); + Status = BoardMiscInit(BoardId); + Status = BoardFunctionInit(BoardId); + Status = BoardSecurityInit(BoardId); + + return EFI_SUCCESS; +} + +//@todo Review this functionality and if it is required for WHL SDS +/** +Create the HOB for hotkey status for 'Attempt USB First' feature + +@retval EFI_SUCCESS HOB Creating successful. +@retval Others HOB Creating failed. +**/ +EFI_STATUS +CreateAttemptUsbFirstHotkeyInfoHob( + VOID +) +{ + EFI_STATUS Status; + ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo; + + Status = EFI_SUCCESS; + + ZeroMem( + &AttemptUsbFirstHotkeyInfo, + sizeof(AttemptUsbFirstHotkeyInfo) + ); + + AttemptUsbFirstHotkeyInfo.RevisonId = 0; + AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE; + + /// + /// Build HOB for Attempt USB First feature + /// + BuildGuidDataHob( + &gAttemptUsbFirstHotkeyInfoHobGuid, + &(AttemptUsbFirstHotkeyInfo), + sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO) + ); + + return Status; +} + +/** +Search and identify the physical address of a +file module inside the FW_BINARIES_FV_SIGNED FV + +@retval EFI_SUCCESS If address has been found +@retval Others If address has not been found +**/ +EFI_STATUS +FindModuleInFlash2( + IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader, + IN EFI_GUID *GuidPtr, + IN OUT UINT32 *ModulePtr, + IN OUT UINT32 *ModuleSize +) +{ + EFI_FFS_FILE_HEADER *FfsHeader; + EFI_FV_FILE_INFO FileInfo; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_COMMON_SECTION_HEADER *SectionHeader; + VOID *FileBuffer; + EFI_STATUS Status; + + FfsHeader = NULL; + FileHandle = NULL; + SectionHeader = NULL; + FileBuffer = NULL; + + while (TRUE) { + // + // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware volume + // + Status = PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle); + if (EFI_ERROR(Status)) { + // unable to find FV_IMAGE file in this FV + break; + } + + FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle; + DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader)); + DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name)); + DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type)); + if (IS_FFS_FILE2(FfsHeader)) { + DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader))); + } + else { + DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader))); + } + + // + // Locate FW_BINARIES_FV FV_IMAGE Section + // + Status = PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer); + if (EFI_ERROR(Status)) { + // continue to search for the next FV_IMAGE file + DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status = %r\n", Status)); + continue; + } + + SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer; + DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n", + (UINT32)(UINT8 *)SectionHeader)); + if (IS_SECTION2(SectionHeader)) { + DEBUG((DEBUG_INFO, " Guid = 0x%g\n", + &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGuid)); + DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n", + ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset)); + } + else { + DEBUG((DEBUG_INFO, " Guid = 0x%g\n", + &((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGuid)); + DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n", + ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset)); + } + DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type)); + + // + // Locate Firmware File System file within Firmware Volume + // + Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID **)&FfsHeader); + if (EFI_ERROR(Status)) { + // continue to search for the next FV_IMAGE file + DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status)); + continue; + } + + *ModulePtr = (UINT32)((UINT8 *)FfsHeader + sizeof(EFI_FFS_FILE_HEADER)); + + // + // Get File Information + // + Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo); + if (!EFI_ERROR(Status)) { + *ModuleSize = (UINT32)FileInfo.BufferSize; + DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size = 0x%X\n", + &FfsHeader->Name, *ModulePtr, *ModuleSize)); + return Status; + } + } + + return EFI_NOT_FOUND; +} + +/** +Get the ChipsetInit Binary pointer. + +@retval EFI_SUCCESS - ChipsetInit Binary found. +@retval EFI_NOT_FOUND - ChipsetInit Binary not found. +**/ +EFI_STATUS +UpdateChipsetInitPtr( + VOID +) +{ + EFI_STATUS Status; + PCH_STEPPING PchStep; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_GUID *ChipsetInitBinaryGuidPtr; + SI_POLICY_PPI *SiPolicyPpi; + PCH_HSIO_CONFIG *HsioConfig; + UINT32 ModuleAddr; + UINT32 ModuleSize; + + ModuleAddr = 0; + ModuleSize = 0; + PchStep = PchStepping(); + + Status = PeiServicesLocatePpi( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + ASSERT_EFI_ERROR(Status); + + Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID *)&HsioConfig); + ASSERT_EFI_ERROR(Status); + + ChipsetInitBinaryGuidPtr = NULL; + if (IsPchLp()) { + switch (PchStep) { + case PCH_D0: + case PCH_D1: + ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid; + DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n")); + break; + default: + return EFI_NOT_FOUND; + } + } + else { + return EFI_NOT_FOUND; + } + + // + // Locate Firmware Volume header + // + // FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)GetFvBinaryBase(); + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32(PcdFlashFvPostMemoryBase); + Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr, &ModuleAddr, &ModuleSize); + // + // Get ChipsetInit Binary Pointer + // + HsioConfig->ChipsetInitBinPtr = ModuleAddr; + + // + // Get File Size + // + HsioConfig->ChipsetInitBinLen = ModuleSize; + + DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->ChipsetInitBinPtr)); + DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->ChipsetInitBinLen)); + + return Status; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 FwConfig; + + BoardConfigInit(); + // + // Configure GPIO and SIO + // + Status = BoardInit(); + ASSERT_EFI_ERROR(Status); + + FwConfig = FwConfigProduction; + PeiPolicyInit(FwConfig); + + // + // Create USB Boot First hotkey information HOB + // + CreateAttemptUsbFirstHotkeyInfoHob(); + + // + // Initializing Platform Specific Programming + // + Status = PlatformSpecificInit(); + ASSERT_EFI_ERROR(Status); + + // + // Update ChipsetInitPtr + // + Status = UpdateChipsetInitPtr(); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c new file mode 100644 index 0000000000..519a5be216 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c @@ -0,0 +1,636 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiWhiskeylakeURvpInitLib.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Reset Generator I/O Port +/// +#define RESET_GENERATOR_PORT 0xCF9 + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 Length; +} MEMORY_MAP; + +// +// Reference RCOMP resistors on motherboard - for WHL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for WHL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 }; + +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = { + { FixedPcdGet64(PcdApicLocalAddress), FixedPcdGet32(PcdApicLocalMmioSize) }, + { FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize) }, + { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) }, + { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) }, + { FixedPcdGet64(PcdGdxcBaseAddress), FixedPcdGet32(PcdGdxcMmioSize) } +}; + +EFI_STATUS +MrcConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +SaGpioConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS + SaMiscConfigInit( +IN UINT16 BoardId +); + +EFI_STATUS + RootPortClkInfoInit( +IN UINT16 BoardId +); + +EFI_STATUS + UsbConfigInit( +IN UINT16 BoardId +); + +EFI_STATUS +GpioGroupTierInit( + IN UINT16 BoardId +); + +EFI_STATUS +GpioTablePreMemInit( + IN UINT16 BoardId +); + +EFI_STATUS +PchPmConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +SaDisplayConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +BoardFunctionInitPreMem( + IN UINT16 BoardId +); + +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +EFI_STATUS +EFIAPI +PchReset( + IN CONST EFI_PEI_SERVICES **PeiServices +); + +static EFI_PEI_RESET_PPI mResetPpi = { + PchReset +}; + +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiResetPpiGuid, + &mResetPpi + } +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiReadOnlyVariable2PpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify +}; + +/** +Board misc init function for PEI pre-memory phase. + +@param[in] BoardId An unsigned integer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInitPreMem( + IN UINT16 BoardId +) +{ + PCD64_BLOB PcdData; + + // + // RecoveryMode GPIO + // + PcdData.Blob = 0; + PcdData.BoardGpioConfig.Type = BoardGpioTypeNotSupported; + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdData.BoardGpioConfig.Type = BoardGpioTypePch; + PcdData.BoardGpioConfig.u.Pin = GPIO_CNL_LP_GPP_F10; + break; + + default: + break; + } + + // + // Configure WWAN Full Card Power Off and reset pins + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + // + // According to board default settings, GPP_D16 is used to enable/disable modem + // power. An alternative way to contol modem power is to toggle FCP_OFF via GPP_D13 + // but board rework is required. + // + PcdSet32S(PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16); + PcdSet32S(PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1); + PcdSet32S(PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15); + PcdSet8S(PcdWwanPerstGpioPolarity, 1); + break; + + default: + break; + } + + PcdSet64S(PcdRecoveryModeGpio, PcdData.Blob); + + // + // Pc8374SioKbc Present + // + PcdSetBoolS(PcdPc8374SioKbcPresent, FALSE); + + return EFI_SUCCESS; +} + +//@todo it should be moved to Si Pkg. +/** +Early Platform PCH initialization +**/ +VOID +EarlyPlatformPchInit( + VOID +) +{ + UINT8 Data8; + UINT8 TcoRebootHappened; + TCO_WDT_HOB *TcoWdtHobPtr; + EFI_STATUS Status; + + /// + /// Read the Second TO status bit + /// + Data8 = IoRead8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS); + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) { + TcoRebootHappened = 1; + DEBUG((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n")); + } + else { + TcoRebootHappened = 0; + } + + /// + /// Create HOB + /// + Status = PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr); + if (!EFI_ERROR(Status)) { + TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid; + TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened; + } + + /// + /// Clear the Second TO status bit + /// + IoWrite8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO); +} + +/** +Board init function for PEI pre-memory phase. + +@param Content pointer to the buffer contain init information for board init. + +@retval EFI_SUCCESS The function completed successfully. +@retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +BoardConfigInitPreMem( + VOID +) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId = BoardIdWhiskeyLakeRvp; + + Status = MrcConfigInit(BoardId); + Status = SaGpioConfigInit(BoardId); + Status = SaMiscConfigInit(BoardId); + Status = RootPortClkInfoInit(BoardId); + Status = UsbConfigInit(BoardId); + Status = GpioGroupTierInit(BoardId); + Status = GpioTablePreMemInit(BoardId); + Status = PchPmConfigInit(BoardId); + Status = BoardMiscInitPreMem(BoardId); + Status = SaDisplayConfigInit(BoardId); + Status = BoardFunctionInitPreMem(BoardId); + + return EFI_SUCCESS; +} + +/** +This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced + +@param[in] PeiServices Pointer to PEI Services Table. +@param[in] NotifyDesc Pointer to the descriptor for the Notification event that + caused this function to execute. +@param[in] Ppi Pointer to the PPI data associated with this function. + +@retval EFI_SUCCESS The function completes successfully +@retval others +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +) +{ + EFI_STATUS Status; + UINT16 ABase; + UINT8 FwConfig; + UINT8 SynchDelay; + + // + // Init Board Config Pcd. + // + BoardConfigInitPreMem(); + + DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n")); + FwConfig = FwConfigProduction; + SynchDelay = 0; + PcdSetBoolS(PcdPcieWwanEnable, FALSE); + PcdSetBoolS(PcdWwanResetWorkaround, FALSE); + + // + // Early Board Configuration before memory is ready. + // + Status = BoardInitEarlyPreMem(); + ASSERT_EFI_ERROR(Status); + + /// + /// If there was unexpected reset but no WDT expiration and no resume from S3/S4, + /// clear unexpected reset status and enforce expiration. This is to inform Firmware + /// which has no access to unexpected reset status bit, that something went wrong. + /// + OcWdtResetCheck(); + + Status = OcWdtInit(); + ASSERT_EFI_ERROR(Status); + + // + // Initialize Intel PEI Platform Policy + // + PeiPolicyInitPreMem(FwConfig); + + /// + /// Configure GPIO and SIO + /// + Status = BoardInitPreMem(); + ASSERT_EFI_ERROR(Status); + + ABase = PmcGetAcpiBase(); + + /// + /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI. + /// + IoWrite16(ABase + R_ACPI_IO_PM1_EN, 0); + IoWrite32(ABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Install Pre Memory PPIs + /// + Status = PeiServicesInstallPpi(&mPreMemPpiList[0]); + ASSERT_EFI_ERROR(Status); + + return Status; +} + +/** +Provide hard reset PPI service. +To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9). + +@param[in] PeiServices General purpose services available to every PEIM. + +@retval Not return System reset occured. +@retval EFI_DEVICE_ERROR Device error, could not reset the system. +**/ +EFI_STATUS +EFIAPI +PchReset( + IN CONST EFI_PEI_SERVICES **PeiServices +) +{ + DEBUG((DEBUG_INFO, "Perform Cold Reset\n")); + IoWrite8(RESET_GENERATOR_PORT, 0x0E); + + CpuDeadLoop(); + + /// + /// System reset occured, should never reach at this line. + /// + ASSERT_EFI_ERROR(EFI_DEVICE_ERROR); + + return EFI_DEVICE_ERROR; +} + +/** +Install Firmware Volume Hob's once there is main memory + +@param[in] PeiServices General purpose services available to every PEIM. +@param[in] NotifyDescriptor Notify that this module published. +@param[in] Ppi PPI that was installed. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT8 PhysicalAddressBits; + UINT32 RegEax; + MEMORY_MAP PcieMmioMap; + + Index = 0; + + Status = PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + AsmCpuid(0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >= 0x80000008) { + AsmCpuid(0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits = (UINT8)RegEax; + } + else { + PhysicalAddressBits = 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob(PhysicalAddressBits, 16); + + /// + /// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios. + /// + PcieMmioMap.BaseAddress = FixedPcdGet64(PcdPciExpressBaseAddress); + PcieMmioMap.Length = PcdGet32(PcdPciExpressRegionLength); + + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + PcieMmioMap.BaseAddress, + PcieMmioMap.Length + ); + BuildMemoryAllocationHob( + PcieMmioMap.BaseAddress, + PcieMmioMap.Length, + EfiMemoryMappedIO + ); + for (Index = 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index++) { + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + MmioMap[Index].BaseAddress, + MmioMap[Index].Length + ); + BuildMemoryAllocationHob( + MmioMap[Index].BaseAddress, + MmioMap[Index].Length, + EfiMemoryMappedIO + ); + } + + // + // Report resource HOB for flash FV + // + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize) + ); + BuildMemoryAllocationHob( + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize), + EfiMemoryMappedIO + ); + + BuildFvHob( + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize) + ); + + return Status; +} + + +/** + Board configuration init function for PEI pre-memory phase. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpInitPreMem ( + VOID + ) +{ + EFI_STATUS Status; + + /// + /// Install Stall PPI + /// + Status = InstallStallPpi(); + ASSERT_EFI_ERROR(Status); + + ///@todo it should be moved to Si Pkg. + /// + /// Do Early PCH init + /// + EarlyPlatformPchInit(); + + // + // Install PCH RESET PPI and EFI RESET2 PeiService + // + Status = PchInitializeReset(); + ASSERT_EFI_ERROR(Status); + + /// + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI produced + /// + Status = PeiServicesNotifyPpi(&mPreMemNotifyList); + + /// + /// After code reorangized, memorycallback will run because the PPI is already + /// installed when code run to here, it is supposed that the InstallEfiMemory is + /// done before. + /// + Status = PeiServicesNotifyPpi(&mMemDiscoveredNotifyList); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ) +{ + WhiskeylakeURvpInitPreMem (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ) +{ + UINT64 LpcBaseAddress; + + /// + /// LPC I/O Configuration + /// + PchLpcIoDecodeRangesSet( + (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) | + (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) | + (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) + ); + + PchLpcIoEnableDecodingSet( + B_LPC_CFG_IOE_ME2 | + B_LPC_CFG_IOE_SE | + B_LPC_CFG_IOE_ME1 | + B_LPC_CFG_IOE_KE | + B_LPC_CFG_IOE_HGE | + B_LPC_CFG_IOE_LGE | + B_LPC_CFG_IOE_FDE | + B_LPC_CFG_IOE_PPE | + B_LPC_CFG_IOE_CBE | + B_LPC_CFG_IOE_CAE + ); + + /// + /// Enable LPC IO decode for EC access + /// + LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpHsioPtssTables.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpHsioPtssTables.c new file mode 100644 index 0000000000..8d8ca835bc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpHsioPtssTables.c @@ -0,0 +1,32 @@ +/** @file + WhiskeylakeURvp HSIO PTSS H File + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef WHISKEYLAKE_RVP3_HSIO_PTSS_H_ +#define WHISKEYLAKE_RVP3_HSIO_PTSS_H_ + +#include + +#ifndef HSIO_PTSS_TABLE_SIZE +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES) +#endif + +//BoardId WhiskeylakeURvp +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[] = { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0} +}; + +UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size = sizeof(PchLpHsioPtss_Cx_WhiskeylakeURvp) / sizeof(HSIO_PTSS_TABLES); + +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[] = { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}, +}; + +UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size = sizeof(PchLpHsioPtss_Bx_WhiskeylakeURvp) / sizeof(HSIO_PTSS_TABLES); + +#endif // WHISKEYLAKE_RVP3_HSIO_PTSS_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c new file mode 100644 index 0000000000..d2c26eb163 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel DXE SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxePolicyBoardConfig.h" + +/** + This function performs DXE SA Policy update by board configuration. + + @param[in, out] DxeSaPolicy DXE SA Policy + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicyBoardConfig ( + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy + ) +{ + EFI_STATUS Status; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n")); + + Status = GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid, (VOID *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..c495a3a401 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c @@ -0,0 +1,299 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 + +#define RECOVERY_MODE_GPIO_PIN 0 // Platform specific @todo use PCD + +#define MANUFACTURE_MODE_GPIO_PIN 0 // Platform specific @todo use PCD + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount); + + + GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO group GPE tier. + + @retval none. +**/ +VOID +GpioGroupTierInitHook( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n")); + + if (PcdGet32 (PcdGpioGroupToGpeDw0)) { + GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0), + PcdGet32 (PcdGpioGroupToGpeDw1), + PcdGet32 (PcdGpioGroupToGpeDw2)); + } + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n")); +} + +/** + Configure single GPIO pad for touchpanel interrupt +**/ +VOID +TouchpanelGpioInit ( + VOID + ) +{ + GPIO_INIT_CONFIG* TouchpanelPad; + GPIO_PAD_OWN PadOwnVal; + + PadOwnVal = 0; + TouchpanelPad = (VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel); + if (TouchpanelPad != NULL) { + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); + if (PadOwnVal == GpioPadOwnHost) { + GpioConfigurePads (1, TouchpanelPad); + } + } +} + +/** + Configure GPIO Before Memory is not ready. + +**/ +VOID +GpioInitPreMem ( + VOID + ) +{ + if (PcdGet32 (PcdBoardGpioTablePreMem) != 0 && PcdGet16 (PcdBoardGpioTablePreMemSize) != 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (UINTN) PcdGet16 (PcdBoardGpioTablePreMemSize)); + } +} + +/** + Basic GPIO configuration before memory is ready + +**/ +VOID +GpioInitEarlyPreMem ( + VOID + ) +{ + GPIO_CONFIG BbrstConfig; + UINT32 WwanBbrstGpio; + + WwanBbrstGpio = PcdGet32 (PcdWwanBbrstGpio); + + if (WwanBbrstGpio) { + // + // BIOS needs to put modem in OFF state for the two scenarios below. + // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep state + // 2. Modem is disabled via setup option + // + GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig); + if ((PcdGetBool (PcdPcieWwanEnable) == FALSE) || + (PcdGetBool (PcdWwanResetWorkaround) == TRUE && + BbrstConfig.Direction == GpioDirOut && + BbrstConfig.OutputState == GpioOutHigh)) { + // + // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs + // + if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize) != 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize)); + } + if (PcdGetBool (PcdPcieWwanEnable) == TRUE && PcdGetBool (PcdWwanResetWorkaround) == TRUE) { + MicroSecondDelay (1 * 1000); // Delay by 1ms + } + } + + // + // Turn ON modem power and de-assert RESET# and PERST# GPIOs + // + if (PcdGetBool (PcdPcieWwanEnable) == TRUE) { + if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize) != 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize)); + } + } + } +} + +/** + Configure GPIO + +**/ +VOID +GpioInit ( + VOID + ) +{ + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) PcdGet16 (PcdBoardGpioTableSize)); + + if (PcdGet32 (PcdBoardGpioTable2)) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2), (UINTN) PcdGet16 (PcdBoardGpioTable2Size)); + } + + TouchpanelGpioInit(); + + // + // Lock pads after initializing platform GPIO. + // Pads which were requested to be unlocked during configuration + // will not be locked. + // + GpioLockPads (); + + return; +} + +/** + Configure Super IO + +**/ +VOID +SioInit ( + VOID + ) +{ + // + // Program and Enable Default Super IO Configuration Port Addresses and range + // + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10); + + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); + return; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ) +{ + // + // Obtain Platform Info from HOB. + // + GpioInitPreMem (); + GpioGroupTierInitHook (); + SioInit (); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ) +{ + + GpioInit (); + + return EFI_SUCCESS; +} + +/** + Do platform specific programming post-memory. + + @retval EFI_SUCCESS The function completed successfully. +**/ + +EFI_STATUS +PlatformSpecificInit ( + VOID + ) +{ + GPIO_CONFIG GpioConfig; + + if (IsCnlPch ()) { + + // + // Tristate unused pins by audio link mode. + // + ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG)); + GpioConfig.PadMode = GpioPadModeGpio; + GpioConfig.HostSoftPadOwn = GpioHostOwnGpio; + GpioConfig.Direction = GpioDirNone; + GpioConfig.OutputState = GpioOutDefault; + GpioConfig.InterruptConfig = GpioIntDis; + GpioConfig.PowerConfig = GpioPlatformReset; + GpioConfig.ElectricalConfig = GpioTermNone; + + GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig); + GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig); + + } + + return EFI_SUCCESS; +} + +/** + Early Board Configuration before memory is ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ) +{ + GpioInitEarlyPreMem (); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c new file mode 100644 index 0000000000..e437814b10 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c @@ -0,0 +1,48 @@ +/** @file + Intel PEI CPU Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI CPU Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post Mem\n")); + + Status = PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR(Status); + + Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..3797df0856 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c @@ -0,0 +1,29 @@ +/** @file + Intel PEI CPU Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI CPU Pre-Memory Policy update by board configuration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c new file mode 100644 index 0000000000..843fe4accd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI ME Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI ME Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post Mem\n")); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..79c93455a6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI ME Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI ME Pre-Memory Policy update by board configuration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre Mem\n")); + + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c new file mode 100644 index 0000000000..5dbc412879 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI PCH Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI PCH Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_CONFIG *PchGeneralConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post Mem\n")); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..1080015029 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI PCH Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI PCH Pre-Memory Policy update by board configuration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre Mem\n")); + + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c new file mode 100644 index 0000000000..d1d964aea7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SA Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + GRAPHICS_PEI_CONFIG *GtConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post Mem\n")); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..34fca7fac3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI SA Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SA Pre-Memory Policy update by board configuration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Pre Mem\n")); + + Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c new file mode 100644 index 0000000000..f5f38910a8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c @@ -0,0 +1,27 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SI Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + return EFI_SUCCESS; +} + -- 2.16.2.windows.1