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From: "Kubacki, Michael A" <michael.a.kubacki@intel.com>
To: devel@edk2.groups.io
Cc: Chasel Chiu <chasel.chiu@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>,
	Liming Gao <liming.gao@intel.com>
Subject: [edk2-platforms][PATCH V4 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures
Date: Tue, 27 Aug 2019 21:09:09 -0700	[thread overview]
Message-ID: <20190828040909.25888-3-michael.a.kubacki@intel.com> (raw)
In-Reply-To: <20190828040909.25888-1-michael.a.kubacki@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec                                                                              |   6 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf                                             |   1 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf                               |   8 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf                          |   2 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf                           |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h                                                             |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h                                                   |  12 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h                                              |   2 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h                              |  41 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h                                    |  41 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c                               |   4 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c                                             |   6 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaVerbTables.h => PchHdaVerbTables.c}                         | 963 +-------------------
 Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c                                               |   7 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c                                        |   6 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c                                   |  15 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c                                                           |   4 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c                            |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c                        |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c                                          |   1 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c                                    |   1 -
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c                                  |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c                                   |   6 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableDefault.h => GpioTableDefault.c}               |  16 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4.h => GpioTableWhiskeylakeUDdr4Rvp.c}  |  20 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4PreMem.h => GpioTableWhlUDdr4PreMem.c} |  21 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c                            |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c                             |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c                               |   2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c                       |  55 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c                        |  82 +-
 31 files changed, 178 insertions(+), 1178 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
index 9d56f0e841..8de48077f0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
@@ -17,12 +17,12 @@
 DEC_SPECIFICATION = 0x00010017
 PACKAGE_NAME = OpenBoardPkg
 PACKAGE_VERSION = 0.1
-PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
+PACKAGE_GUID = 8FE3E02F-BC79-41F2-9A0D-10140B292472
 
 [Includes]
 Include
-WhiskeylakeURvp\Include
-Features\Tbt\Include
+Features/Tbt/Include
+WhiskeylakeURvp/Include
 
 [Guids]
 
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
index 3c017577b6..b09dc6b139 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
@@ -36,6 +36,7 @@
 
 [Sources]
   PeiHdaVerbTableLib.c
+  PchHdaVerbTables.c
 
 ################################################################################
 #
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
index a8c4869e96..91cc569388 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
@@ -19,11 +19,12 @@
 
 [LibraryClasses]
   BaseLib
-  DebugLib
   BaseMemoryLib
+  DebugLib
+  GpioExpanderLib
+  GpioLib
   HdaVerbTableLib
   MemoryAllocationLib
-  GpioExpanderLib
   PcdLib
 
 [Packages]
@@ -37,6 +38,8 @@
 [Sources]
   PeiWhiskeylakeURvpInitPostMemLib.c
   PeiBoardInitPostMemLib.c
+  GpioTableDefault.c
+  GpioTableWhiskeylakeUDdr4Rvp.c
 
 [Pcd]
   gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
@@ -50,4 +53,3 @@
   gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
 
   gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
index 4831735dc5..c7330439fb 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -44,6 +44,8 @@
   PeiMultiBoardInitPostMemLib.c
   BoardFunc.c
   BoardFuncInit.c
+  GpioTableDefault.c
+  GpioTableWhiskeylakeUDdr4Rvp.c
 
 [FixedPcd]
 
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 6affc3180e..927a89d401 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -20,17 +20,18 @@
 
 [LibraryClasses]
   BaseLib
-  DebugLib
   BaseMemoryLib
+  DebugLib
+  GpioLib
   MemoryAllocationLib
-  PcdLib
   MultiBoardInitSupportLib
-  StallPpiLib
+  OcWdtLib
+  PcdLib
   PchResetLib
   PeiPlatformHookLib
-  PlatformHookLib
   PeiPolicyInitLib
-  OcWdtLib
+  PlatformHookLib
+  StallPpiLib
 
 [Packages]
   MinPlatformPkg/MinPlatformPkg.dec
@@ -47,6 +48,7 @@
   BoardSaInitPreMemLib.c
   BoardPchInitPreMemLib.c
   BoardFuncInitPreMem.c
+  GpioTableWhlUDdr4PreMem.c
 
 [Ppis]
   gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
index 395d08779c..79f98af2f0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
@@ -9,7 +9,7 @@
 #ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_
 #define _PCIE_DEVICE_OVERRIDE_TABLE_H_
 
-#include <ConfigBlock/PcieRpconfig.h>
+#include <ConfigBlock/PcieRpConfig.h>
 #include <IndustryStandard/Pci22.h>
 
 #define PCI_CLASS_NETWORK             0x02
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
deleted file mode 100644
index 7d44acccc1..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/** @file
-
-  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _WHISKEYLAKE_ERB_ID_H_
-#define _WHISKEYLAKE_ERB_ID_H_
-
-#define BoardIdWhiskeyLakeRvp          0x60
-#endif // _WHISKEYLAKE_RVP3_ID_H_
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
index eca492e72d..9e0ff8d033 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
@@ -9,6 +9,8 @@
 #ifndef _BOARD_FUNC_H_
 #define _BOARD_FUNC_H_
 
+#include <Uefi.h>
+
 EFI_STATUS
 PeiBoardSpecificInitPostMemNull (
   VOID
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
deleted file mode 100644
index 89c780cc0b..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/** @file
-
-  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_
-#define _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-#include <Library/GpioLib.h>
-#include <Ppi/SiPolicy.h>
-#include <PchHsioPtssTables.h>
-#include <IoExpander.h>
-
-#include <WhiskeylakeURvpId.h>
-
-extern const UINT8 mDqByteMapSklRvp3[2][6][2];
-extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];
-extern const UINT8 mSkylakeRvp3Spd110[];
-extern const UINT16 mSkylakeRvp3Spd110Size;
-extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[];
-extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size;
-extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[];
-extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size;
-
-extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];
-extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;
-
-extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];
-extern UINT16 mGpioTableIoExpanderSize;
-extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;
-extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];
-extern UINT16 mGpioTableLpDdr3Rvp3Size;
-
-#endif // _PEI_Whiskeylake_RVP3_BOARD_INIT_LIB_H_
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
new file mode 100644
index 0000000000..325bcb41df
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
@@ -0,0 +1,41 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WHISKEY_LAKE_U_RVP_INIT_H_
+#define _WHISKEY_LAKE_U_RVP_INIT_H_
+
+#include <Uefi.h>
+#include <IoExpander.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[];
+extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[];
+extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size;
+
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[];
+extern UINT16 mGpioTableWhlUDdr4PreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize;
+
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[];
+extern UINT16 mGpioTableWhlUDdr4_0Size;
+extern GPIO_INIT_CONFIG mGpioTableDefault[];
+extern UINT16 mGpioTableDefaultSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4[];
+extern UINT16 mGpioTableWhlUDdr4Size;
+
+#endif // _WHISKEY_LAKE_U_RVP_INIT_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
index f38901f2ae..38c95f7b5d 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
@@ -173,7 +173,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2(
   // Retrieve BIST data from SecPlatform2
   //
   Status = SecPlatformInformation2Ppi->PlatformInformation2 (
-                                         PeiServices,
+                                         (CONST EFI_PEI_SERVICES  **) PeiServices,
                                          &InformationSize,
                                          SecPlatformInformation2
                                          );
@@ -240,7 +240,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInFormat2(
   // Retrieve BIST data from SecPlatform
   //
   Status = SecPlatformInformationPpi->PlatformInformation (
-                                        PeiServices,
+                                        (CONST EFI_PEI_SERVICES  **) PeiServices,
                                         &InformationSize,
                                         SecPlatformInformation
                                         );
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
index 8498952888..c6009eae12 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
@@ -70,12 +70,11 @@ GpioExpGetRegister (
   IN UINT8 Register
   )
 {
-  EFI_STATUS Status;
   UINT8 WriBuf[1];
   UINT8 ReBuf[1] = {0};
 
   WriBuf[0] = Register;
-  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
 
   return ReBuf[0];
 }
@@ -99,13 +98,12 @@ GpioExpSetRegister (
   IN UINT8 Value
   )
 {
-  EFI_STATUS Status;
   UINT8 WriBuf[2];
 
   WriBuf[0] = Register;
   WriBuf[1] = Value;
-  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
 
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
 }
 /**
   Set the input register to a give value mentioned in the function.
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c
similarity index 65%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.h
rename to Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c
index 0d26e8ad7a..563685b4aa 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c
@@ -4,9 +4,7 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#ifndef _PCH_HDA_VERB_TABLES_H_
-#define _PCH_HDA_VERB_TABLES_H_
-
+#include <ConfigBlock/HdAudioConfig.h>
 #include <Ppi/SiPolicy.h>
 
 HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio = HDAUDIO_VERB_TABLE_INIT (
@@ -1105,962 +1103,6 @@ HDAUDIO_VERB_TABLE HdaVerbTableAlc274 = HDAUDIO_VERB_TABLE_INIT (
   0x0204201B
 ); //HdaVerbTableAlc274
 
-//
-// CFL S Audio Codec
-//
-STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
-  //
-  //  VerbTable: (Realtek ALC700) CFL S RVP
-  //  Revision ID = 0xff
-  //  Codec Verb Table
-  //  Codec Address: CAd value (0/1/2)
-  //  Codec Vendor: 0x10EC0700
-  //
-  0x10EC, 0x0700,
-  0xFF, 0xFF,
-
-  //===================================================================================================
-  //
-  //                               Realtek Semiconductor Corp.
-  //
-  //===================================================================================================
-
-  //Realtek High Definition Audio Configuration - Version : 5.0.3.1
-  //Realtek HD Audio Codec : ALC700
-  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
-  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C
-  //The number of verb command block : 17
-
-  //    NID 0x12 : 0x90A60130
-  //    NID 0x13 : 0x40000000
-  //    NID 0x14 : 0x411111F0
-  //    NID 0x15 : 0x411111F0
-  //    NID 0x16 : 0x03011010
-  //    NID 0x17 : 0x90170120
-  //    NID 0x18 : 0x411111F0
-  //    NID 0x19 : 0x04A1103E
-  //    NID 0x1A : 0x411111F0
-  //    NID 0x1B : 0x03A11040
-  //    NID 0x1D : 0x40600001
-  //    NID 0x1E : 0x411111F0
-  //    NID 0x1F : 0x411111F0
-  //    NID 0x21 : 0x0421102F
-  //    NID 0x29 : 0x411111F0
-
-
-  //===== HDA Codec Subsystem ID Verb-table =====
-  //HDA Codec Subsystem ID  : 0x10EC112C
-  0x0017202C,
-  0x00172111,
-  0x001722EC,
-  0x00172310,
-
-
-  //===== Pin Widget Verb-table =====
-  //Widget node 0x01 :
-  0x0017FF00,
-  0x0017FF00,
-  0x0017FF00,
-  0x0017FF00,
-  //Pin widget 0x12 - DMIC
-  0x01271C30,
-  0x01271D01,
-  0x01271EA6,
-  0x01271F90,
-  //Pin widget 0x13 - DMIC
-  0x01371C00,
-  0x01371D00,
-  0x01371E00,
-  0x01371F40,
-  //Pin widget 0x14 - FRONT (Port-D)
-  0x01471CF0,
-  0x01471D11,
-  0x01471E11,
-  0x01471F41,
-  //Pin widget 0x15 - I2S-OUT
-  0x01571CF0,
-  0x01571D11,
-  0x01571E11,
-  0x01571F41,
-  //Pin widget 0x16 - LINE3 (Port-B)
-  0x01671C10,
-  0x01671D10,
-  0x01671E01,
-  0x01671F03,
-  //Pin widget 0x17 - I2S-OUT
-  0x01771C20,
-  0x01771D01,
-  0x01771E17,
-  0x01771F90,
-  //Pin widget 0x18 - I2S-IN
-  0x01871CF0,
-  0x01871D11,
-  0x01871E11,
-  0x01871F41,
-  //Pin widget 0x19 - MIC2 (Port-F)
-  0x01971C3E,
-  0x01971D10,
-  0x01971EA1,
-  0x01971F04,
-  //Pin widget 0x1A - LINE1 (Port-C)
-  0x01A71CF0,
-  0x01A71D11,
-  0x01A71E11,
-  0x01A71F41,
-  //Pin widget 0x1B - LINE2 (Port-E)
-  0x01B71C40,
-  0x01B71D10,
-  0x01B71EA1,
-  0x01B71F03,
-  //Pin widget 0x1D - PC-BEEP
-  0x01D71C01,
-  0x01D71D00,
-  0x01D71E60,
-  0x01D71F40,
-  //Pin widget 0x1E - S/PDIF-OUT
-  0x01E71CF0,
-  0x01E71D11,
-  0x01E71E11,
-  0x01E71F41,
-  //Pin widget 0x1F - S/PDIF-IN
-  0x01F71CF0,
-  0x01F71D11,
-  0x01F71E11,
-  0x01F71F41,
-  //Pin widget 0x21 - HP-OUT (Port-I)
-  0x02171C2F,
-  0x02171D10,
-  0x02171E21,
-  0x02171F04,
-  //Pin widget 0x29 - I2S-IN
-  0x02971CF0,
-  0x02971D11,
-  0x02971E11,
-  0x02971F41,
-
-  //Widget node 0x20 - 0  FAKE JD unplug
-  0x02050008,
-  0x0204A80F,
-  0x02050008,
-  0x0204A80F,
-  //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of NID 1Bh ,  HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14)
-  0x0205006B,
-  0x02044260,
-  0x0205006B,
-  0x02044260,
-  //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700
-  0x05B50010,
-  0x05B45C1D,
-  0x0205006F,
-  0x02040F8B,   //Zeek, 0F8Bh
-  //Widget node 0x20 -3 :  MIC2-Vrefo-R and MIC2-vrefo-L to independent control
-  0x02050045,
-  0x02045089,
-  0x0205004A,
-  0x0204201B,
-  //Widget node 0x20 - 4   From JD detect
-  0x02050008,
-  0x0204A807,
-  0x02050008,
-  0x0204A807,
-  //Widget node 0x20 - 5  Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first
-  0x02050090,
-  0x02040424,
-  0x00171620,
-  0x00171720,
-
-  0x00171520,
-  0x01770740,
-  0x01770740,
-  0x01770740,
-
-
-  //Widget node 0X20 for ALC1305   20181023 update   2W/4ohm to remove ALC1305 EQ setting
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040000,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x020400CF,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x02045548,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003F,
-  0x02050028,
-  0x02041000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040004,
-  0x02050028,
-  0x02040600,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FFD0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040080,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040880,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003A,
-  0x02050028,
-  0x02040DFE,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x0204005D,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x02040442,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040005,
-  0x02050028,
-  0x02040880,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040006,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040008,
-  0x02050028,
-  0x0204B000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204002E,
-  0x02050028,
-  0x02040800,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x020400C3,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x0204D4A0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x020400CC,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x0204400A,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x020400C1,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x02040320,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040039,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003B,
-  0x02050028,
-  0x0204FFFF,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FC20,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x02040006,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x020400C0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FCA0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FCE0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FCF0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040080,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040880,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040880,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FCE0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FCA0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003C,
-  0x02050028,
-  0x0204FC20,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x02040006,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040080,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C0,
-  0x02050028,
-  0x020401F0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C1,
-  0x02050028,
-  0x0204C1C7,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C2,
-  0x02050028,
-  0x02041C00,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C3,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C4,
-  0x02050028,
-  0x02040200,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C5,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C6,
-  0x02050028,
-  0x020403E1,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C7,
-  0x02050028,
-  0x02040F5A,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C8,
-  0x02050028,
-  0x02041E1E,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400C9,
-  0x02050028,
-  0x0204083F,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CA,
-  0x02050028,
-  0x020401F0,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CB,
-  0x02050028,
-  0x0204C1C7,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CC,
-  0x02050028,
-  0x02041C00,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CD,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CE,
-  0x02050028,
-  0x02040200,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400CF,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400D0,
-  0x02050028,
-  0x020403E1,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400D1,
-  0x02050028,
-  0x02040F5A,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400D2,
-  0x02050028,
-  0x02041E1E,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x020400D3,
-  0x02050028,
-  0x0204083F,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040062,
-  0x02050028,
-  0x02048000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040063,
-  0x02050028,
-  0x02045F5F,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040064,
-  0x02050028,
-  0x02042000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040065,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040066,
-  0x02050028,
-  0x02044004,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040067,
-  0x02050028,
-  0x02040802,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040068,
-  0x02050028,
-  0x0204890F,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040069,
-  0x02050028,
-  0x0204E021,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040070,
-  0x02050028,
-  0x02048012,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040071,
-  0x02050028,
-  0x02043450,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040072,
-  0x02050028,
-  0x02040123,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040073,
-  0x02050028,
-  0x02044543,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040074,
-  0x02050028,
-  0x02042100,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040075,
-  0x02050028,
-  0x02044321,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040076,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040050,
-  0x02050028,
-  0x02048200,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040051,
-  0x02050028,
-  0x02040707,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040052,
-  0x02050028,
-  0x02044090,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006A,
-  0x02050028,
-  0x02040090,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204006C,
-  0x02050028,
-  0x0204721F,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040012,
-  0x02050028,
-  0x0204DFDF,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204009E,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040004,
-  0x02050028,
-  0x02040500,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040060,
-  0x02050028,
-  0x02042213,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003A,
-  0x02050028,
-  0x02041DFE,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204003F,
-  0x02050028,
-  0x02043000,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040040,
-  0x02050028,
-  0x0204000C,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x02040046,
-  0x02050028,
-  0x0204C22E,
-  0x02050029,
-  0x0204B024,
-
-  0x02050024,
-  0x02040010,
-  0x02050026,
-  0x0204004B,
-  0x02050028,
-  0x02040000,
-  0x02050029,
-  0x0204B024
-);
-
-
 //
 // WHL codecs verb tables
 //
@@ -3009,6 +2051,3 @@ HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
   0x02050029,
   0x0204B024
 ); // WhlHdaVerbTableAlc700
-
-#endif // _PCH_HDA_VERB_TABLES_H_
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
index b8afd791f0..46cfe9566c 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
@@ -13,7 +13,12 @@
 #include <Library/HdaVerbTableLib.h>
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PcdLib.h>
-#include "PchHdaVerbTables.h"
+
+extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701;
+extern HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700;
 
 /**
   Add verb table helper function.
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
index 3e44c6cc29..e7e5ff5b1a 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -24,7 +24,6 @@
 #include <PlatformBoardConfig.h>
 #include <Library/CnviLib.h>
 #include <Register/PchRegsLpcCnl.h>
-#include <Ppi/PeiTbtPolicy.h>
 #include <PcieDeviceOverrideTable.h>
 
 VOID
@@ -275,7 +274,6 @@ UpdatePeiPchPolicy (
   EFI_STATUS                      Status;
   UINT8                           Index;
   DMI_HW_WIDTH_CONTROL            *DmiHaAWC;
-  UINT16                          LpcDid;
   PCH_GENERAL_CONFIG              *PchGeneralConfig;
   PCH_PCIE_CONFIG                 *PcieRpConfig;
   PCH_SATA_CONFIG                 *SataConfig;
@@ -295,7 +293,6 @@ UpdatePeiPchPolicy (
   USB_CONFIG                      *UsbConfig;
   PCH_ESPI_CONFIG                 *EspiConfig;
   PCH_CNVI_CONFIG                 *CnviConfig;
-  PEI_TBT_POLICY                  *PeiTbtPolicy;
   SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
 
   Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
@@ -345,9 +342,6 @@ UpdatePeiPchPolicy (
                 );
   ASSERT_EFI_ERROR (Status);
 
-  PeiTbtPolicy = NULL;
-  LpcDid = PchGetLpcDid ();
-
   DmiConfig->PwrOptEnable = TRUE;
   PmConfig->PchSlpS3MinAssert = 0;
   PmConfig->PchSlpS4MinAssert = 0;
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
index 3dc455ab29..0bdd503e2c 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -1,9 +1,10 @@
 /** @file
-Do Platform Stage System Agent initialization.
+  Platform Stage System Agent initialization.
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
+
 **/
 
 #include "PeiSaPolicyUpdate.h"
@@ -26,7 +27,7 @@ Do Platform Stage System Agent initialization.
 /// Memory Reserved should be between 125% to 150% of the Current required memory
 /// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
 ///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
   { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) },  // ASL
   { EfiACPIMemoryNVS,       FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) },      // ACPI NVS (including S3 related)
   { EfiReservedMemoryType,  FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) },     // BIOS Reserved (including S3 related)
@@ -35,7 +36,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInfo
   { EfiMaxMemoryType, 0 }
 };
 
-
 /**
   UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
 
@@ -57,7 +57,6 @@ UpdatePeiSaPolicyPreMem (
   UINTN                           DataSize;
   EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];
   EFI_BOOT_MODE                   BootMode;
-  UINT8                           MorControl;
   UINT32                          TraceHubTotalMemSize;
   GRAPHICS_PEI_PREMEM_CONFIG      *GtPreMemConfig = NULL;
   MEMORY_CONFIGURATION            *MemConfig = NULL;
@@ -67,15 +66,9 @@ UpdatePeiSaPolicyPreMem (
   OVERCLOCKING_PREMEM_CONFIG      *OcPreMemConfig = NULL;
   VTD_CONFIG                      *Vtd = NULL;
   UINT32                          ProcessorTraceTotalMemSize;
-  UINT16                          AdjustedMmioSize;
-  CPU_FAMILY                      CpuFamilyId;
-  CPU_STEPPING                    CpuStepping;
 
   TraceHubTotalMemSize = 0;
   ProcessorTraceTotalMemSize = 0;
-  AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
-  CpuFamilyId = GetCpuFamily();
-  CpuStepping = GetCpuStepping();
 
   DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdatePeiSaPolicyPreMem\n"));
 
@@ -106,7 +99,6 @@ UpdatePeiSaPolicyPreMem (
   Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *)&Vtd);
   ASSERT_EFI_ERROR(Status);
 
-
   RcompData = MemConfigNoCrc->RcompData;
 
   //
@@ -124,7 +116,6 @@ UpdatePeiSaPolicyPreMem (
   ASSERT_EFI_ERROR(Status);
 
   MiscPeiPreMemConfig->S3DataPtr = NULL;
-  MorControl = 0;
   MiscPeiPreMemConfig->UserBd = 0; // It's a CRB mobile board by default (btCRBMB)
 
   PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform));
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
index 2bba58eed3..09bf3bccfc 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
@@ -227,10 +227,6 @@ InitCommonPlatformPcd (
   )
 {
   PCD64_BLOB Data64;
-  TBT_INFO_HOB  *TbtInfoHob = NULL;
-
-  TbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
-
 
   //
   // Enable EC SMI# for SMI
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
index 978e367cda..5fc61861a6 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -16,7 +16,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
index 97a3fae51b..6dc47984da 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
@@ -15,7 +15,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
index 5104329825..b8c69166ed 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
@@ -6,7 +6,6 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include "BoardFunc.h"
 
 /**
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
index 3a42a9bd03..1944a02bf1 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
@@ -6,7 +6,6 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include <GopConfigLib.h>
 //
 // Null function for nothing GOP VBT update.
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
index 458a73f892..5305ec7f7c 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
@@ -1,17 +1,17 @@
 /** @file
- Source code for the board PCH configuration Pcd init functions for Pre-Mmeory Init phase.
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 #include <GpioPinsCnlLp.h>
 #include <GpioPinsCnlH.h>
 #include <PlatformBoardConfig.h>        // for USB 20 AFE & Root Port Clk Info.
-#include "GpioTableWhlUDdr4PreMem.h"
 #include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
 
 /**
   Board Root Port Clock Info configuration init function for PEI pre-memory phase.
@@ -346,11 +346,11 @@ GpioTablePreMemInit (
   switch (BoardId) {
     case BoardIdWhiskeyLakeRvp:
       PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableWhlUDdr4PreMem);
-      PcdSet16S (PcdBoardGpioTablePreMemSize, sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableWhlUDdr4PreMemSize);
       PcdSet32S (PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOnEarlyPreMem);
-      PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableWhlUDdr4WwanOnEarlyPreMemSize);
       PcdSet32S (PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOffEarlyPreMem);
-      PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableWhlUDdr4WwanOffEarlyPreMemSize);
       break;
 
     default:
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
index 17f12c117d..6c3425b544 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
@@ -6,11 +6,11 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include "BoardSaConfigPreMem.h"
+#include "SaPolicyCommon.h"
+#include "WhiskeylakeURvpInit.h"
 #include <PlatformBoardConfig.h>
 #include <Library/CpuPlatformLib.h>
-#include "SaPolicyCommon.h"
 
 //
 // Display DDI settings for WHL ERB
@@ -74,10 +74,8 @@ MrcConfigInit (
   )
 {
   CPU_FAMILY    CpuFamilyId;
-  CPU_STEPPING  CpuStepping;
 
   CpuFamilyId = GetCpuFamily();
-  CpuStepping = GetCpuStepping();
 
   if (CpuFamilyId == EnumCpuCflDtHalo) {
     PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c
similarity index 98%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h
rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c
index a943d5bd04..e495965a5f 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c
@@ -1,14 +1,10 @@
 /** @file
   GPIO definition table
 
-
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#ifndef _GPIO_TABLE_DEFAULT_H_
-#define _GPIO_TABLE_DEFAULT_H_
-
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
@@ -18,8 +14,7 @@
 //
 // CNL U DRR4 Board GPIO table configuration is used as default
 //
-
-GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =
+GPIO_INIT_CONFIG mGpioTableDefault[] =
 {
 //                      Pmode,  GPI_IS,  GpioDir,  GPIOTxState,  RxEvCfg,  GPIRoutConfig,  PadRstCfg,  Term,
   //{GPIO_CNL_LP_GPP_A0,  { GpioPadModeNotUsed,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermNone }},
@@ -215,11 +210,4 @@ GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =
   //(Default HW)  {GPIO_CNL_LP_GPD11,  { GpioPadModeNative1,  GpioHostOwnGpio,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioResetDefault,  GpioTermNone }},  //LANPHY_EN
   {GPIO_CNL_LP_PECI,  { GpioHardwareDefault,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermWpd20K }}, // 20K PD for PECI
 };
-
-GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemDefault[] =
-{
-  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
-};
-
-#endif
-
+UINT16 mGpioTableDefaultSize = sizeof (mGpioTableDefault) / sizeof (GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c
similarity index 98%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h
rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c
index 86b7cb3717..a082b1ceee 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c
@@ -1,19 +1,16 @@
 /** @file
-  GPIO definition table for WhiskeyLake U Ddr4 RVP
-
+  GPIO definition table for Whiskey Lake U DDR4 RVP
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
+
 **/
 
-#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
-#define _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
-
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
 {
 //                      Pmode,  GPI_IS,  GpioDir,  GPIOTxState,  RxEvCfg,  GPIRoutConfig,  PadRstCfg,  Term,
   //{GPIO_CNL_LP_GPP_A0,  { GpioPadModeNotUsed,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermNone }},
@@ -220,8 +217,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
   //(Default HW)  {GPIO_CNL_LP_GPD11,  { GpioPadModeNative1,  GpioHostOwnGpio,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioResetDefault,  GpioTermNone }},  //LANPHY_EN
   {GPIO_CNL_LP_PECI,  { GpioHardwareDefault,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermWpd20K }}, // 20K PD for PECI
 };
+UINT16 mGpioTableWhlUDdr4_0Size = sizeof (mGpioTableWhlUDdr4_0) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
+GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
   //                       Pmode,                GPI_IS,             GpioDir,        GPIOTxState,    RxEvCfg/GPIRoutConfig,          PadRstCfg,        Term,
   // WiGig start
   {GPIO_CNL_LP_GPP_A16,  { GpioPadModeGpio,      GpioHostOwnGpio,     GpioDirOut,    GpioOutHigh, GpioIntDefault,               GpioPlatformReset,  GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U
@@ -249,8 +247,9 @@ static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,      GpioHostOwnGpio,    GpioDirNone, GpioOutDefault, GpioIntDis,                   GpioPlatformReset,  GpioTermNone   }}  //Unused so disabled / Not used on CNL U
   // Unused end
 };
+UINT16 mGpioTableCflUDdr4Size = sizeof (mGpioTableCflUDdr4) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
   //                       Pmode,                GPI_IS,             GpioDir,        GPIOTxState,    RxEvCfg/GPIRoutConfig,          PadRstCfg,        Term,
   // WiGig start
   {GPIO_CNL_LP_GPP_A16,  { GpioPadModeGpio, GpioHostOwnGpio,     GpioDirOut,    GpioOutHigh, GpioIntDefault,             GpioPlatformReset,  GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U
@@ -278,7 +277,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
   {GPIO_CNL_LP_GPP_F3,   { GpioPadModeGpio, GpioHostOwnGpio,    GpioDirNone, GpioOutDefault, GpioIntDis,                 GpioPlatformReset,  GpioTermWpu20K }}  //Unused so disabled / WF_CLK_EN on CNL U
   // Unused end
 };
-
-
-#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
-
+UINT16 mGpioTableWhlUDdr4Size = sizeof (mGpioTableWhlUDdr4) / sizeof (GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c
similarity index 84%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h
rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c
index 01a6599564..d159f4bd5e 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c
@@ -1,27 +1,25 @@
 /** @file
-  GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory
+  GPIO definition table for Whiskey Lake U DDR4 RVP Pre-Memory
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
 {
   {GPIO_CNL_LP_GPP_C15,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_RST_N
   {GPIO_CNL_LP_GPP_C14,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_PWREN_N
   {GPIO_CNL_LP_GPP_C12,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_RST_N
   {GPIO_CNL_LP_GPP_C13,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutHigh, GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_PWREN_N
 };
+UINT16 mGpioTableWhlUDdr4PreMemSize = sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
 {
   // do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume.
   //{GPIO_CNL_LP_GPP_C15,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_RST_N
@@ -29,9 +27,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
   {GPIO_CNL_LP_GPP_C12,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_RST_N
   {GPIO_CNL_LP_GPP_C13,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutHigh, GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_PWREN_N
 };
+UINT16 mGpioTableWhlTbtRvpPreMemSize = sizeof (mGpioTableWhlTbtRvpPreMem) / sizeof (GPIO_INIT_CONFIG);
 
-
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
 {
   // Turn on WWAN power and de-assert reset pins by default
   {GPIO_CNL_LP_GPP_A11,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}},   //WWAN_WAKE_N
@@ -42,8 +40,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
   {GPIO_CNL_LP_GPP_H16,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_DISABLE_N
 };
+UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
 {
   // Assert reset pins and then turn off WWAN power
   {GPIO_CNL_LP_GPP_A11,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}},   //WWAN_WAKE_N
@@ -54,6 +53,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
   {GPIO_CNL_LP_GPP_H16,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_DISABLE_N
 };
-
-#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-
+UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
index 965110a5a5..915dadbf8c 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
@@ -14,7 +14,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
index a2a6efe506..744864f98f 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
@@ -14,7 +14,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
index 0adbed7f53..98aeff519d 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
@@ -27,7 +27,7 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 
-#include "PeiWhiskeylakeURvpInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 
 #include <ConfigBlock.h>
 #include <ConfigBlock/MemoryConfig.h>
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
index 80b0a97612..71a81f3db2 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
@@ -25,14 +25,12 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 #include <IoExpander.h>
-#include "PeiWhiskeylakeURvpInitLib.h"
-#include "GpioTableDefault.h"
-#include "GpioTableWhlUDdr4.h"
 #include <AttemptUsbFirst.h>
 #include <PeiPlatformHookLib.h>
 #include <Library/PeiPolicyInitLib.h>
 #include <Library/PchInfoLib.h>
 #include <FirwmareConfigurations.h>
+#include "WhiskeylakeURvpInit.h"
 
 EFI_STATUS
 BoardFunctionInit(
@@ -49,7 +47,7 @@ GPIO init function for PEI post memory phase.
 EFI_STATUS
 BoardGpioInit(
   IN UINT16 BoardId
-)
+  )
 {
   //
   // GPIO Table Init.
@@ -57,16 +55,16 @@ BoardGpioInit(
   switch (BoardId) {
 
     case BoardIdWhiskeyLakeRvp:
-      PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableWhlUDdr4_0);
-      PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableWhlUDdr4_0) / sizeof(GPIO_INIT_CONFIG));
-      PcdSet32S(PcdBoardGpioTable2, (UINTN)mGpioTableWhlUDdr4);
-      PcdSet16S(PcdBoardGpioTable2Size, sizeof(mGpioTableWhlUDdr4) / sizeof(GPIO_INIT_CONFIG));
+      PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableWhlUDdr4_0);
+      PcdSet16S (PcdBoardGpioTableSize, mGpioTableWhlUDdr4_0Size);
+      PcdSet32S (PcdBoardGpioTable2, (UINTN) mGpioTableWhlUDdr4);
+      PcdSet16S (PcdBoardGpioTable2Size, mGpioTableWhlUDdr4Size);
       break;
 
     default:
-      DEBUG((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n"));
-      PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableDefault);
-      PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableDefault) / sizeof(GPIO_INIT_CONFIG));
+      DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n"));
+      PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault);
+      PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize);
       break;
   }
 
@@ -148,31 +146,36 @@ BoardSecurityInit (
 }
 
 /**
-WhiskeyLake board configuration init function for PEI post memory phase.
+  Board configuration initialization in the post-memory boot phase.
 
-@param[in]  Content  pointer to the buffer contain init information for board init.
-
-@retval EFI_SUCCESS             The function completed successfully.
-@retval EFI_INVALID_PARAMETER   The parameter is NULL.
 **/
 EFI_STATUS
-BoardConfigInit(
+BoardConfigInit (
   VOID
-)
+  )
 {
   EFI_STATUS  Status;
   UINT16      BoardId;
 
   BoardId = BoardIdWhiskeyLakeRvp;
 
-  Status = BoardGpioInit(BoardId);
-  Status = TouchPanelGpioInit(BoardId);
-  Status = HdaVerbTableInit(BoardId);
-  Status = BoardMiscInit(BoardId);
-  Status = BoardFunctionInit(BoardId);
-  Status = BoardSecurityInit(BoardId);
-
-  return EFI_SUCCESS;
+  Status = BoardGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = TouchPanelGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = HdaVerbTableInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardFunctionInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardSecurityInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
 }
 
 //@todo Review this functionality and if it is required for WHL SDS
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
index 519a5be216..0124888244 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
@@ -27,7 +27,7 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 
-#include "PeiWhiskeylakeURvpInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 #include <ConfigBlock.h>
 #include <ConfigBlock/MemoryConfig.h>
 #include <Library/PeiServicesLib.h>
@@ -274,36 +274,51 @@ EarlyPlatformPchInit(
 }
 
 /**
-Board init function for PEI pre-memory phase.
+  Board configuration initialization in the pre-memory boot phase.
 
-@param  Content  pointer to the buffer contain init information for board init.
-
-@retval EFI_SUCCESS             The function completed successfully.
-@retval EFI_INVALID_PARAMETER   The parameter is NULL.
 **/
-EFI_STATUS
-BoardConfigInitPreMem(
+VOID
+BoardConfigInitPreMem (
   VOID
-)
+  )
 {
   EFI_STATUS Status;
   UINT16 BoardId;
 
   BoardId = BoardIdWhiskeyLakeRvp;
 
-  Status = MrcConfigInit(BoardId);
-  Status = SaGpioConfigInit(BoardId);
-  Status = SaMiscConfigInit(BoardId);
-  Status = RootPortClkInfoInit(BoardId);
-  Status = UsbConfigInit(BoardId);
-  Status = GpioGroupTierInit(BoardId);
-  Status = GpioTablePreMemInit(BoardId);
-  Status = PchPmConfigInit(BoardId);
-  Status = BoardMiscInitPreMem(BoardId);
-  Status = SaDisplayConfigInit(BoardId);
-  Status = BoardFunctionInitPreMem(BoardId);
-
-  return EFI_SUCCESS;
+  Status = MrcConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaGpioConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaMiscConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = RootPortClkInfoInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = UsbConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioGroupTierInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioTablePreMemInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PchPmConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInitPreMem (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaDisplayConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardFunctionInitPreMem (BoardId);
+  ASSERT_EFI_ERROR (Status);
 }
 
 /**
@@ -328,7 +343,6 @@ PlatformInitPreMemCallBack(
   EFI_STATUS                        Status;
   UINT16                            ABase;
   UINT8                             FwConfig;
-  UINT8                             SynchDelay;
 
   //
   // Init Board Config Pcd.
@@ -337,7 +351,6 @@ PlatformInitPreMemCallBack(
 
   DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
   FwConfig = FwConfigProduction;
-  SynchDelay = 0;
   PcdSetBoolS(PcdPcieWwanEnable, FALSE);
   PcdSetBoolS(PcdWwanResetWorkaround, FALSE);
 
@@ -586,18 +599,16 @@ WhiskeylakeURvpBoardDebugInit (
   VOID
   )
 {
-  UINT64                            LpcBaseAddress;
-
   ///
   /// LPC I/O Configuration
   ///
-  PchLpcIoDecodeRangesSet(
+  PchLpcIoDecodeRangesSet (
     (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
     (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
     (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
-  );
+    );
 
-  PchLpcIoEnableDecodingSet(
+  PchLpcIoEnableDecodingSet (
     B_LPC_CFG_IOE_ME2 |
     B_LPC_CFG_IOE_SE |
     B_LPC_CFG_IOE_ME1 |
@@ -608,18 +619,7 @@ WhiskeylakeURvpBoardDebugInit (
     B_LPC_CFG_IOE_PPE |
     B_LPC_CFG_IOE_CBE |
     B_LPC_CFG_IOE_CAE
-  );
-
-  ///
-  /// Enable LPC IO decode for EC access
-  ///
-  LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS(
-    DEFAULT_PCI_SEGMENT_NUMBER_PCH,
-    DEFAULT_PCI_BUS_NUMBER_PCH,
-    PCI_DEVICE_NUMBER_PCH_LPC,
-    PCI_FUNCTION_NUMBER_PCH_LPC,
-    0
-  );
+    );
 
   return EFI_SUCCESS;
 }
-- 
2.16.2.windows.1


      parent reply	other threads:[~2019-08-28  4:09 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28  4:09 [edk2-platforms][PATCH V4 0/2] Fix Whiskey Lake GCC Build Failures Kubacki, Michael A
2019-08-28  4:09 ` [edk2-platforms][PATCH V4 1/2] CoffeelakeSiliconPkg: Fix " Kubacki, Michael A
2019-08-28  4:09 ` Kubacki, Michael A [this message]

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