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* [PATCH 1/1] Platform: Intel: Update licenses to SPDX and update clock settings
@ 2019-09-04  5:35 Loh, Tien Hock
  2019-09-04 12:58 ` Ard Biesheuvel
  0 siblings, 1 reply; 2+ messages in thread
From: Loh, Tien Hock @ 2019-09-04  5:35 UTC (permalink / raw)
  To: devel, thloh85
  Cc: Tien Hock, Loh, Ard Biesheuvel, Leif Lindholm, Michael D Kinney

From: "Tien Hock, Loh" <tien.hock.loh@intel.com>

Update all license to SPDX. Also update UART clock to be calculated instead
of hardcoded, removed some unused packages, and updated maintainers.

Signed-off-by: "Tien Hock, Loh" <tien.hock.loh@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 Platform/Intel/Stratix10/Stratix10SoCPkg.dec                                  |   3 +-
 Platform/Intel/Stratix10/Stratix10SoCPkg.dsc                                  |  15 ++-
 Platform/Intel/Stratix10/Stratix10SoCPkg.fdf                                  |   1 -
 Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf        |  22 ++--
 Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf        |  94 +++++++-------
 Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf          |  41 ++++++
 Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf          |  34 +++++
 Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h    |  48 +++++++
 Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c          |  22 ++--
 Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c              |  20 ++-
 Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c      |  19 +--
 Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c            |  43 +++++++
 Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c            | 133 ++++++++++++++++++++
 Maintainers.txt                                                               |   5 +
 Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S |   8 +-
 15 files changed, 391 insertions(+), 117 deletions(-)

diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
index 7c44670d591d..346f7f9a042b 100755
--- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
+++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
@@ -10,7 +10,8 @@ [Defines]
   PACKAGE_GUID                   = 45533DD0-C41F-4ab6-A5DF-65B52684AC60
   PACKAGE_VERSION                = 0.1
 
-[Includes.common]
+[Includes]
+  Include
 
 [Guids.common]
   gStratix10SocFpgaTokenSpaceGuid = { 0x0fe272eb, 0xb2cf, 0x4390, { 0xa5, 0xc4, 0x60, 0x13, 0x2c, 0x6b, 0xd0, 0x34 } }
diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
index 17d0c5baadc6..d3ad0eba7e75 100755
--- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
+++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
@@ -27,6 +27,8 @@ [Defines]
 # Pcd Section - list of all EDK II PCD Entries defined by this Platform
 #
 ################################################################################
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|184320
 
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
@@ -103,7 +105,6 @@ [PcdsFixedAtBuild.common]
   #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
   #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
   #  DEBUG_ERROR     0x80000000  // Error
-#  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803010CF
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
 
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x00
@@ -227,7 +228,8 @@ [LibraryClasses.common]
   SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
 
   SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
-  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+  PlatformHookLib|Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
+  S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
 
   SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
   UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -251,7 +253,6 @@ [LibraryClasses.common]
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-#  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
   CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
 
   #
@@ -414,7 +415,6 @@ [Components.common]
   #
   MdeModulePkg/Core/Dxe/DxeMain.inf {
     <LibraryClasses>
-      #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
       NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
   }
 
@@ -475,7 +475,6 @@ [Components.common]
       NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
       NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
       NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
-#      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
       HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
       PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
       BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
@@ -487,9 +486,13 @@ [Components.common]
   }
 
   #
-  # Platform Specific Init for DXE phase
+  # Platform Specific Init
   #
   Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
+  Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf {
+    <LibraryClasses>
+    S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
+  }
 
 [BuildOptions]
   #-------------------------------
diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf b/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
index 2c4e5ee887ca..1ac2da28addf 100755
--- a/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
+++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
@@ -140,7 +140,6 @@ [FV.FV_DXE]
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
   INF MdeModulePkg/Application/UiApp/UiApp.inf
-  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
 
   # FV Filesystem
diff --git a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
index 64b398969f1e..b16d93f22058 100644
--- a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
+++ b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
@@ -1,18 +1,12 @@
-#/** @file
-#
-#  Copyright (c) 2019, Intel All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
 
+### @file
+#
+#  Intel Stratix 10 Platform
+#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+###
+
 [Defines]
   INF_VERSION                    = 0x0001001B
   BASE_NAME                      = IntelPlatformDxe
diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf b/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
index ef5c06aede7f..88f343511b41 100644
--- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
+++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
@@ -1,49 +1,45 @@
-/** @file
-*
-*  Stratix 10 Platform Library
-*
-*  Copyright (c) 2019, Intel Corporations All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-[Defines]
-  INF_VERSION                    = 0x0001001B
-  BASE_NAME                      = Stratix10PlatformLib
-  FILE_GUID                      = 99E236C7-D5FD-42A0-B520-60C85C4870B8
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmPlatformLib
-
-[Packages]
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  ArmPkg/ArmPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
-
-[LibraryClasses]
-  ArmLib
-  ArmMmuLib
-  DebugLib
-  IoLib
-  PcdLib
-
-[Sources.common]
-  Stratix10PlatformLib.c
-  Stratix10Mmu.c
-
-[Sources.AArch64]
-  AArch64/ArmPlatformHelper.S
-
-[FixedPcd]
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-  gArmTokenSpaceGuid.PcdArmPrimaryCore
-
+### @file
+#
+#  Stratix 10 Platform Library
+#  Copyright (c) 2019, Intel Corporation All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+###
+
+[Defines]
+  INF_VERSION                    = 0x0001001B
+  BASE_NAME                      = Stratix10PlatformLib
+  FILE_GUID                      = 99E236C7-D5FD-42A0-B520-60C85C4870B8
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmMmuLib
+  DebugLib
+  PlatformHookLib
+  IoLib
+  PcdLib
+
+[Sources.common]
+  Stratix10PlatformLib.c
+  Stratix10Mmu.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate       ## PRODUCES
+
diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
new file mode 100644
index 000000000000..dc18db7c5444
--- /dev/null
+++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
@@ -0,0 +1,41 @@
+## @file
+#  Platform Hook Library instance for UART device.
+#
+#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001B
+  BASE_NAME                      = PlatformHookLib
+  FILE_GUID                      = 90A73C58-A6E3-4EED-A1A3-6F9C7C3D998F
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformHookLib
+  CONSTRUCTOR                    = PlatformHookSerialPortInitialize
+
+[Sources]
+  PlatformHookLib.c
+
+[LibraryClasses]
+  PcdLib
+  PciLib
+  S10ClockManager
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
+  UefiPayloadPkg/UefiPayloadPkg.dec
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio         ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase    ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate        ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate       ## PRODUCES
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate         ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters   ## PRODUCES
+
diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
new file mode 100644
index 000000000000..c0eccd304810
--- /dev/null
+++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
@@ -0,0 +1,34 @@
+## @file
+#  Clock Manager Library instance
+#
+#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001B
+  BASE_NAME                      = S10ClockManagerLib
+  FILE_GUID                      = 90A73C58-A6E3-4EED-A1A3-6F9C7C3E998F
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = S10ClockManagerLib
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmMmuLib
+  DebugLib
+  IoLib
+  PcdLib
+
+[Sources]
+  S10ClockManager.c
+
diff --git a/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h
new file mode 100644
index 000000000000..f081a70a7a11
--- /dev/null
+++ b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h
@@ -0,0 +1,48 @@
+/** @file
+Stratix 10 Clock Manager header
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _S10_CLOCK_MANAGER_
+#define _S10_CLOCK_MANAGER_
+#define CLOCK_MANAGER_MAINPLL                      0xffd10030
+#define CLOCK_MANAGER_MAINPLL_NOCCLK               0x4c
+
+#define CLOCK_MANAGER_PERPLL                       0xffd100a4
+#define CLOCK_MANAGER_MAINPLL_PLLGLOB              0x44
+#define CLOCK_MANAGER_PERPLL_PLLGLOB               0x40
+#define CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(x)      (((x) >> 16) & 3)
+#define CLOCK_MANAGER_CNTR6CLK                     0x4c
+#define CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1           0
+#define CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC          1
+#define CLOCK_MANAGER_PLLGLOB_PSRC_F2S             2
+#define CLOCK_MANAGER_SRC                          16
+#define CLOCK_MANAGER_SRC_MSK                      0x7
+#define CLOCK_MANAGER_SRC_MAIN                     (0)
+#define CLOCK_MANAGER_SRC_PERI                     (1)
+#define CLOCK_MANAGER_SRC_OSC1                     (2)
+#define CLOCK_MANAGER_SRC_INTOSC                   (3)
+#define CLOCK_MANAGER_SRC_FPGA                     (4)
+#define CLOCK_MANAGER_FDBCK                        0x44
+#define CLOCK_MANAGER_FDBCK_MDIV(x)                ((x) >> 24 & 0xff)
+#define CLOCK_MANAGER_PERPLL_FDBCK                 0x48
+#define CLOCK_MANAGER_CNT_MSK                      0x3ff
+#define CLOCK_MANAGER_PERPLL_CNTR6CLK              0x28
+#define CLOCK_MANAGER_PLLGLOB_REFCLKDIV(x)         (((x) >> 8) & 0x3f)
+#define CLOCK_MANAGER_PLLC1_DIV(x)                 ((x) & 0x7f)
+#define CLOCK_MANAGER_PLLC1                        0x54
+#define CLOCK_MANAGER_NOCDIV_L4SPCLK(x)            ((x) >> 16 & 0x3)
+#define CLOCK_MANAGER_MAINPLL_NOCDIV               0x40
+
+#define S10_SYSTEM_MANAGER                         0xffd12000
+#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1       0x204
+#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2       0x208
+#define S10_CLOCK_INTOSC                           460000000
+
+UINT32 S10ClockManagerGetMmcClock();
+UINT32 S10ClockManagerGetUartClock();
+
+#endif
diff --git a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
index 144b4c54ef55..b762fdc69ca4 100644
--- a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
+++ b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
@@ -1,16 +1,12 @@
-/** @file
-*
-*  Copyright (c) 2019, Intel All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
+/** @file
+
+  Stratix 10 Platform Entry code
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
 
 
 #include <Uefi.h>
diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
index 892387bf5d07..73ea1b423567 100644
--- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
+++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
@@ -1,17 +1,11 @@
 /** @file
-*
-*  Stratix 10 Mmu configuration
-*
-*  Copyright (c) 2019, Intel Corporations All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
+
+  Stratix 10 Mmu configuration
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
 **/
 
 #include <Library/ArmLib.h>
diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
index 8ac30559362d..dc10716361b1 100644
--- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
+++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
@@ -1,17 +1,10 @@
 /** @file
-*
-*  Stratix 10 Platform Library
-*
-*  Copyright (c) 2019, Intel Corporations All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
+  Stratix 10 Platform Library
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
 **/
 
 #include <Library/ArmLib.h>
diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c
new file mode 100644
index 000000000000..a204718909df
--- /dev/null
+++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c
@@ -0,0 +1,43 @@
+/** @file
+  Platform Hook Library
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/S10ClockManager/S10ClockManager.h>
+
+/**
+  Performs platform specific initialization required for the CPU to access
+  the hardware associated with a SerialPortLib instance.  This function does
+  not initialize the serial port hardware itself.  Instead, it initializes
+  hardware devices that are required for the CPU to access the serial port
+  hardware.  This function may be called more than once.
+
+  @retval RETURN_SUCCESS       The platform specific initialization succeeded.
+  @retval RETURN_DEVICE_ERROR  The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+  VOID
+  )
+{
+  RETURN_STATUS Status;
+
+  Status = PcdSet32S (PcdSerialClockRate, S10ClockManagerGetUartClock());
+
+  if (RETURN_ERROR (Status)) {
+    return Status;
+  }
+
+  return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c
new file mode 100644
index 000000000000..5e6fe283646d
--- /dev/null
+++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c
@@ -0,0 +1,133 @@
+/** @file
+Stratix 10 Clock Manager
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/IoLib.h>
+#include <Library/S10ClockManager/S10ClockManager.h>
+
+UINT32
+S10ClockManagerGetPerClock() {
+  UINT32 PllGlob, MDiv, RefClkDiv, RefClk;
+
+  PllGlob = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_PLLGLOB);
+
+  switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) {
+  case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1:
+    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
+    RefClk = 2500000;
+    break;
+  case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC:
+    RefClk = S10_CLOCK_INTOSC;
+    break;
+  case CLOCK_MANAGER_PLLGLOB_PSRC_F2S:
+    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
+    RefClk = 5000000;
+    break;
+  }
+
+  RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob);
+
+  MDiv = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_FDBCK);
+
+  return (RefClk / RefClkDiv) * (6 + MDiv);
+}
+
+UINT32
+S10ClockManagerGetMainClock() {
+  UINT32 PllGlob, MDiv, RefClkDiv, RefClk;
+
+  PllGlob = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_PLLGLOB);
+
+  switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) {
+  case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1:
+    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
+    RefClk = 2500000;
+    break;
+  case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC:
+    RefClk = S10_CLOCK_INTOSC;
+    break;
+  case CLOCK_MANAGER_PLLGLOB_PSRC_F2S:
+    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
+    RefClk = 5000000;
+    break;
+  }
+
+  RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob);
+  MDiv = CLOCK_MANAGER_FDBCK_MDIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PERPLL_FDBCK));
+
+  return (RefClk / RefClkDiv) * (6 + MDiv);
+}
+
+INTN
+S10ClockManagerGetL3MainClock() {
+  UINT32 Clock;
+  UINT32 ClockSrc = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK);
+
+  ClockSrc = (ClockSrc >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK;
+
+  switch (ClockSrc) {
+  case CLOCK_MANAGER_SRC_MAIN:
+    Clock = S10ClockManagerGetMainClock() /
+      CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PLLC1));
+    break;
+  case CLOCK_MANAGER_SRC_PERI:
+    Clock = S10ClockManagerGetPerClock() /
+      CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PLLC1));
+    break;
+  case CLOCK_MANAGER_SRC_OSC1:
+    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
+    break;
+  case CLOCK_MANAGER_SRC_INTOSC:
+    Clock = S10_CLOCK_INTOSC;
+    break;
+  case CLOCK_MANAGER_SRC_FPGA:
+    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
+    break;
+  }
+
+  Clock /= 1 + (MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK) & CLOCK_MANAGER_CNT_MSK);
+
+  return Clock;
+}
+
+UINT32
+S10ClockManagerGetUartClock() {
+  return  S10ClockManagerGetL3MainClock() /
+             (1 << (CLOCK_MANAGER_NOCDIV_L4SPCLK(MmioRead32(CLOCK_MANAGER_MAINPLL_NOCDIV))));
+}
+
+UINT32
+S10ClockManagerGetMmcClock() {
+  UINT32 Clock = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK);
+
+  Clock = (Clock >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK;
+
+  switch (Clock) {
+  case CLOCK_MANAGER_SRC_MAIN:
+    Clock = S10ClockManagerGetL3MainClock();
+    Clock /=  1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) &
+      CLOCK_MANAGER_CNT_MSK);
+    break;
+  case CLOCK_MANAGER_SRC_PERI:
+    Clock = S10ClockManagerGetPerClock();
+    Clock /=  1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) &
+      CLOCK_MANAGER_CNT_MSK);
+    break;
+  case CLOCK_MANAGER_SRC_OSC1:
+    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
+    break;
+  case CLOCK_MANAGER_SRC_INTOSC:
+    Clock = S10_CLOCK_INTOSC;
+    break;
+  case CLOCK_MANAGER_SRC_FPGA:
+    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
+    break;
+  }
+
+  return Clock / 4;
+}
+
diff --git a/Maintainers.txt b/Maintainers.txt
index 876ae5612ad8..47d58ffa0b2c 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -98,6 +98,11 @@ M: Shifei A Lu <shifei.a.lu@intel.com>
 M: Xiaohu Zhou <bowen.zhou@intel.com>
 M: Isaac W Oram <isaac.w.oram@intel.com>
 
+Platform/Intel/Stratix10SocPkg
+M: Leif Lindholm <leif.lindholm@linaro.org>
+M: Michael D Kinney <michael.d.kinney@intel.com>
+R: Tien Hock Loh <tien.hock.loh@intel.com>
+
 Platform/Intel/Tools
 M: Bob Feng <bob.c.feng@intel.com>
 M: Liming Gao <liming.gao@intel.com>
diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
index 2f4cf95cbf13..b7c6dbdc2e61 100644
--- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
+++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,13 +1,7 @@
 //
 //  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
 //
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 //
 
-- 
2.19.0


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH 1/1] Platform: Intel: Update licenses to SPDX and update clock settings
  2019-09-04  5:35 [PATCH 1/1] Platform: Intel: Update licenses to SPDX and update clock settings Loh, Tien Hock
@ 2019-09-04 12:58 ` Ard Biesheuvel
  0 siblings, 0 replies; 2+ messages in thread
From: Ard Biesheuvel @ 2019-09-04 12:58 UTC (permalink / raw)
  To: Loh Tien Hock
  Cc: edk2-devel-groups-io, thloh85, Leif Lindholm, Michael D Kinney

On Tue, 3 Sep 2019 at 22:36, <tien.hock.loh@intel.com> wrote:
>
> From: "Tien Hock, Loh" <tien.hock.loh@intel.com>
>
> Update all license to SPDX. Also update UART clock to be calculated instead
> of hardcoded, removed some unused packages, and updated maintainers.
>

Please split this into 4 patches

> Signed-off-by: "Tien Hock, Loh" <tien.hock.loh@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> ---
>  Platform/Intel/Stratix10/Stratix10SoCPkg.dec                                  |   3 +-
>  Platform/Intel/Stratix10/Stratix10SoCPkg.dsc                                  |  15 ++-
>  Platform/Intel/Stratix10/Stratix10SoCPkg.fdf                                  |   1 -
>  Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf        |  22 ++--
>  Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf        |  94 +++++++-------
>  Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf          |  41 ++++++
>  Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf          |  34 +++++
>  Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h    |  48 +++++++
>  Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c          |  22 ++--
>  Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c              |  20 ++-
>  Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c      |  19 +--
>  Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c            |  43 +++++++
>  Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c            | 133 ++++++++++++++++++++
>  Maintainers.txt                                                               |   5 +
>  Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S |   8 +-
>  15 files changed, 391 insertions(+), 117 deletions(-)
>
> diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> index 7c44670d591d..346f7f9a042b 100755
> --- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> +++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> @@ -10,7 +10,8 @@ [Defines]
>    PACKAGE_GUID                   = 45533DD0-C41F-4ab6-A5DF-65B52684AC60
>    PACKAGE_VERSION                = 0.1
>
> -[Includes.common]
> +[Includes]
> +  Include
>
>  [Guids.common]
>    gStratix10SocFpgaTokenSpaceGuid = { 0x0fe272eb, 0xb2cf, 0x4390, { 0xa5, 0xc4, 0x60, 0x13, 0x2c, 0x6b, 0xd0, 0x34 } }
> diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
> index 17d0c5baadc6..d3ad0eba7e75 100755
> --- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
> +++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc
> @@ -27,6 +27,8 @@ [Defines]
>  # Pcd Section - list of all EDK II PCD Entries defined by this Platform
>  #
>  ################################################################################
> +[PcdsPatchableInModule.common]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|184320
>
>  [PcdsFixedAtBuild.common]
>    gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> @@ -103,7 +105,6 @@ [PcdsFixedAtBuild.common]
>    #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
>    #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
>    #  DEBUG_ERROR     0x80000000  // Error
> -#  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803010CF
>    gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
>
>    gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x00
> @@ -227,7 +228,8 @@ [LibraryClasses.common]
>    SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
>
>    SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> -  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
> +  PlatformHookLib|Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
> +  S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
>
>    SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
>    UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> @@ -251,7 +253,6 @@ [LibraryClasses.common]
>    PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>
>    CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> -#  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
>    CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
>
>    #
> @@ -414,7 +415,6 @@ [Components.common]
>    #
>    MdeModulePkg/Core/Dxe/DxeMain.inf {
>      <LibraryClasses>
> -      #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>        NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
>    }
>
> @@ -475,7 +475,6 @@ [Components.common]
>        NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
>        NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
>        NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> -#      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
>        HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
>        PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>        BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> @@ -487,9 +486,13 @@ [Components.common]
>    }
>
>    #
> -  # Platform Specific Init for DXE phase
> +  # Platform Specific Init
>    #
>    Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
> +  Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf {
> +    <LibraryClasses>
> +    S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
> +  }
>
>  [BuildOptions]
>    #-------------------------------
> diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf b/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
> index 2c4e5ee887ca..1ac2da28addf 100755
> --- a/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
> +++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.fdf
> @@ -140,7 +140,6 @@ [FV.FV_DXE]
>    INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
>    INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>    INF MdeModulePkg/Application/UiApp/UiApp.inf
> -  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
>    INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
>
>    # FV Filesystem
> diff --git a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
> index 64b398969f1e..b16d93f22058 100644
> --- a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
> +++ b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf
> @@ -1,18 +1,12 @@
> -#/** @file
> -#
> -#  Copyright (c) 2019, Intel All rights reserved.
> -#
> -#  This program and the accompanying materials
> -#  are licensed and made available under the terms and conditions of the BSD License
> -#  which accompanies this distribution.  The full text of the license may be found at
> -#  http://opensource.org/licenses/bsd-license.php
> -#
> -#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> -#
> -#
> -#**/
>
> +### @file
> +#
> +#  Intel Stratix 10 Platform
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +###
> +
>  [Defines]
>    INF_VERSION                    = 0x0001001B
>    BASE_NAME                      = IntelPlatformDxe
> diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf b/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
> index ef5c06aede7f..88f343511b41 100644
> --- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
> +++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/IntelPlatformLib.inf
> @@ -1,49 +1,45 @@
> -/** @file
> -*
> -*  Stratix 10 Platform Library
> -*
> -*  Copyright (c) 2019, Intel Corporations All rights reserved.
> -*
> -*  This program and the accompanying materials
> -*  are licensed and made available under the terms and conditions of the BSD License
> -*  which accompanies this distribution.  The full text of the license may be found at
> -*  http://opensource.org/licenses/bsd-license.php
> -*
> -*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> -*
> -**/
> -
> -[Defines]
> -  INF_VERSION                    = 0x0001001B
> -  BASE_NAME                      = Stratix10PlatformLib
> -  FILE_GUID                      = 99E236C7-D5FD-42A0-B520-60C85C4870B8
> -  MODULE_TYPE                    = BASE
> -  VERSION_STRING                 = 1.0
> -  LIBRARY_CLASS                  = ArmPlatformLib
> -
> -[Packages]
> -  ArmPlatformPkg/ArmPlatformPkg.dec
> -  ArmPkg/ArmPkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
> -  MdePkg/MdePkg.dec
> -  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> -
> -[LibraryClasses]
> -  ArmLib
> -  ArmMmuLib
> -  DebugLib
> -  IoLib
> -  PcdLib
> -
> -[Sources.common]
> -  Stratix10PlatformLib.c
> -  Stratix10Mmu.c
> -
> -[Sources.AArch64]
> -  AArch64/ArmPlatformHelper.S
> -
> -[FixedPcd]
> -  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> -  gArmTokenSpaceGuid.PcdArmPrimaryCore
> -
> +### @file
> +#
> +#  Stratix 10 Platform Library
> +#  Copyright (c) 2019, Intel Corporation All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +###
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001B
> +  BASE_NAME                      = Stratix10PlatformLib
> +  FILE_GUID                      = 99E236C7-D5FD-42A0-B520-60C85C4870B8
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = ArmPlatformLib
> +
> +[Packages]
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  ArmPkg/ArmPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  ArmMmuLib
> +  DebugLib
> +  PlatformHookLib
> +  IoLib
> +  PcdLib
> +
> +[Sources.common]
> +  Stratix10PlatformLib.c
> +  Stratix10Mmu.c
> +
> +[Sources.AArch64]
> +  AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +  gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> +[Pcd]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate       ## PRODUCES
> +
> diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
> new file mode 100644
> index 000000000000..dc18db7c5444
> --- /dev/null
> +++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf
> @@ -0,0 +1,41 @@
> +## @file
> +#  Platform Hook Library instance for UART device.
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001B
> +  BASE_NAME                      = PlatformHookLib
> +  FILE_GUID                      = 90A73C58-A6E3-4EED-A1A3-6F9C7C3D998F
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = PlatformHookLib
> +  CONSTRUCTOR                    = PlatformHookSerialPortInitialize
> +
> +[Sources]
> +  PlatformHookLib.c
> +
> +[LibraryClasses]
> +  PcdLib
> +  PciLib
> +  S10ClockManager
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> +  UefiPayloadPkg/UefiPayloadPkg.dec
> +
> +[Pcd]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio         ## PRODUCES
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase    ## PRODUCES
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate        ## PRODUCES
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate       ## PRODUCES
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate         ## PRODUCES
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters   ## PRODUCES
> +
> diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
> new file mode 100644
> index 000000000000..c0eccd304810
> --- /dev/null
> +++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf
> @@ -0,0 +1,34 @@
> +## @file
> +#  Clock Manager Library instance
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001B
> +  BASE_NAME                      = S10ClockManagerLib
> +  FILE_GUID                      = 90A73C58-A6E3-4EED-A1A3-6F9C7C3E998F
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = S10ClockManagerLib
> +
> +[Packages]
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  ArmPkg/ArmPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  Platform/Intel/Stratix10/Stratix10SoCPkg.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  ArmMmuLib
> +  DebugLib
> +  IoLib
> +  PcdLib
> +
> +[Sources]
> +  S10ClockManager.c
> +
> diff --git a/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h
> new file mode 100644
> index 000000000000..f081a70a7a11
> --- /dev/null
> +++ b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h
> @@ -0,0 +1,48 @@
> +/** @file
> +Stratix 10 Clock Manager header
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _S10_CLOCK_MANAGER_
> +#define _S10_CLOCK_MANAGER_
> +#define CLOCK_MANAGER_MAINPLL                      0xffd10030
> +#define CLOCK_MANAGER_MAINPLL_NOCCLK               0x4c
> +
> +#define CLOCK_MANAGER_PERPLL                       0xffd100a4
> +#define CLOCK_MANAGER_MAINPLL_PLLGLOB              0x44
> +#define CLOCK_MANAGER_PERPLL_PLLGLOB               0x40
> +#define CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(x)      (((x) >> 16) & 3)
> +#define CLOCK_MANAGER_CNTR6CLK                     0x4c
> +#define CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1           0
> +#define CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC          1
> +#define CLOCK_MANAGER_PLLGLOB_PSRC_F2S             2
> +#define CLOCK_MANAGER_SRC                          16
> +#define CLOCK_MANAGER_SRC_MSK                      0x7
> +#define CLOCK_MANAGER_SRC_MAIN                     (0)
> +#define CLOCK_MANAGER_SRC_PERI                     (1)
> +#define CLOCK_MANAGER_SRC_OSC1                     (2)
> +#define CLOCK_MANAGER_SRC_INTOSC                   (3)
> +#define CLOCK_MANAGER_SRC_FPGA                     (4)
> +#define CLOCK_MANAGER_FDBCK                        0x44
> +#define CLOCK_MANAGER_FDBCK_MDIV(x)                ((x) >> 24 & 0xff)
> +#define CLOCK_MANAGER_PERPLL_FDBCK                 0x48
> +#define CLOCK_MANAGER_CNT_MSK                      0x3ff
> +#define CLOCK_MANAGER_PERPLL_CNTR6CLK              0x28
> +#define CLOCK_MANAGER_PLLGLOB_REFCLKDIV(x)         (((x) >> 8) & 0x3f)
> +#define CLOCK_MANAGER_PLLC1_DIV(x)                 ((x) & 0x7f)
> +#define CLOCK_MANAGER_PLLC1                        0x54
> +#define CLOCK_MANAGER_NOCDIV_L4SPCLK(x)            ((x) >> 16 & 0x3)
> +#define CLOCK_MANAGER_MAINPLL_NOCDIV               0x40
> +
> +#define S10_SYSTEM_MANAGER                         0xffd12000
> +#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1       0x204
> +#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2       0x208
> +#define S10_CLOCK_INTOSC                           460000000
> +
> +UINT32 S10ClockManagerGetMmcClock();
> +UINT32 S10ClockManagerGetUartClock();
> +
> +#endif
> diff --git a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
> index 144b4c54ef55..b762fdc69ca4 100644
> --- a/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
> +++ b/Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.c
> @@ -1,16 +1,12 @@
> -/** @file
> -*
> -*  Copyright (c) 2019, Intel All rights reserved.
> -*
> -*  This program and the accompanying materials
> -*  are licensed and made available under the terms and conditions of the BSD License
> -*  which accompanies this distribution.  The full text of the license may be found at
> -*  http://opensource.org/licenses/bsd-license.php
> -*
> -*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> -*
> -**/
> +/** @file
> +
> +  Stratix 10 Platform Entry code
> +
> +  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
>
>
>  #include <Uefi.h>
> diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
> index 892387bf5d07..73ea1b423567 100644
> --- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
> +++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10Mmu.c
> @@ -1,17 +1,11 @@
>  /** @file
> -*
> -*  Stratix 10 Mmu configuration
> -*
> -*  Copyright (c) 2019, Intel Corporations All rights reserved.
> -*
> -*  This program and the accompanying materials
> -*  are licensed and made available under the terms and conditions of the BSD License
> -*  which accompanies this distribution.  The full text of the license may be found at
> -*  http://opensource.org/licenses/bsd-license.php
> -*
> -*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> -*
> +
> +  Stratix 10 Mmu configuration
> +
> +  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
>  **/
>
>  #include <Library/ArmLib.h>
> diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
> index 8ac30559362d..dc10716361b1 100644
> --- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
> +++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/Stratix10PlatformLib.c
> @@ -1,17 +1,10 @@
>  /** @file
> -*
> -*  Stratix 10 Platform Library
> -*
> -*  Copyright (c) 2019, Intel Corporations All rights reserved.
> -*
> -*  This program and the accompanying materials
> -*  are licensed and made available under the terms and conditions of the BSD License
> -*  which accompanies this distribution.  The full text of the license may be found at
> -*  http://opensource.org/licenses/bsd-license.php
> -*
> -*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> -*
> +  Stratix 10 Platform Library
> +
> +  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
>  **/
>
>  #include <Library/ArmLib.h>
> diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c
> new file mode 100644
> index 000000000000..a204718909df
> --- /dev/null
> +++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c
> @@ -0,0 +1,43 @@
> +/** @file
> +  Platform Hook Library
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Uefi/UefiBaseType.h>
> +#include <Library/PlatformHookLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/S10ClockManager/S10ClockManager.h>
> +
> +/**
> +  Performs platform specific initialization required for the CPU to access
> +  the hardware associated with a SerialPortLib instance.  This function does
> +  not initialize the serial port hardware itself.  Instead, it initializes
> +  hardware devices that are required for the CPU to access the serial port
> +  hardware.  This function may be called more than once.
> +
> +  @retval RETURN_SUCCESS       The platform specific initialization succeeded.
> +  @retval RETURN_DEVICE_ERROR  The platform specific initialization could not be completed.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PlatformHookSerialPortInitialize (
> +  VOID
> +  )
> +{
> +  RETURN_STATUS Status;
> +
> +  Status = PcdSet32S (PcdSerialClockRate, S10ClockManagerGetUartClock());
> +
> +  if (RETURN_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  return RETURN_SUCCESS;
> +}
> diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c
> new file mode 100644
> index 000000000000..5e6fe283646d
> --- /dev/null
> +++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c
> @@ -0,0 +1,133 @@
> +/** @file
> +Stratix 10 Clock Manager
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/IoLib.h>
> +#include <Library/S10ClockManager/S10ClockManager.h>
> +
> +UINT32
> +S10ClockManagerGetPerClock() {
> +  UINT32 PllGlob, MDiv, RefClkDiv, RefClk;
> +
> +  PllGlob = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_PLLGLOB);
> +
> +  switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) {
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1:
> +    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
> +    RefClk = 2500000;
> +    break;
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC:
> +    RefClk = S10_CLOCK_INTOSC;
> +    break;
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_F2S:
> +    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
> +    RefClk = 5000000;
> +    break;
> +  }
> +
> +  RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob);
> +
> +  MDiv = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_FDBCK);
> +
> +  return (RefClk / RefClkDiv) * (6 + MDiv);
> +}
> +
> +UINT32
> +S10ClockManagerGetMainClock() {
> +  UINT32 PllGlob, MDiv, RefClkDiv, RefClk;
> +
> +  PllGlob = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_PLLGLOB);
> +
> +  switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) {
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1:
> +    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
> +    RefClk = 2500000;
> +    break;
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC:
> +    RefClk = S10_CLOCK_INTOSC;
> +    break;
> +  case CLOCK_MANAGER_PLLGLOB_PSRC_F2S:
> +    RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
> +    RefClk = 5000000;
> +    break;
> +  }
> +
> +  RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob);
> +  MDiv = CLOCK_MANAGER_FDBCK_MDIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PERPLL_FDBCK));
> +
> +  return (RefClk / RefClkDiv) * (6 + MDiv);
> +}
> +
> +INTN
> +S10ClockManagerGetL3MainClock() {
> +  UINT32 Clock;
> +  UINT32 ClockSrc = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK);
> +
> +  ClockSrc = (ClockSrc >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK;
> +
> +  switch (ClockSrc) {
> +  case CLOCK_MANAGER_SRC_MAIN:
> +    Clock = S10ClockManagerGetMainClock() /
> +      CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PLLC1));
> +    break;
> +  case CLOCK_MANAGER_SRC_PERI:
> +    Clock = S10ClockManagerGetPerClock() /
> +      CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PLLC1));
> +    break;
> +  case CLOCK_MANAGER_SRC_OSC1:
> +    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
> +    break;
> +  case CLOCK_MANAGER_SRC_INTOSC:
> +    Clock = S10_CLOCK_INTOSC;
> +    break;
> +  case CLOCK_MANAGER_SRC_FPGA:
> +    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
> +    break;
> +  }
> +
> +  Clock /= 1 + (MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK) & CLOCK_MANAGER_CNT_MSK);
> +
> +  return Clock;
> +}
> +
> +UINT32
> +S10ClockManagerGetUartClock() {
> +  return  S10ClockManagerGetL3MainClock() /
> +             (1 << (CLOCK_MANAGER_NOCDIV_L4SPCLK(MmioRead32(CLOCK_MANAGER_MAINPLL_NOCDIV))));
> +}
> +
> +UINT32
> +S10ClockManagerGetMmcClock() {
> +  UINT32 Clock = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK);
> +
> +  Clock = (Clock >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK;
> +
> +  switch (Clock) {
> +  case CLOCK_MANAGER_SRC_MAIN:
> +    Clock = S10ClockManagerGetL3MainClock();
> +    Clock /=  1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) &
> +      CLOCK_MANAGER_CNT_MSK);
> +    break;
> +  case CLOCK_MANAGER_SRC_PERI:
> +    Clock = S10ClockManagerGetPerClock();
> +    Clock /=  1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) &
> +      CLOCK_MANAGER_CNT_MSK);
> +    break;
> +  case CLOCK_MANAGER_SRC_OSC1:
> +    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1);
> +    break;
> +  case CLOCK_MANAGER_SRC_INTOSC:
> +    Clock = S10_CLOCK_INTOSC;
> +    break;
> +  case CLOCK_MANAGER_SRC_FPGA:
> +    Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2);
> +    break;
> +  }
> +
> +  return Clock / 4;
> +}
> +
> diff --git a/Maintainers.txt b/Maintainers.txt
> index 876ae5612ad8..47d58ffa0b2c 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -98,6 +98,11 @@ M: Shifei A Lu <shifei.a.lu@intel.com>
>  M: Xiaohu Zhou <bowen.zhou@intel.com>
>  M: Isaac W Oram <isaac.w.oram@intel.com>
>
> +Platform/Intel/Stratix10SocPkg
> +M: Leif Lindholm <leif.lindholm@linaro.org>
> +M: Michael D Kinney <michael.d.kinney@intel.com>
> +R: Tien Hock Loh <tien.hock.loh@intel.com>
> +
>  Platform/Intel/Tools
>  M: Bob Feng <bob.c.feng@intel.com>
>  M: Liming Gao <liming.gao@intel.com>
> diff --git a/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
> index 2f4cf95cbf13..b7c6dbdc2e61 100644
> --- a/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
> +++ b/Platform/Intel/Stratix10/Library/IntelPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -1,13 +1,7 @@
>  //
>  //  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
>  //
> -//  This program and the accompanying materials
> -//  are licensed and made available under the terms and conditions of the BSD License
> -//  which accompanies this distribution.  The full text of the license may be found at
> -//  http://opensource.org/licenses/bsd-license.php
> -//
> -//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//  SPDX-License-Identifier: BSD-2-Clause-Patent
>  //
>  //
>
> --
> 2.19.0
>

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2019-09-04  5:35 [PATCH 1/1] Platform: Intel: Update licenses to SPDX and update clock settings Loh, Tien Hock
2019-09-04 12:58 ` Ard Biesheuvel

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