From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=nnH4mlDB; spf=pass (domain: linaro.org, ip: 209.85.221.44, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by groups.io with SMTP; Wed, 04 Sep 2019 13:40:28 -0700 Received: by mail-wr1-f44.google.com with SMTP id j16so197056wrr.8 for ; Wed, 04 Sep 2019 13:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=i6e2ndImwAlhI468C76lar+nCVWiG3aIsIshgYsOrjc=; b=nnH4mlDBcw/XxzFfklpII4FIkrJY003GHUHn0wNd26hCvob6iCd6gzlkEy4hTO4xex 3AELO9aqipjeYVfXmLptWLusaMw1UuLKJVGq1j9DRrP0xIiQRn4KCNKOZmQz9zhP3Xze Im+jNr7jGG7PsVVqqZly5UKBt7c9kqjlE5D5lTBvoAplEMsL/KVV0fFLpGzlcMlqNrN1 5XmvFZadyZncNOyGFas99gr0gFfGHtHPjkm7/pXv+6Cs6uZAGKZMzVf5SlTZLp+VXWAx SFPMVXmkhnPyebBPvLZHWhq4v3924VX5zy7zp2dPD22/USMoLIs5Qrg+9RJjhj55LGYV BX9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=i6e2ndImwAlhI468C76lar+nCVWiG3aIsIshgYsOrjc=; b=OWFZDCTmDL7TDs7aE60x0H3xGon30pweVrvV8tIYeww3kWKw0+B3Tt+6s8VsokreHs dd4mhFLwocbdzps31/x1Ek+IFHX6AaWQO9d2TN4W7TcA9xfZDeiHD3WfWkg2VgzjjMGu wp66JB0LtBMmdgqVthoe5fagwyb93iJa4XQtNc6xlEqjr6vyfBd34hazqQg8eGhFb9xo Lj6Z49eEO/w5JnBRj/Yn9V+mDDu4gfeauanqK13ehN6arGhwe/9zxG2uhurgBK+CN6HU ov+Vyf/ZPm7QtGHICNhUetH+w1Tpt79dUwkvjgYxMrmlGeCfCLUus1ofiI9gBQlGyY+3 kxgg== X-Gm-Message-State: APjAAAUEIjkqO/CPMK1H6DCvDmBDF1w4FOwEU4VSGL0Pd4qEcdG6YXzH Z8UDW5fou8mUm/E71hGKxL6myB2VwIA= X-Google-Smtp-Source: APXvYqw6szF1KibmR1EoeeTZHWt4MnBMAqu81nXW6Rj+VlEt2BLPJxwDWb9guyoi1D8t08fpbvqd0w== X-Received: by 2002:adf:ed0f:: with SMTP id a15mr33635839wro.49.1567629626400; Wed, 04 Sep 2019 13:40:26 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m62sm143719wmm.35.2019.09.04.13.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:40:25 -0700 (PDT) Date: Wed, 4 Sep 2019 21:40:24 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 04/22]: MdePkg/Include: RISC-V definitions. Message-ID: <20190904204024.GR29255@bivouac.eciton.net> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> <1567593797-26216-5-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1567593797-26216-5-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 04, 2019 at 06:42:59PM +0800, Abner Chang wrote: > Add RISC-V processor related definitions. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Abner Chang > --- > MdePkg/Include/IndustryStandard/PeImage.h | 14 +- > MdePkg/Include/Library/BaseLib.h | 67 ++++++ > MdePkg/Include/Protocol/DebugSupport.h | 55 +++++ > MdePkg/Include/Protocol/PxeBaseCode.h | 8 + > MdePkg/Include/RiscV64/ProcessorBind.h | 336 ++++++++++++++++++++++++++++++ > MdePkg/Include/Uefi/UefiBaseType.h | 25 +++ > MdePkg/Include/Uefi/UefiSpec.h | 11 + > 7 files changed, 513 insertions(+), 3 deletions(-) > create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h > > diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h > index 720bb08..47796b2 100644 > --- a/MdePkg/Include/IndustryStandard/PeImage.h > +++ b/MdePkg/Include/IndustryStandard/PeImage.h > @@ -9,6 +9,8 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define IMAGE_FILE_MACHINE_X64 0x8664 > #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 > #define IMAGE_FILE_MACHINE_ARM64 0xAA64 > +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 > +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 > > // > // EXE file formats > @@ -478,9 +483,9 @@ typedef struct { > /// > #define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8 > > -// > -// Based relocation types. > -// > +/// > +/// Based relocation types. > +/// I don't know if this change to the comment block is a wonky rebase or whatever, but please drop it. > #define EFI_IMAGE_REL_BASED_ABSOLUTE 0 > #define EFI_IMAGE_REL_BASED_HIGH 1 > #define EFI_IMAGE_REL_BASED_LOW 2 > @@ -488,7 +493,10 @@ typedef struct { > #define EFI_IMAGE_REL_BASED_HIGHADJ 4 > #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 > #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 I agree this is following the existing pattern, but the existing pattern looks bonkers. Sorting relocation types by numeric value rather than grouping the architecture-specific ones by architecture... Could you group the RISC-V ones together and put them after a single blank line below the current defines? I'll try to come back and fix the others once this set has been merged. > #define EFI_IMAGE_REL_BASED_IA64_IMM64 9 > #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9 > #define EFI_IMAGE_REL_BASED_DIR64 10 > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h > index 2a75bc0..5f0ee8d 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -4,6 +4,8 @@ > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -124,6 +126,71 @@ typedef struct { > > #endif // defined (MDE_CPU_AARCH64) > > +#if defined (MDE_CPU_RISCV64) > +/// > +/// The RISC-V architecture context buffer used by SetJump() and LongJump(). > +/// > +typedef struct { > + UINT64 RA; > + UINT64 S0; > + UINT64 S1; > + UINT64 S2; > + UINT64 S3; > + UINT64 S4; > + UINT64 S5; > + UINT64 S6; > + UINT64 S7; > + UINT64 S8; > + UINT64 S9; > + UINT64 S10; > + UINT64 S11; > + UINT64 SP; > +} BASE_LIBRARY_JUMP_BUFFER; > + > +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 > + > +/** > + RISC-V read CSR register. > + > +**/ > +UINT32 > +EFIAPI > +RiscVReadCsr ( This function does not appear to be implemented by any patch in this set? > + UINT32 CsrIndex > + ); > + > +/** > + RISC-V write CSR register. > + > +**/ > +VOID > +EFIAPI > +RiscVwriteCsr ( Neither does this one. (Also, that 'w' should probably be upper case if it was.) > + UINT32 CsrIndex, > + UINT32 Value > + ); > + > +/** > + RISC-V invalidate instruction cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvdInstCacheAsm ( > + VOID > + ); > + > +/** > + RISC-V invalidate data cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvdDataCacheAsm ( > + VOID > + ); > + I guess this is a larger discussion, but I think these cache operations should really live somewhere else. (As should the IA32/X64 ones - BaseLib.h is pushing 8k lines before this set.) Also, by proper CamelCase naming 'Invalidate' should be written out fully. > +#endif // defined (MDE_CPU_RISCV64) > > // > // String Services > diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h > index 800e771..1a29cc0 100644 > --- a/MdePkg/Include/Protocol/DebugSupport.h > +++ b/MdePkg/Include/Protocol/DebugSupport.h > @@ -7,6 +7,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -603,6 +604,59 @@ typedef struct { > UINT64 FAR; // Fault Address Register > } EFI_SYSTEM_CONTEXT_AARCH64; > > +/// > +/// RISC-V processor exception types. > +/// > +#define EXCEPT_RISCV_INST_MISALIGNED 0 > +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 > +#define EXCEPT_RISCV_ILLEGAL_INST 2 > +#define EXCEPT_RISCV_BREAKPOINT 3 > +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 > +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 > +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 > +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 > +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 > +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 > +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 > +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 > + > +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 > +#define EXCEPT_RISCV_TIMER_INT 0x1 > + > +typedef struct { > + UINT64 X0; > + UINT64 X1; > + UINT64 X2; > + UINT64 X3; > + UINT64 X4; > + UINT64 X5; > + UINT64 X6; > + UINT64 X7; > + UINT64 X8; > + UINT64 X9; > + UINT64 X10; > + UINT64 X11; > + UINT64 X12; > + UINT64 X13; > + UINT64 X14; > + UINT64 X15; > + UINT64 X16; > + UINT64 X17; > + UINT64 X18; > + UINT64 X19; > + UINT64 X20; > + UINT64 X21; > + UINT64 X22; > + UINT64 X23; > + UINT64 X24; > + UINT64 X25; > + UINT64 X26; > + UINT64 X27; > + UINT64 X28; > + UINT64 X29; > + UINT64 X30; > + UINT64 X31; > +} EFI_SYSTEM_CONTEXT_RISCV64; > > /// > /// Universal EFI_SYSTEM_CONTEXT definition. > @@ -614,6 +668,7 @@ typedef union { > EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; > EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; > EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; > + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; > } EFI_SYSTEM_CONTEXT; > > // > diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h > index b02d270..b7f9303 100644 > --- a/MdePkg/Include/Protocol/PxeBaseCode.h > +++ b/MdePkg/Include/Protocol/PxeBaseCode.h > @@ -3,6 +3,8 @@ > devices for network access and network booting. > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > @par Revision Reference: > @@ -153,6 +155,12 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; > #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A > #elif defined (MDE_CPU_AARCH64) > #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B > +#elif defined (MDE_CPU_RISCV32) > +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0019 > +#elif defined (MDE_CPU_RISCV64) > +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B > +#elif defined (MDE_CPU_RISCV128) > +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001D > #endif > > > diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h > new file mode 100644 > index 0000000..c1bf5cd > --- /dev/null > +++ b/MdePkg/Include/RiscV64/ProcessorBind.h > @@ -0,0 +1,336 @@ > +/** @file > + Processor or Compiler specific defines and types for RISC-V > + > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +**/ > + > +#ifndef __PROCESSOR_BIND_H__ > +#define __PROCESSOR_BIND_H__ > + > +/// > +/// Define the processor type so other code can make processor based choices > +/// > +#define MDE_CPU_RISCV64 > + > +// > +// Make sure we are using the correct packing rules per EFI specification > +// > +#if !defined(__GNUC__) > +#pragma pack() > +#endif > + > +#if defined(__INTEL_COMPILER) ICC supports RISC-V? > +// > +// Disable ICC's remark #869: "Parameter" was never referenced warning. > +// This is legal ANSI C code so we disable the remark that is turned on with -Wall > +// > +#pragma warning ( disable : 869 ) > + > +// > +// Disable ICC's remark #1418: external function definition with no prior declaration. > +// This is legal ANSI C code so we disable the remark that is turned on with /W4 > +// > +#pragma warning ( disable : 1418 ) > + > +// > +// Disable ICC's remark #1419: external declaration in primary source file > +// This is legal ANSI C code so we disable the remark that is turned on with /W4 > +// > +#pragma warning ( disable : 1419 ) > + > +// > +// Disable ICC's remark #593: "Variable" was set but never used. > +// This is legal ANSI C code so we disable the remark that is turned on with /W4 > +// > +#pragma warning ( disable : 593 ) > + > +#endif > + > + > +#if defined(_MSC_EXTENSIONS) Visual Studio supports RISC-V? > + > +// > +// Disable warning that make it impossible to compile at /W4 > +// This only works for Microsoft* tools > +// > + > +// > +// Disabling bitfield type checking warnings. > +// > +#pragma warning ( disable : 4214 ) > + > +// > +// Disabling the unreferenced formal parameter warnings. > +// > +#pragma warning ( disable : 4100 ) > + > +// > +// Disable slightly different base types warning as CHAR8 * can not be set > +// to a constant string. > +// > +#pragma warning ( disable : 4057 ) > + > +// > +// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning > +// > +#pragma warning ( disable : 4127 ) > + > +// > +// This warning is caused by functions defined but not used. For precompiled header only. > +// > +#pragma warning ( disable : 4505 ) > + > +// > +// This warning is caused by empty (after preprocessing) source file. For precompiled header only. > +// > +#pragma warning ( disable : 4206 ) > + > +#if _MSC_VER == 1800 > + > +// > +// Disable these warnings for VS2013. > +// > + > +// > +// This warning is for potentially uninitialized local variable, and it may cause false > +// positive issues in VS2013 build > +// > +#pragma warning ( disable : 4701 ) > + > +// > +// This warning is for potentially uninitialized local pointer variable, and it may cause > +// false positive issues in VS2013 build > +// > +#pragma warning ( disable : 4703 ) > + > +#endif > + > +#endif > + > + > +#if defined(_MSC_EXTENSIONS) > + // > + // use Microsoft C complier dependent integer width types > + // > + > + /// > + /// 8-byte unsigned value > + /// > + typedef unsigned __int64 UINT64; > + /// > + /// 8-byte signed value > + /// > + typedef __int64 INT64; > + /// > + /// 4-byte unsigned value > + /// > + typedef unsigned __int32 UINT32; > + /// > + /// 4-byte signed value > + /// > + typedef __int32 INT32; > + /// > + /// 2-byte unsigned value > + /// > + typedef unsigned short UINT16; > + /// > + /// 2-byte Character. Unless otherwise specified all strings are stored in the > + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. > + /// > + typedef unsigned short CHAR16; > + /// > + /// 2-byte signed value > + /// > + typedef short INT16; > + /// > + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other > + /// values are undefined. > + /// > + typedef unsigned char BOOLEAN; > + /// > + /// 1-byte unsigned value > + /// > + typedef unsigned char UINT8; > + /// > + /// 1-byte Character > + /// > + typedef char CHAR8; > + /// > + /// 1-byte signed value > + /// > + typedef signed char INT8; > + > + /// > + /// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, > + /// 8 bytes on supported 64-bit processor instructions) > + /// > + typedef UINT64 UINTN; > + /// > + /// Signed value of native width. (4 bytes on supported 32-bit processor instructions, > + /// 8 bytes on supported 64-bit processor instructions) > + /// > + typedef INT64 INTN; > +#else > + /// > + /// 8-byte unsigned value > + /// > + typedef unsigned long long UINT64 __attribute__ ((aligned (8))); > + /// > + /// 8-byte signed value > + /// > + typedef long long INT64 __attribute__ ((aligned (8))); > + /// > + /// 4-byte unsigned value > + /// > + typedef unsigned int UINT32 __attribute__ ((aligned (4))); > + /// > + /// 4-byte signed value > + /// > + typedef int INT32 __attribute__ ((aligned (4))); > + /// > + /// 2-byte unsigned value > + /// > + typedef unsigned short UINT16 __attribute__ ((aligned (2))); > + /// > + /// 2-byte Character. Unless otherwise specified all strings are stored in the > + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. > + /// > + typedef unsigned short CHAR16 __attribute__ ((aligned (2))); > + /// > + /// 2-byte signed value > + /// > + typedef short INT16 __attribute__ ((aligned (2))); > + /// > + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other > + /// values are undefined. > + /// > + typedef unsigned char BOOLEAN; > + /// > + /// 1-byte unsigned value > + /// > + typedef unsigned char UINT8; > + /// > + /// 1-byte Character > + /// > + typedef char CHAR8; > + /// > + /// 1-byte signed value > + /// > + typedef signed char INT8; > + /// > + /// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, > + /// 8 bytes on supported 64-bit processor instructions) > + /// > + typedef UINT64 UINTN __attribute__ ((aligned (8))); > + /// > + /// Signed value of native width. (4 bytes on supported 32-bit processor instructions, > + /// 8 bytes on supported 64-bit processor instructions) > + /// > + typedef INT64 INTN __attribute__ ((aligned (8))); > +#endif > + > +// > +// Processor specific defines > +// > + > +/// > +/// A value of native width with the highest bit set. > +/// > +#define MAX_BIT 0x8000000000000000ULL > +/// > +/// A value of native width with the two highest bits set. > +/// > +#define MAX_2_BITS 0xC000000000000000ULL > + > +/// > +/// Maximum legal x64 address > +/// > +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL > + > +/// > +/// Maximum usable address at boot time (48 bits using 4 KB pages) This is true for AArch64, is it also true for RISC-V? > +/// > +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL > + > +/// > +/// Maximum legal RISC-V INTN and UINTN values. > +/// > +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) > +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) > + > +/// > +/// The stack alignment required for RISC-V > +/// > +#define CPU_STACK_ALIGNMENT 16 > + > +/// > +/// Page allocation granularity for RISC-V > +/// > +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) > +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) > + > +// > +// Modifier to ensure that all protocol member functions and EFI intrinsics > +// use the correct C calling convention. All protocol member functions and > +// EFI intrinsics are required to modify their member functions with EFIAPI. > +// > +#ifdef EFIAPI > + /// > + /// If EFIAPI is already defined, then we use that definition. > + /// > +#elif defined(_MSC_EXTENSIONS) > + /// > + /// Microsoft* compiler specific method for EFIAPI calling convention. > + /// > + #define EFIAPI __cdecl > +#elif defined(__GNUC__) > + /// > + /// Define the standard calling convention regardless of optimization level > + /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI > + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64) > + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for > + /// x64. Warning the assembly code in the MDE x64 does not follow the correct > + /// ABI for the standard x64 (x86-64) GCC. > + /// > + #define EFIAPI > +#else > + /// > + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI > + /// is the standard. > + /// > + #define EFIAPI > +#endif > + > +#if defined(__GNUC__) > + /// > + /// For GNU assembly code, .global or .globl can declare global symbols. > + /// Define this macro to unify the usage. > + /// > + #define ASM_GLOBAL .globl > +#endif > + > +/** > + Return the pointer to the first instruction of a function given a function pointer. > + On x64 CPU architectures, these two pointer values are the same, > + so the implementation of this macro is very simple. > + > + @param FunctionPointer A pointer to a function. > + > + @return The pointer to the first instruction of a function given a function pointer. > + > +**/ > +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) > + > +#ifndef __USER_LABEL_PREFIX__ > +#define __USER_LABEL_PREFIX__ > +#endif > + > +#endif > diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h > index a62f13d..89880be 100644 > --- a/MdePkg/Include/Uefi/UefiBaseType.h > +++ b/MdePkg/Include/Uefi/UefiBaseType.h > @@ -3,6 +3,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -240,6 +241,12 @@ typedef union { > /// > #define EFI_IMAGE_MACHINE_AARCH64 0xAA64 > > +/// > +/// PE32+ Machine type for RISC-V 32/64/128 > +/// > +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 > +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 > +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 > > #if defined (MDE_CPU_IA32) > > @@ -268,6 +275,24 @@ typedef union { > > #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > > +#elif defined (MDE_CPU_RISCV128) > +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ > + (((Machine) == EFI_IMAGE_MACHINE_RISCV128) || ((Machine) == EFI_IMAGE_MACHINE_EBC)) I wouldn't worry about the EBC case until there is an interpreter for RISC-V (and there are not many good reasons for implementing one). Same applies for tests below. > + > +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > + > +#elif defined (MDE_CPU_RISCV64) > +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ > + (((Machine) == EFI_IMAGE_MACHINE_RISCV64) || ((Machine) == EFI_IMAGE_MACHINE_EBC)) > + > +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > + > +#elif defined (MDE_CPU_RISCV32) > +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ > + (((Machine) == EFI_IMAGE_MACHINE_RISCV32) || ((Machine) == EFI_IMAGE_MACHINE_EBC)) > + > +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > + / Leif > #elif defined (MDE_CPU_EBC) > > /// > diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h > index 44a0a6a..b805175 100644 > --- a/MdePkg/Include/Uefi/UefiSpec.h > +++ b/MdePkg/Include/Uefi/UefiSpec.h > @@ -6,6 +6,8 @@ > by this include file. > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -2178,6 +2180,9 @@ typedef struct { > #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" > #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" > #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" > +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV32 L"\\EFI\\BOOT\\BOOTRISCV32.EFI" > +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI" > +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV128 L"\\EFI\\BOOT\\BOOTRISCV128.EFI" > > #if defined (MDE_CPU_IA32) > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 > @@ -2188,6 +2193,12 @@ typedef struct { > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM > #elif defined (MDE_CPU_AARCH64) > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 > +#elif defined (MDE_CPU_RISCV32) > + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV32 > +#elif defined (MDE_CPU_RISCV64) > + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 > +#elif defined (MDE_CPU_RISCV128) > + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV128 > #else > #error Unknown Processor Type > #endif > -- > 2.7.4 > > > >