From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: tien.hock.loh@intel.com) Received: from mga11.intel.com (mga11.intel.com []) by groups.io with SMTP; Thu, 05 Sep 2019 00:25:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2019 00:25:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,469,1559545200"; d="scan'208";a="187890393" Received: from ppglcf0018.png.intel.com ([10.226.229.38]) by orsmga006.jf.intel.com with ESMTP; 05 Sep 2019 00:25:09 -0700 From: "Loh, Tien Hock" To: devel@edk2.groups.io, thloh85@gmail.com Cc: "Tien Hock, Loh" , Ard Biesheuvel , Leif Lindholm , Michael D Kinney Subject: [PATCH 4/4] Platform: Intel: Remove hardcoded Stratix 10 UART clock Date: Thu, 5 Sep 2019 15:24:23 +0800 Message-Id: <20190905072423.150004-5-tien.hock.loh@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20190905072423.150004-1-tien.hock.loh@intel.com> References: <20190905072423.150004-1-tien.hock.loh@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Tien Hock, Loh" Added clock manager so that Stratix 10 UART clock doesn't need to be hardcoded Signed-off-by: "Tien Hock, Loh" Contributed-under: TianoCore Contribution Agreement 1.1 Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Platform/Intel/Stratix10/Stratix10SoCPkg.dec | 3 +- Platform/Intel/Stratix10/Stratix10SoCPkg.dsc | 11 +- Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf | 41 ++++++ Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf | 34 +++++ Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h | 48 +++++++ Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c | 43 +++++++ Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c | 133 ++++++++++++++++++++ 7 files changed, 310 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec index 7c44670d591d..346f7f9a042b 100755 --- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dec +++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dec @@ -10,7 +10,8 @@ [Defines] PACKAGE_GUID = 45533DD0-C41F-4ab6-A5DF-65B52684AC60 PACKAGE_VERSION = 0.1 -[Includes.common] +[Includes] + Include [Guids.common] gStratix10SocFpgaTokenSpaceGuid = { 0x0fe272eb, 0xb2cf, 0x4390, { 0xa5, 0xc4, 0x60, 0x13, 0x2c, 0x6b, 0xd0, 0x34 } } diff --git a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc index 643ce625c563..d3ad0eba7e75 100755 --- a/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc +++ b/Platform/Intel/Stratix10/Stratix10SoCPkg.dsc @@ -27,6 +27,8 @@ [Defines] # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ################################################################################ +[PcdsPatchableInModule.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|184320 [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE @@ -226,7 +228,8 @@ [LibraryClasses.common] SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + PlatformHookLib|Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf + S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf @@ -483,9 +486,13 @@ [Components.common] } # - # Platform Specific Init for DXE phase + # Platform Specific Init # Platform/Intel/Stratix10/Drivers/IntelPlatformDxe/IntelPlatformDxe.inf + Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf { + + S10ClockManager|Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf + } [BuildOptions] #------------------------------- diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf new file mode 100644 index 000000000000..dc18db7c5444 --- /dev/null +++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.inf @@ -0,0 +1,41 @@ +## @file +# Platform Hook Library instance for UART device. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PlatformHookLib + FILE_GUID = 90A73C58-A6E3-4EED-A1A3-6F9C7C3D998F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformHookLib + CONSTRUCTOR = PlatformHookSerialPortInitialize + +[Sources] + PlatformHookLib.c + +[LibraryClasses] + PcdLib + PciLib + S10ClockManager + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/Intel/Stratix10/Stratix10SoCPkg.dec + UefiPayloadPkg/UefiPayloadPkg.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES + diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf new file mode 100644 index 000000000000..c0eccd304810 --- /dev/null +++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.inf @@ -0,0 +1,34 @@ +## @file +# Clock Manager Library instance +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = S10ClockManagerLib + FILE_GUID = 90A73C58-A6E3-4EED-A1A3-6F9C7C3E998F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = S10ClockManagerLib + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Intel/Stratix10/Stratix10SoCPkg.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + DebugLib + IoLib + PcdLib + +[Sources] + S10ClockManager.c + diff --git a/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h new file mode 100644 index 000000000000..f081a70a7a11 --- /dev/null +++ b/Platform/Intel/Stratix10/Include/Library/S10ClockManager/S10ClockManager.h @@ -0,0 +1,48 @@ +/** @file +Stratix 10 Clock Manager header + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _S10_CLOCK_MANAGER_ +#define _S10_CLOCK_MANAGER_ +#define CLOCK_MANAGER_MAINPLL 0xffd10030 +#define CLOCK_MANAGER_MAINPLL_NOCCLK 0x4c + +#define CLOCK_MANAGER_PERPLL 0xffd100a4 +#define CLOCK_MANAGER_MAINPLL_PLLGLOB 0x44 +#define CLOCK_MANAGER_PERPLL_PLLGLOB 0x40 +#define CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(x) (((x) >> 16) & 3) +#define CLOCK_MANAGER_CNTR6CLK 0x4c +#define CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1 0 +#define CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC 1 +#define CLOCK_MANAGER_PLLGLOB_PSRC_F2S 2 +#define CLOCK_MANAGER_SRC 16 +#define CLOCK_MANAGER_SRC_MSK 0x7 +#define CLOCK_MANAGER_SRC_MAIN (0) +#define CLOCK_MANAGER_SRC_PERI (1) +#define CLOCK_MANAGER_SRC_OSC1 (2) +#define CLOCK_MANAGER_SRC_INTOSC (3) +#define CLOCK_MANAGER_SRC_FPGA (4) +#define CLOCK_MANAGER_FDBCK 0x44 +#define CLOCK_MANAGER_FDBCK_MDIV(x) ((x) >> 24 & 0xff) +#define CLOCK_MANAGER_PERPLL_FDBCK 0x48 +#define CLOCK_MANAGER_CNT_MSK 0x3ff +#define CLOCK_MANAGER_PERPLL_CNTR6CLK 0x28 +#define CLOCK_MANAGER_PLLGLOB_REFCLKDIV(x) (((x) >> 8) & 0x3f) +#define CLOCK_MANAGER_PLLC1_DIV(x) ((x) & 0x7f) +#define CLOCK_MANAGER_PLLC1 0x54 +#define CLOCK_MANAGER_NOCDIV_L4SPCLK(x) ((x) >> 16 & 0x3) +#define CLOCK_MANAGER_MAINPLL_NOCDIV 0x40 + +#define S10_SYSTEM_MANAGER 0xffd12000 +#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1 0x204 +#define S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2 0x208 +#define S10_CLOCK_INTOSC 460000000 + +UINT32 S10ClockManagerGetMmcClock(); +UINT32 S10ClockManagerGetUartClock(); + +#endif diff --git a/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c new file mode 100644 index 000000000000..a204718909df --- /dev/null +++ b/Platform/Intel/Stratix10/Library/PlatformHookLib/PlatformHookLib.c @@ -0,0 +1,43 @@ +/** @file + Platform Hook Library + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + RETURN_STATUS Status; + + Status = PcdSet32S (PcdSerialClockRate, S10ClockManagerGetUartClock()); + + if (RETURN_ERROR (Status)) { + return Status; + } + + return RETURN_SUCCESS; +} diff --git a/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c new file mode 100644 index 000000000000..5e6fe283646d --- /dev/null +++ b/Platform/Intel/Stratix10/Library/S10ClockManager/S10ClockManager.c @@ -0,0 +1,133 @@ +/** @file +Stratix 10 Clock Manager + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +UINT32 +S10ClockManagerGetPerClock() { + UINT32 PllGlob, MDiv, RefClkDiv, RefClk; + + PllGlob = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_PLLGLOB); + + switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) { + case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1: + RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1); + RefClk = 2500000; + break; + case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC: + RefClk = S10_CLOCK_INTOSC; + break; + case CLOCK_MANAGER_PLLGLOB_PSRC_F2S: + RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2); + RefClk = 5000000; + break; + } + + RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob); + + MDiv = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_FDBCK); + + return (RefClk / RefClkDiv) * (6 + MDiv); +} + +UINT32 +S10ClockManagerGetMainClock() { + UINT32 PllGlob, MDiv, RefClkDiv, RefClk; + + PllGlob = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_PLLGLOB); + + switch (CLOCK_MANAGER_MAINPLL_PLLGLOB_PSRC(PllGlob)) { + case CLOCK_MANAGER_PLLGLOB_PSRC_EOSC1: + RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1); + RefClk = 2500000; + break; + case CLOCK_MANAGER_PLLGLOB_PSRC_INTOSC: + RefClk = S10_CLOCK_INTOSC; + break; + case CLOCK_MANAGER_PLLGLOB_PSRC_F2S: + RefClk = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2); + RefClk = 5000000; + break; + } + + RefClkDiv = CLOCK_MANAGER_PLLGLOB_REFCLKDIV(PllGlob); + MDiv = CLOCK_MANAGER_FDBCK_MDIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PERPLL_FDBCK)); + + return (RefClk / RefClkDiv) * (6 + MDiv); +} + +INTN +S10ClockManagerGetL3MainClock() { + UINT32 Clock; + UINT32 ClockSrc = MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK); + + ClockSrc = (ClockSrc >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK; + + switch (ClockSrc) { + case CLOCK_MANAGER_SRC_MAIN: + Clock = S10ClockManagerGetMainClock() / + CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_PLLC1)); + break; + case CLOCK_MANAGER_SRC_PERI: + Clock = S10ClockManagerGetPerClock() / + CLOCK_MANAGER_PLLC1_DIV(MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PLLC1)); + break; + case CLOCK_MANAGER_SRC_OSC1: + Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1); + break; + case CLOCK_MANAGER_SRC_INTOSC: + Clock = S10_CLOCK_INTOSC; + break; + case CLOCK_MANAGER_SRC_FPGA: + Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2); + break; + } + + Clock /= 1 + (MmioRead32(CLOCK_MANAGER_MAINPLL + CLOCK_MANAGER_MAINPLL_NOCCLK) & CLOCK_MANAGER_CNT_MSK); + + return Clock; +} + +UINT32 +S10ClockManagerGetUartClock() { + return S10ClockManagerGetL3MainClock() / + (1 << (CLOCK_MANAGER_NOCDIV_L4SPCLK(MmioRead32(CLOCK_MANAGER_MAINPLL_NOCDIV)))); +} + +UINT32 +S10ClockManagerGetMmcClock() { + UINT32 Clock = MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK); + + Clock = (Clock >> CLOCK_MANAGER_SRC) & CLOCK_MANAGER_SRC_MSK; + + switch (Clock) { + case CLOCK_MANAGER_SRC_MAIN: + Clock = S10ClockManagerGetL3MainClock(); + Clock /= 1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) & + CLOCK_MANAGER_CNT_MSK); + break; + case CLOCK_MANAGER_SRC_PERI: + Clock = S10ClockManagerGetPerClock(); + Clock /= 1 + (MmioRead32(CLOCK_MANAGER_PERPLL + CLOCK_MANAGER_PERPLL_CNTR6CLK) & + CLOCK_MANAGER_CNT_MSK); + break; + case CLOCK_MANAGER_SRC_OSC1: + Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD1); + break; + case CLOCK_MANAGER_SRC_INTOSC: + Clock = S10_CLOCK_INTOSC; + break; + case CLOCK_MANAGER_SRC_FPGA: + Clock = MmioRead32(S10_SYSTEM_MANAGER + S10_SYSTEM_MANAGER_BOOTSCRATCH_COLD2); + break; + } + + return Clock / 4; +} + -- 2.19.0