From: "Leif Lindholm" <leif.lindholm@linaro.org>
To: devel@edk2.groups.io, abner.chang@hpe.com
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 08/22]: MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
Date: Thu, 5 Sep 2019 15:38:39 +0100 [thread overview]
Message-ID: <20190905143839.GZ29255@bivouac.eciton.net> (raw)
In-Reply-To: <1567593797-26216-9-git-send-email-abner.chang@hpe.com>
On Wed, Sep 04, 2019 at 06:43:03PM +0800, Abner Chang wrote:
> Support RISC-V image relocation.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 4 +-
> .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 149 +++++++++++++++++++++
> 5 files changed, 160 insertions(+), 2 deletions(-)
> create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> index 07bb62f..97e0ff4 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> @@ -1,6 +1,6 @@
> /** @file
> Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
> - only supports relocating IA32, x64, IPF, and EBC images.
> + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
>
> Caution: This file requires additional review when modified.
> This library will have external input - PE/COFF image.
> @@ -17,6 +17,7 @@
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> index 395c140..e5c8e66 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> @@ -3,6 +3,7 @@
> # The IPF version library supports loading IPF and EBC PE/COFF image.
> # The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
> # The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> +# The RISC-V version library support loading RISC-V images.
> #
> # Caution: This module requires additional review when modified.
> # This library will have external input - PE/COFF image.
> @@ -11,6 +12,7 @@
> #
> # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -41,6 +43,9 @@
> [Sources.ARM]
> Arm/PeCoffLoaderEx.c
>
> +[Sources.RISCV64]
> + RiscV/PeCoffLoaderEx.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> index b0ea702..edc48cd 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> @@ -4,7 +4,8 @@
> // The IPF version library supports loading IPF and EBC PE/COFF image.
> // The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
> // The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> -//
> +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
> +//
The above diff looks like you're adding a blank line and deleting
another one. This happens because you have added a trailing space on
the gap line. PatchCheck.py finds these.
/
Leif
> // Caution: This module requires additional review when modified.
> // This library will have external input - PE/COFF image.
> // This external input must be validated carefully to avoid security issue like
> @@ -12,6 +13,7 @@
> //
> // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent
> //
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> index b74277f..9c33703 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> @@ -2,6 +2,7 @@
> Declaration of internal functions in PE/COFF Lib.
>
> Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> new file mode 100644
> index 0000000..a99550f
> --- /dev/null
> +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> @@ -0,0 +1,149 @@
> +/** @file
> + PE/Coff loader for RISC-V PE image
> +
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +#include "BasePeCoffLibInternals.h"
> +#include <Library/BaseLib.h>
> +
> +//
> +// RISC-V definition.
> +//
> +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> +#define RISCV_IMM_BITS 12
> +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> +#define RISCV_CONST_HIGH_PART(VALUE) \
> + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> +
> +/**
> + Performs an RISC-V specific relocation fixup and is a no-op on
> + other instruction sets.
> + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
> + types. We have to know the lower 12-bit fixup first then we can deal
> + carry over on high 20-bit fixup. So we log the high 20-bit in
> + FixupData.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeCoffLoaderRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + UINT32 Value;
> + UINT32 Value2;
> + UINT32 *RiscVHi20Fixup;
> +
> + switch ((*Reloc) >> 12) {
> + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> +
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
> + (RV_X (*(UINT32 *)Fixup, 0, 20));
> + }
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> + Value &= RISCV_IMM_REACH - 1;
> + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
> + }
> + break;
> +
> + default:
> + return RETURN_UNSUPPORTED;
> +
> + }
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Returns TRUE if the machine type of PE/COFF image is supported. Supported
> + does not mean the image can be executed it means the PE/COFF loader supports
> + loading and relocating of the image type. It's up to the caller to support
> + the entry point.
> +
> + @param Machine Machine type from the PE Header.
> +
> + @return TRUE if this PE/COFF loader can load the image
> +
> +**/
> +BOOLEAN
> +PeCoffLoaderImageFormatSupported (
> + IN UINT16 Machine
> + )
> +{
> + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine == IMAGE_FILE_MACHINE_RISCV64)) {
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Performs an Itanium-based specific re-relocation fixup and is a no-op on other
> + instruction sets. This is used to re-relocated the image into the EFI virtual
> + space for runtime calls.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeHotRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + return RETURN_UNSUPPORTED;
> +}
> --
> 2.7.4
>
>
>
>
next prev parent reply other threads:[~2019-09-05 14:38 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 10:42 [PATCH 00/22] RISC-V EDK2 Port on edk2-staging/RISC-V-V2 branch Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 01/22]: RiscVPkg: RISC-V processor package Abner Chang
2019-09-04 17:51 ` [edk2-devel] " Leif Lindholm
2019-09-16 5:15 ` Abner Chang
2019-09-17 14:03 ` Leif Lindholm
2019-09-19 7:10 ` Abner Chang
2019-09-20 17:04 ` Leif Lindholm
2019-09-21 7:14 ` Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 02/22]: RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-04 18:55 ` [edk2-devel] " Leif Lindholm
2019-09-16 4:02 ` Abner Chang
2019-09-17 13:54 ` Leif Lindholm
2019-09-19 6:58 ` Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 03/22]: MdePkg: RISC-V sections in DEC file Abner Chang
2019-09-04 19:02 ` [edk2-devel] " Leif Lindholm
2019-09-16 5:16 ` Abner Chang
2019-09-16 9:17 ` Leif Lindholm
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 04/22]: MdePkg/Include: RISC-V definitions Abner Chang
2019-09-04 20:40 ` [edk2-devel] " Leif Lindholm
2019-09-16 5:31 ` Abner Chang
2019-09-17 14:11 ` Leif Lindholm
2019-09-17 8:32 ` Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 05/22]: MdeModulePkg/CapsuleRuntimeDxe: Add RISC-V arch Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 6/22]: MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-09-04 20:49 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 07/22]: MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-05 14:28 ` [edk2-devel] " Leif Lindholm
2019-09-16 5:37 ` Abner Chang
2019-09-17 14:14 ` Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 08/22]: MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-09-05 14:38 ` Leif Lindholm [this message]
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 09/22]: MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-05 14:42 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 10/22]: MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-05 14:51 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 11/22]: BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-05 15:44 ` [edk2-devel] " Leif Lindholm
2019-09-16 6:44 ` Abner Chang
2019-09-17 12:15 ` Leif Lindholm
2019-09-09 11:36 ` Leif Lindholm
2019-09-16 7:46 ` Abner Chang
2019-09-17 13:08 ` Leif Lindholm
2019-09-17 14:26 ` Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 12/22]: MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-05 16:11 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 13/22]: MdePkg/Include: Update SmBios header file Abner Chang
2019-09-05 16:16 ` [edk2-devel] " Leif Lindholm
2019-09-16 7:01 ` Abner Chang
2019-09-17 14:15 ` Leif Lindholm
[not found] ` <15C4D92300C8E997.28834@groups.io>
2019-09-17 6:58 ` Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 14/22]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Abner Chang
2019-09-05 16:19 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 15/22]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Abner Chang
2019-09-05 16:26 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 16/22]: RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-05 16:28 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 17/22]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS " Abner Chang
2019-09-05 16:31 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 18/22]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Abner Chang
2019-09-05 16:48 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 19/22]: MdeModulePkg/DxeIplPeim:RISC-V platform DXEIPL Abner Chang
2019-09-05 16:50 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 20/22]: MdeModulePkg/Logo Abner Chang
2019-09-05 16:51 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 21/22]: NetworkPkg Abner Chang
2019-09-05 16:52 ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 22/22]: BaseTools/Scripts Abner Chang
2019-09-05 16:54 ` [edk2-devel] " Leif Lindholm
2019-09-05 17:15 ` [edk2-devel] [PATCH 00/22] RISC-V EDK2 Port on edk2-staging/RISC-V-V2 branch Leif Lindholm
2019-09-06 1:27 ` Abner Chang
[not found] ` <15C1B52667BA1578.25810@groups.io>
2019-09-23 1:15 ` Abner Chang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190905143839.GZ29255@bivouac.eciton.net \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox