From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=U0boz1Fc; spf=pass (domain: linaro.org, ip: 209.85.128.48, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by groups.io with SMTP; Thu, 05 Sep 2019 07:38:43 -0700 Received: by mail-wm1-f48.google.com with SMTP id q19so3104382wmc.3 for ; Thu, 05 Sep 2019 07:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=FbfXDKLGmHsYmAvUuHJkbboK2P6fhvjD3jsuZDHKQ+A=; b=U0boz1Fc2/Q5JYQO2S1kzS1Mnq6Fkc7iAM0/dWp0EikwBLEj/Hj6v+VSo2eaeDVXky gQRlPlBvd1aPGjDsOUxoK1cYaaehxIqBLqhYiMyKj2akaJuCt/I1RJSNEVeIwTnOpvcW x39xSgiKx4wDfD1eBvndnKnX6heO/f6z1TtHabVBerPCSS8UCtCFgnrG3HqJhePpt1sy zcHKvmfXefp1nDCT99DL4TG2ii3JBKEF+OY5T5shZZ4fCXlzdztQ66oF2pIHQ6lw17B4 ZRTftviwTBATYrUxK2jZVbzsTCTetcdYAhFPXcWTMXP0OMy2YXXx/QmeE+vRFj+worQS ki9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=FbfXDKLGmHsYmAvUuHJkbboK2P6fhvjD3jsuZDHKQ+A=; b=BLAIgdONRwkB8uO0OIziZ37Vwy4f+EUqlf0ZsOiokeqVU8JmljVRGb9tDWK+VsEGm1 C9Se0i3B0iaURRXUY+PHVIaos6kNunA8DG+/SRiqWaPNTpj/KfvS6va5qixtlQ+qflkO fQG3aZCxojNosBbUwBTGcFtnG8bZoyH8dKI4vFyOi7n6HFb9ky5w8H9p23dHVYC/U3tx d7fdkxmK0gawHZoe1et4upJRaqBaIeTdHwgM4sW8ViDkv3D2/wXNO1lHXS5/FcNzpsDp LSTrsv5Ip0vT59zwM9cslYLgL2oBcnytqx3I0IA4LBYL+HB43Q9uqlgZcuiZ3j3F71nR ndlQ== X-Gm-Message-State: APjAAAVwjLFjKIo+A83H/Rr3bzoHArgWtLOEABDX+1Ytc6FbmKGIZNfv sflw5GZTZTpTHMFkVIVutwEUWxyXqPc= X-Google-Smtp-Source: APXvYqwOUNdJOEwlyGXOgVrI5uRGPO5D1FMHI3lueLUGmjC2s0kFPH6Dgr4StdF2aqrrjKIOV8Sb7w== X-Received: by 2002:a7b:c4d0:: with SMTP id g16mr3446677wmk.94.1567694321622; Thu, 05 Sep 2019 07:38:41 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f66sm4310365wmg.2.2019.09.05.07.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 07:38:40 -0700 (PDT) Date: Thu, 5 Sep 2019 15:38:39 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 08/22]: MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Message-ID: <20190905143839.GZ29255@bivouac.eciton.net> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> <1567593797-26216-9-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1567593797-26216-9-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 04, 2019 at 06:43:03PM +0800, Abner Chang wrote: > Support RISC-V image relocation. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Abner Chang > --- > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 4 +- > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 + > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 149 +++++++++++++++++++++ > 5 files changed, 160 insertions(+), 2 deletions(-) > create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c > index 07bb62f..97e0ff4 100644 > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c > @@ -1,6 +1,6 @@ > /** @file > Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but > - only supports relocating IA32, x64, IPF, and EBC images. > + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images. > > Caution: This file requires additional review when modified. > This library will have external input - PE/COFF image. > @@ -17,6 +17,7 @@ > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > index 395c140..e5c8e66 100644 > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > @@ -3,6 +3,7 @@ > # The IPF version library supports loading IPF and EBC PE/COFF image. > # The IA32 version library support loading IA32, X64 and EBC PE/COFF images. > # The X64 version library support loading IA32, X64 and EBC PE/COFF images. > +# The RISC-V version library support loading RISC-V images. > # > # Caution: This module requires additional review when modified. > # This library will have external input - PE/COFF image. > @@ -11,6 +12,7 @@ > # > # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -41,6 +43,9 @@ > [Sources.ARM] > Arm/PeCoffLoaderEx.c > > +[Sources.RISCV64] > + RiscV/PeCoffLoaderEx.c > + > [Packages] > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni > index b0ea702..edc48cd 100644 > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni > @@ -4,7 +4,8 @@ > // The IPF version library supports loading IPF and EBC PE/COFF image. > // The IA32 version library support loading IA32, X64 and EBC PE/COFF images. > // The X64 version library support loading IA32, X64 and EBC PE/COFF images. > -// > +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images. > +// The above diff looks like you're adding a blank line and deleting another one. This happens because you have added a trailing space on the gap line. PatchCheck.py finds these. / Leif > // Caution: This module requires additional review when modified. > // This library will have external input - PE/COFF image. > // This external input must be validated carefully to avoid security issue like > @@ -12,6 +13,7 @@ > // > // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> // > // SPDX-License-Identifier: BSD-2-Clause-Patent > // > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h > index b74277f..9c33703 100644 > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h > @@ -2,6 +2,7 @@ > Declaration of internal functions in PE/COFF Lib. > > Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c > new file mode 100644 > index 0000000..a99550f > --- /dev/null > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c > @@ -0,0 +1,149 @@ > +/** @file > + PE/Coff loader for RISC-V PE image > + > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +**/ > +#include "BasePeCoffLibInternals.h" > +#include > + > +// > +// RISC-V definition. > +// > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) > +#define RISCV_IMM_BITS 12 > +#define RISCV_IMM_REACH (1LL< +#define RISCV_CONST_HIGH_PART(VALUE) \ > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) > + > +/** > + Performs an RISC-V specific relocation fixup and is a no-op on > + other instruction sets. > + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation > + types. We have to know the lower 12-bit fixup first then we can deal > + carry over on high 20-bit fixup. So we log the high 20-bit in > + FixupData. > + > + @param Reloc The pointer to the relocation record. > + @param Fixup The pointer to the address to fix up. > + @param FixupData The pointer to a buffer to log the fixups. > + @param Adjust The offset to adjust the fixup. > + > + @return Status code. > + > +**/ > +RETURN_STATUS > +PeCoffLoaderRelocateImageEx ( > + IN UINT16 *Reloc, > + IN OUT CHAR8 *Fixup, > + IN OUT CHAR8 **FixupData, > + IN UINT64 Adjust > + ) > +{ > + UINT32 Value; > + UINT32 Value2; > + UINT32 *RiscVHi20Fixup; > + > + switch ((*Reloc) >> 12) { > + case EFI_IMAGE_REL_BASED_RISCV_HI20: > + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup; > + break; > + > + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData)); > + if (RiscVHi20Fixup != NULL) { > + > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); > + if (Value2 & (RISCV_IMM_REACH/2)) { > + Value2 |= ~(RISCV_IMM_REACH-1); > + } > + Value += Value2; > + Value += (UINT32)Adjust; > + Value2 = RISCV_CONST_HIGH_PART (Value); > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\ > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12)); > + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\ > + (RV_X (*(UINT32 *)Fixup, 0, 20)); > + } > + break; > + > + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData)); > + if (RiscVHi20Fixup != NULL) { > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5)); > + if (Value2 & (RISCV_IMM_REACH/2)) { > + Value2 |= ~(RISCV_IMM_REACH-1); > + } > + Value += Value2; > + Value += (UINT32)Adjust; > + Value2 = RISCV_CONST_HIGH_PART (Value); > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \ > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12)); > + Value2 = *(UINT32 *)Fixup & 0x01fff07f; > + Value &= RISCV_IMM_REACH - 1; > + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25))); > + } > + break; > + > + default: > + return RETURN_UNSUPPORTED; > + > + } > + return RETURN_SUCCESS; > +} > + > +/** > + Returns TRUE if the machine type of PE/COFF image is supported. Supported > + does not mean the image can be executed it means the PE/COFF loader supports > + loading and relocating of the image type. It's up to the caller to support > + the entry point. > + > + @param Machine Machine type from the PE Header. > + > + @return TRUE if this PE/COFF loader can load the image > + > +**/ > +BOOLEAN > +PeCoffLoaderImageFormatSupported ( > + IN UINT16 Machine > + ) > +{ > + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine == IMAGE_FILE_MACHINE_RISCV64)) { > + return TRUE; > + } > + > + return FALSE; > +} > + > +/** > + Performs an Itanium-based specific re-relocation fixup and is a no-op on other > + instruction sets. This is used to re-relocated the image into the EFI virtual > + space for runtime calls. > + > + @param Reloc The pointer to the relocation record. > + @param Fixup The pointer to the address to fix up. > + @param FixupData The pointer to a buffer to log the fixups. > + @param Adjust The offset to adjust the fixup. > + > + @return Status code. > + > +**/ > +RETURN_STATUS > +PeHotRelocateImageEx ( > + IN UINT16 *Reloc, > + IN OUT CHAR8 *Fixup, > + IN OUT CHAR8 **FixupData, > + IN UINT64 Adjust > + ) > +{ > + return RETURN_UNSUPPORTED; > +} > -- > 2.7.4 > > > >