public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Leif Lindholm" <leif.lindholm@linaro.org>
To: devel@edk2.groups.io, abner.chang@hpe.com
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 13/22]: MdePkg/Include: Update SmBios header file.
Date: Thu, 5 Sep 2019 17:16:33 +0100	[thread overview]
Message-ID: <20190905161633.GF29255@bivouac.eciton.net> (raw)
In-Reply-To: <1567593797-26216-14-git-send-email-abner.chang@hpe.com>

On Wed, Sep 04, 2019 at 06:43:08PM +0800, Abner Chang wrote:
> Update SmBios header file to conform with SMBIOS v3.3.0.
> The major update is to add definitions of SMBIOS Type 44h record.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Abner Chang <abner.chang@hpe.com>

This would be really useful to get straight into edk2 - could you
submit it straight for inclusion in edk2 master? We can then
cherry-pick that back to the edk2-staging branch.

/
    Leif

> ---
>  MdePkg/Include/IndustryStandard/SmBios.h | 74 +++++++++++++++++++++++++++++++-
>  1 file changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
> index f3b6f18..a744d06 100644
> --- a/MdePkg/Include/IndustryStandard/SmBios.h
> +++ b/MdePkg/Include/IndustryStandard/SmBios.h
> @@ -3,6 +3,7 @@
>  
>  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
>  (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>
> +(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>  
>  **/
> @@ -46,7 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>  #define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
>  
>  //
> -// SMBIOS type macros which is according to SMBIOS 2.7 specification.
> +// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
>  //
>  #define SMBIOS_TYPE_BIOS_INFORMATION                     0
>  #define SMBIOS_TYPE_SYSTEM_INFORMATION                   1
> @@ -92,6 +93,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>  #define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
>  #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
>  #define SMBIOS_TYPE_TPM_DEVICE                           43
> +#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION     44
>  
>  ///
>  /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
> @@ -727,7 +729,10 @@ typedef enum {
>    ProcessorFamilyMII                   = 0x012E,
>    ProcessorFamilyWinChip               = 0x0140,
>    ProcessorFamilyDSP                   = 0x015E,
> -  ProcessorFamilyVideoProcessor        = 0x01F4
> +  ProcessorFamilyVideoProcessor        = 0x01F4,
> +  ProcessorFamilyRiscvRV32             = 0x0200,  ///< SMBIOS spec 3.3.0 added
> +  ProcessorFamilyRiscVRV64             = 0x0201,  ///< SMBIOS spec 3.3.0 added
> +  ProcessorFamilyRiscVRV128            = 0x0202   ///< SMBIOS spec 3.3.0 added
>  } PROCESSOR_FAMILY2_DATA;
>  
>  ///
> @@ -857,6 +862,19 @@ typedef struct {
>  } PROCESSOR_FEATURE_FLAGS;
>  
>  typedef struct {
> +  UINT32  ProcessorReserved1             :1;
> +  UINT32  ProcessorUnknown               :1;
> +  UINT32  Processor64BitCapble           :1;
> +  UINT32  ProcessorMultiCore             :1;
> +  UINT32  ProcessorHardwareThread        :1;
> +  UINT32  ProcessorExecuteProtection     :1;
> +  UINT32  ProcessorEnhancedVirtulization :1;
> +  UINT32  ProcessorPowerPerformanceCtrl  :1;
> +  UINT32  Processor128bitCapble          :1;
> +  UINT32  ProcessorReserved2             :7;
> +} PROCESSOR_CHARACTERISTIC_FLAGS;
> +
> +typedef struct {
>    PROCESSOR_SIGNATURE     Signature;
>    PROCESSOR_FEATURE_FLAGS FeatureFlags;
>  } PROCESSOR_ID_DATA;
> @@ -2508,6 +2526,57 @@ typedef struct {
>    UINT8                             InterfaceTypeSpecificData[4];   ///< This field has a minimum of four bytes
>  } SMBIOS_TABLE_TYPE42;
>  
> +
> +///
> +/// Processor Specific Block - Processor Architecture Type
> +///
> +typedef enum{
> +  ProcessorSpecificBlockArchTypeReserved   = 0x00,
> +  ProcessorSpecificBlockArchTypeIa32       = 0x01,
> +  ProcessorSpecificBlockArchTypeX64        = 0x02,
> +  ProcessorSpecificBlockArchTypeItanium    = 0x03,
> +  ProcessorSpecificBlockArchTypeAarch32    = 0x04,
> +  ProcessorSpecificBlockArchTypeAarch64    = 0x05,
> +  ProcessorSpecificBlockArchTypeRiscVRV32  = 0x06,
> +  ProcessorSpecificBlockArchTypeRiscVRV64  = 0x07,
> +  ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
> +} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
> +
> +///
> +/// Processor Specific Block is the standard container of processor-specific data.
> +///
> +typedef struct {
> +  UINT8                              Length;
> +  UINT8                              ProcessorArchType;
> +  ///
> +  /// Below followed by Processor-specific data
> +  ///
> +  ///
> +} PROCESSOR_SPECIFIC_BLOCK;
> +
> +///
> +/// Processor Additional Information(Type 44).
> +///
> +/// The information in this structure defines the processor additional information in case 
> +/// SMBIOS type 4 is not sufficient to describe processor characteristics.
> +/// The SMBIOS type 44 structure has a reference handle field to link back to the related 
> +/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the 
> +/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor, 
> +/// SMBIOS type 44 structures describe different core-specific information.
> +/// 
> +/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
> +/// contents of processor-specific data are maintained by processor 
> +/// architecture workgroups or vendors in separate documents.
> +///
> +typedef struct {
> +  SMBIOS_STRUCTURE                  Hdr;
> +  SMBIOS_HANDLE                     RefHandle;                 ///< This field refer to associated SMBIOS type 4
> +  ///
> +  /// Below followed by Processor-specific block
> +  ///
> +  PROCESSOR_SPECIFIC_BLOCK          ProcessorSpecificBlock;
> +} SMBIOS_TABLE_TYPE44;
> +
>  ///
>  /// TPM Device (Type 43).
>  ///
> @@ -2586,6 +2655,7 @@ typedef union {
>    SMBIOS_TABLE_TYPE41   *Type41;
>    SMBIOS_TABLE_TYPE42   *Type42;
>    SMBIOS_TABLE_TYPE43   *Type43;
> +  SMBIOS_TABLE_TYPE44   *Type44;
>    SMBIOS_TABLE_TYPE126  *Type126;
>    SMBIOS_TABLE_TYPE127  *Type127;
>    UINT8                 *Raw;
> -- 
> 2.7.4
> 
> 
> 
> 

  reply	other threads:[~2019-09-05 16:16 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-04 10:42 [PATCH 00/22] RISC-V EDK2 Port on edk2-staging/RISC-V-V2 branch Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 01/22]: RiscVPkg: RISC-V processor package Abner Chang
2019-09-04 17:51   ` [edk2-devel] " Leif Lindholm
2019-09-16  5:15     ` Abner Chang
2019-09-17 14:03       ` Leif Lindholm
2019-09-19  7:10         ` Abner Chang
2019-09-20 17:04           ` Leif Lindholm
2019-09-21  7:14             ` Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 02/22]: RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-04 18:55   ` [edk2-devel] " Leif Lindholm
2019-09-16  4:02     ` Abner Chang
2019-09-17 13:54       ` Leif Lindholm
2019-09-19  6:58         ` Abner Chang
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 03/22]: MdePkg: RISC-V sections in DEC file Abner Chang
2019-09-04 19:02   ` [edk2-devel] " Leif Lindholm
2019-09-16  5:16     ` Abner Chang
2019-09-16  9:17       ` Leif Lindholm
2019-09-04 10:42 ` [edk2-staging/RISC-V-V2 PATCH v1 04/22]: MdePkg/Include: RISC-V definitions Abner Chang
2019-09-04 20:40   ` [edk2-devel] " Leif Lindholm
2019-09-16  5:31     ` Abner Chang
2019-09-17 14:11       ` Leif Lindholm
2019-09-17  8:32     ` Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 05/22]: MdeModulePkg/CapsuleRuntimeDxe: Add RISC-V arch Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 6/22]: MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-09-04 20:49   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 07/22]: MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-05 14:28   ` [edk2-devel] " Leif Lindholm
2019-09-16  5:37     ` Abner Chang
2019-09-17 14:14       ` Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 08/22]: MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-09-05 14:38   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 09/22]: MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-05 14:42   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 10/22]: MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-05 14:51   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 11/22]: BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-05 15:44   ` [edk2-devel] " Leif Lindholm
2019-09-16  6:44     ` Abner Chang
2019-09-17 12:15       ` Leif Lindholm
2019-09-09 11:36   ` Leif Lindholm
2019-09-16  7:46     ` Abner Chang
2019-09-17 13:08       ` Leif Lindholm
2019-09-17 14:26         ` Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 12/22]: MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-05 16:11   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 13/22]: MdePkg/Include: Update SmBios header file Abner Chang
2019-09-05 16:16   ` Leif Lindholm [this message]
2019-09-16  7:01     ` [edk2-devel] " Abner Chang
2019-09-17 14:15       ` Leif Lindholm
     [not found]     ` <15C4D92300C8E997.28834@groups.io>
2019-09-17  6:58       ` Abner Chang
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 14/22]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Abner Chang
2019-09-05 16:19   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 15/22]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Abner Chang
2019-09-05 16:26   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 16/22]: RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-05 16:28   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 17/22]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS " Abner Chang
2019-09-05 16:31   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 18/22]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Abner Chang
2019-09-05 16:48   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 19/22]: MdeModulePkg/DxeIplPeim:RISC-V platform DXEIPL Abner Chang
2019-09-05 16:50   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 20/22]: MdeModulePkg/Logo Abner Chang
2019-09-05 16:51   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 21/22]: NetworkPkg Abner Chang
2019-09-05 16:52   ` [edk2-devel] " Leif Lindholm
2019-09-04 10:43 ` [edk2-staging/RISC-V-V2 PATCH v1 22/22]: BaseTools/Scripts Abner Chang
2019-09-05 16:54   ` [edk2-devel] " Leif Lindholm
2019-09-05 17:15 ` [edk2-devel] [PATCH 00/22] RISC-V EDK2 Port on edk2-staging/RISC-V-V2 branch Leif Lindholm
2019-09-06  1:27   ` Abner Chang
     [not found]   ` <15C1B52667BA1578.25810@groups.io>
2019-09-23  1:15     ` Abner Chang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190905161633.GF29255@bivouac.eciton.net \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox