From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=NWwXShOl; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Thu, 05 Sep 2019 09:16:37 -0700 Received: by mail-wr1-f67.google.com with SMTP id u16so3517341wrr.0 for ; Thu, 05 Sep 2019 09:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=i3z2guycTiiPYetgLVJ7B+QJowMzbMHCry4rgN2lOS8=; b=NWwXShOl4YZprP0XYICZvkSM/GS+h41sHm1ZA7naGMD2Bqgp5R1r+9qMRc5EtLBeLM bsOS2tQMIWvPThXp9utua7ugeLZ94rEGDhLnUfWtDhi8dNrD7hUnsDEqqNDA/3HErijY NQUdBwInfiIxOon3F3DQByTuwsboIPThXqSb89O5cA7K/ajo/HYnLU8yLeqDwnSSP0tu o+cZzNFSrQSlCqEjY8WCMdf5dFD2uBWtedUVYN99w/X+mLi26jDb1BL/yur+sNIQiBXJ KqCKzwzeyxlkxDo49QiFbGa0keAvcivEeOgYzkqDnYCSs757IrQrzQSU0raO3g3Ubf+2 FaSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=i3z2guycTiiPYetgLVJ7B+QJowMzbMHCry4rgN2lOS8=; b=bMNHxtrzrsvbiEYDyOcZuluLyxTKk8fsJNXwEcosRrbUmpCUKrnWPe4Ky9RS3e0Ahi 70qbkIUKW7/fnow5we2Sxd1d3wvjT21Zzhgafg56tFeigEArzUnMC90woTn2L52gxCrQ VzvmxNeUsg+HmMLzdoaAEHTjYvj0deinW5IrBv/qbwLFag51H/UMJ60V2K0K+nw6Kl3w Pca3XhkF+mbEh+JKe3K44F+kxNBdBIYtdjMY35U3YeciYRNuTHRdRDlm7JMv1cihDmlk vxhw5ELRcLpJl4PQCj85MQ2CChdIGyz3WPgMcuQ6AmfYmLBffmk5MfEyaPZWQgnYLTlz N+8Q== X-Gm-Message-State: APjAAAV7YWuN8udhHMAezp6kMV6FUL49krmlJ18zVJM+Le26/hFiLsdO Nk8742hdVITNOnBy3gS92W5IP27/Zs8= X-Google-Smtp-Source: APXvYqxtpg1dUEGt7I0a/swIGg5wQIglkl0esBVm+XfnZpoizf91t9kusGSVPF7hy2A5MJr2Q3Fcsw== X-Received: by 2002:adf:fad0:: with SMTP id a16mr3320652wrs.195.1567700195247; Thu, 05 Sep 2019 09:16:35 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id z189sm4535298wmc.25.2019.09.05.09.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 09:16:34 -0700 (PDT) Date: Thu, 5 Sep 2019 17:16:33 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 13/22]: MdePkg/Include: Update SmBios header file. Message-ID: <20190905161633.GF29255@bivouac.eciton.net> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> <1567593797-26216-14-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1567593797-26216-14-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 04, 2019 at 06:43:08PM +0800, Abner Chang wrote: > Update SmBios header file to conform with SMBIOS v3.3.0. > The major update is to add definitions of SMBIOS Type 44h record. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Abner Chang This would be really useful to get straight into edk2 - could you submit it straight for inclusion in edk2 master? We can then cherry-pick that back to the edk2-staging branch. / Leif > --- > MdePkg/Include/IndustryStandard/SmBios.h | 74 +++++++++++++++++++++++++++++++- > 1 file changed, 72 insertions(+), 2 deletions(-) > > diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h > index f3b6f18..a744d06 100644 > --- a/MdePkg/Include/IndustryStandard/SmBios.h > +++ b/MdePkg/Include/IndustryStandard/SmBios.h > @@ -3,6 +3,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
> +(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -46,7 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF > > // > -// SMBIOS type macros which is according to SMBIOS 2.7 specification. > +// SMBIOS type macros which is according to SMBIOS 3.3.0 specification. > // > #define SMBIOS_TYPE_BIOS_INFORMATION 0 > #define SMBIOS_TYPE_SYSTEM_INFORMATION 1 > @@ -92,6 +93,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41 > #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42 > #define SMBIOS_TYPE_TPM_DEVICE 43 > +#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44 > > /// > /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43. > @@ -727,7 +729,10 @@ typedef enum { > ProcessorFamilyMII = 0x012E, > ProcessorFamilyWinChip = 0x0140, > ProcessorFamilyDSP = 0x015E, > - ProcessorFamilyVideoProcessor = 0x01F4 > + ProcessorFamilyVideoProcessor = 0x01F4, > + ProcessorFamilyRiscvRV32 = 0x0200, ///< SMBIOS spec 3.3.0 added > + ProcessorFamilyRiscVRV64 = 0x0201, ///< SMBIOS spec 3.3.0 added > + ProcessorFamilyRiscVRV128 = 0x0202 ///< SMBIOS spec 3.3.0 added > } PROCESSOR_FAMILY2_DATA; > > /// > @@ -857,6 +862,19 @@ typedef struct { > } PROCESSOR_FEATURE_FLAGS; > > typedef struct { > + UINT32 ProcessorReserved1 :1; > + UINT32 ProcessorUnknown :1; > + UINT32 Processor64BitCapble :1; > + UINT32 ProcessorMultiCore :1; > + UINT32 ProcessorHardwareThread :1; > + UINT32 ProcessorExecuteProtection :1; > + UINT32 ProcessorEnhancedVirtulization :1; > + UINT32 ProcessorPowerPerformanceCtrl :1; > + UINT32 Processor128bitCapble :1; > + UINT32 ProcessorReserved2 :7; > +} PROCESSOR_CHARACTERISTIC_FLAGS; > + > +typedef struct { > PROCESSOR_SIGNATURE Signature; > PROCESSOR_FEATURE_FLAGS FeatureFlags; > } PROCESSOR_ID_DATA; > @@ -2508,6 +2526,57 @@ typedef struct { > UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes > } SMBIOS_TABLE_TYPE42; > > + > +/// > +/// Processor Specific Block - Processor Architecture Type > +/// > +typedef enum{ > + ProcessorSpecificBlockArchTypeReserved = 0x00, > + ProcessorSpecificBlockArchTypeIa32 = 0x01, > + ProcessorSpecificBlockArchTypeX64 = 0x02, > + ProcessorSpecificBlockArchTypeItanium = 0x03, > + ProcessorSpecificBlockArchTypeAarch32 = 0x04, > + ProcessorSpecificBlockArchTypeAarch64 = 0x05, > + ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06, > + ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07, > + ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08 > +} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE; > + > +/// > +/// Processor Specific Block is the standard container of processor-specific data. > +/// > +typedef struct { > + UINT8 Length; > + UINT8 ProcessorArchType; > + /// > + /// Below followed by Processor-specific data > + /// > + /// > +} PROCESSOR_SPECIFIC_BLOCK; > + > +/// > +/// Processor Additional Information(Type 44). > +/// > +/// The information in this structure defines the processor additional information in case > +/// SMBIOS type 4 is not sufficient to describe processor characteristics. > +/// The SMBIOS type 44 structure has a reference handle field to link back to the related > +/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the > +/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor, > +/// SMBIOS type 44 structures describe different core-specific information. > +/// > +/// SMBIOS type 44 defines the standard header for the processor-specific block, while the > +/// contents of processor-specific data are maintained by processor > +/// architecture workgroups or vendors in separate documents. > +/// > +typedef struct { > + SMBIOS_STRUCTURE Hdr; > + SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4 > + /// > + /// Below followed by Processor-specific block > + /// > + PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock; > +} SMBIOS_TABLE_TYPE44; > + > /// > /// TPM Device (Type 43). > /// > @@ -2586,6 +2655,7 @@ typedef union { > SMBIOS_TABLE_TYPE41 *Type41; > SMBIOS_TABLE_TYPE42 *Type42; > SMBIOS_TABLE_TYPE43 *Type43; > + SMBIOS_TABLE_TYPE44 *Type44; > SMBIOS_TABLE_TYPE126 *Type126; > SMBIOS_TABLE_TYPE127 *Type127; > UINT8 *Raw; > -- > 2.7.4 > > > >