* [PATCH 00/15] [platforms/devel-riscv-v2]: Add SiFive U500 VC707 FPGA Platform
@ 2019-09-05 1:23 Gilbert Chen
2019-09-06 16:40 ` [edk2-devel] " Leif Lindholm
0 siblings, 1 reply; 2+ messages in thread
From: Gilbert Chen @ 2019-09-05 1:23 UTC (permalink / raw)
To: devel@edk2.groups.io
"devel-riscv-v2" is a new branch created for reviewing code changes of SiFive U500 VC707 FPGA
platform EDK2 port. Compare to old "devel-riscv" branch, the patches sent to "devel-riscv-v2"
branch are made based on the most recent edk2/master. The corresponding patches of
edk2 code changes were sent to edk2 devel mail list with [edk2-staging/RISC-V-V2] in
patch message subject.
Gilbert Chen (15):
[platforms/devel-riscv-v2]: Silicon/SiFive: Initial version of SiFive
silicon package
[platforms/devel-riscv-v2]: Silicon/SiFive: Add library module of
SiFive RISC-V cores
[platforms/devel-riscv-v2]: platforms/RiscV: Initial version of RISC-V
platform package
[platforms/devel-riscv-v2]: RiscV/Include: Initial version of header
files in RISC-V platform package
[platforms/devel-riscv-v2]: RiscV/Library: Initial version of
libraries introduced in RISC-V platform package
[platforms/devel-riscv-v2]: RiscV/Universal: Initial version of common
RISC-V SEC module
[platforms/devel-riscv-v2]: RiscV/SiFive: Initial version of SiFive
U500 platform package
[platforms/devel-riscv-v2]: U500Pkg/Include: Header files of SiFive
U500 platform
[platforms/devel-riscv-v2]: U500Pkg/Library: Initial version of
PlatformBootManagerLib
[platforms/devel-riscv-v2]: U500Pkg/Library: Library instances of U500
platform library.
[platforms/devel-riscv-v2]: U500Pkg/RamFvbServiceruntimeDxe: FVB
driver for EFI variable.
[platforms/devel-riscv-v2]: U500Pkg/TimerDxe: Platform Timer DXE
driver
[platforms/devel-riscv-v2]: U500Pkg/PlatformPei: Platform
initialization PEIM
[platforms/devel-riscv-v2]: Platforms: Readme file updates
[platforms/devel-riscv-v2]: U500Pkg: Update Readme.md
Maintainers.txt | 9 +
.../Library/FirmwareContextProcessorSpecificLib.h | 47 +
.../FirmwareContextProcessorSpecificLib.c | 88 ++
.../FirmwareContextProcessorSpecificLib.inf | 39 +
.../RealTimeClockLibNull/RealTimeClockLibNull.c | 212 ++++
.../RealTimeClockLibNull/RealTimeClockLibNull.inf | 36 +
Platform/RiscV/Readme.md | 89 ++
Platform/RiscV/RiscVPlatformPkg.dec | 79 ++
Platform/RiscV/RiscVPlatformPkg.uni | Bin 0 -> 1754 bytes
Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
.../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h | 57 +
Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h | 24 +
.../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 53 +
.../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 ++++
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 201 ++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 64 ++
.../Library/PlatformBootManagerLib/MemoryTest.c | 689 ++++++++++++
.../PlatformBootManagerLib/PlatformBootManager.c | 280 +++++
.../PlatformBootManagerLib/PlatformBootManager.h | 140 +++
.../PlatformBootManagerLib.inf | 69 ++
.../Library/PlatformBootManagerLib/PlatformData.c | 54 +
.../Library/PlatformBootManagerLib/Strings.uni | Bin 0 -> 3922 bytes
.../RiscVPlatformTimerLib.inf | 46 +
.../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s | 54 +
.../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 37 +
.../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 247 +++++
.../Library/SerialIoLib/U500SerialPortLib.uni | 22 +
Platform/RiscV/SiFive/U500Pkg/Readme.md | 62 ++
Platform/RiscV/SiFive/U500Pkg/U500.dec | 40 +
Platform/RiscV/SiFive/U500Pkg/U500.dsc | 555 ++++++++++
Platform/RiscV/SiFive/U500Pkg/U500.fdf | 342 ++++++
Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc | 58 +
Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
.../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 133 +++
.../FvbServicesRuntimeDxe.inf | 88 ++
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1129 ++++++++++++++++++++
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 193 ++++
.../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 156 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 151 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 92 ++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 26 +
.../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c | 317 ++++++
.../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h | 179 ++++
.../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni | Bin 0 -> 1678 bytes
.../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf | 54 +
.../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni | Bin 0 -> 1374 bytes
.../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 55 +
.../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 80 ++
.../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 319 ++++++
.../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 97 ++
.../Universal/Pei/PlatformPei/PlatformPei.inf | 82 ++
Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc | 85 ++
Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 ++++++++
Platform/RiscV/Universal/Sec/SecMain.c | 529 +++++++++
Platform/RiscV/Universal/Sec/SecMain.h | 56 +
Platform/RiscV/Universal/Sec/SecMain.inf | 81 ++
Readme.md | 11 +
.../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 248 +++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 57 +
Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++
Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++
.../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 61 ++
Silicon/SiFive/SiFive.dec | 45 +
.../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 300 ++++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 57 +
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 191 ++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 56 +
68 files changed, 9406 insertions(+)
create mode 100644 Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
create mode 100644 Platform/RiscV/Readme.md
create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc
create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c
create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h
create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
create mode 100644 Silicon/SiFive/SiFive.dec
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [edk2-devel] [PATCH 00/15] [platforms/devel-riscv-v2]: Add SiFive U500 VC707 FPGA Platform
2019-09-05 1:23 [PATCH 00/15] [platforms/devel-riscv-v2]: Add SiFive U500 VC707 FPGA Platform Gilbert Chen
@ 2019-09-06 16:40 ` Leif Lindholm
0 siblings, 0 replies; 2+ messages in thread
From: Leif Lindholm @ 2019-09-06 16:40 UTC (permalink / raw)
To: devel, gilbert.chen; +Cc: Abner Chang
Hi Gilbert,
Thank you for this set.
However, the patches are too corrupted by Outlook/Exchange for me to
be able to apply them. You need to use git send-email to send patches
- Abner should be able to show you what he did with the edk2 set.
It would also help if you executed
<edk2>/BaseTools/Scripts/SetupGit.py (while in the edk2-platforms
directory), in order to set up some useful defaults in the local
config, before regenerating this set to resend.
Please add myself and Mike Kinney to cc as well.
Best Regards,
Leif
On Thu, Sep 05, 2019 at 01:23:54AM +0000, Gilbert Chen wrote:
> "devel-riscv-v2" is a new branch created for reviewing code changes of SiFive U500 VC707 FPGA
> platform EDK2 port. Compare to old "devel-riscv" branch, the patches sent to "devel-riscv-v2"
> branch are made based on the most recent edk2/master. The corresponding patches of
> edk2 code changes were sent to edk2 devel mail list with [edk2-staging/RISC-V-V2] in
> patch message subject.
>
> Gilbert Chen (15):
> [platforms/devel-riscv-v2]: Silicon/SiFive: Initial version of SiFive
> silicon package
> [platforms/devel-riscv-v2]: Silicon/SiFive: Add library module of
> SiFive RISC-V cores
> [platforms/devel-riscv-v2]: platforms/RiscV: Initial version of RISC-V
> platform package
> [platforms/devel-riscv-v2]: RiscV/Include: Initial version of header
> files in RISC-V platform package
> [platforms/devel-riscv-v2]: RiscV/Library: Initial version of
> libraries introduced in RISC-V platform package
> [platforms/devel-riscv-v2]: RiscV/Universal: Initial version of common
> RISC-V SEC module
> [platforms/devel-riscv-v2]: RiscV/SiFive: Initial version of SiFive
> U500 platform package
> [platforms/devel-riscv-v2]: U500Pkg/Include: Header files of SiFive
> U500 platform
> [platforms/devel-riscv-v2]: U500Pkg/Library: Initial version of
> PlatformBootManagerLib
> [platforms/devel-riscv-v2]: U500Pkg/Library: Library instances of U500
> platform library.
> [platforms/devel-riscv-v2]: U500Pkg/RamFvbServiceruntimeDxe: FVB
> driver for EFI variable.
> [platforms/devel-riscv-v2]: U500Pkg/TimerDxe: Platform Timer DXE
> driver
> [platforms/devel-riscv-v2]: U500Pkg/PlatformPei: Platform
> initialization PEIM
> [platforms/devel-riscv-v2]: Platforms: Readme file updates
> [platforms/devel-riscv-v2]: U500Pkg: Update Readme.md
>
> Maintainers.txt | 9 +
> .../Library/FirmwareContextProcessorSpecificLib.h | 47 +
> .../FirmwareContextProcessorSpecificLib.c | 88 ++
> .../FirmwareContextProcessorSpecificLib.inf | 39 +
> .../RealTimeClockLibNull/RealTimeClockLibNull.c | 212 ++++
> .../RealTimeClockLibNull/RealTimeClockLibNull.inf | 36 +
> Platform/RiscV/Readme.md | 89 ++
> Platform/RiscV/RiscVPlatformPkg.dec | 79 ++
> Platform/RiscV/RiscVPlatformPkg.uni | Bin 0 -> 1754 bytes
> Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
> .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h | 57 +
> Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h | 24 +
> .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 53 +
> .../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 ++++
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 201 ++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 64 ++
> .../Library/PlatformBootManagerLib/MemoryTest.c | 689 ++++++++++++
> .../PlatformBootManagerLib/PlatformBootManager.c | 280 +++++
> .../PlatformBootManagerLib/PlatformBootManager.h | 140 +++
> .../PlatformBootManagerLib.inf | 69 ++
> .../Library/PlatformBootManagerLib/PlatformData.c | 54 +
> .../Library/PlatformBootManagerLib/Strings.uni | Bin 0 -> 3922 bytes
> .../RiscVPlatformTimerLib.inf | 46 +
> .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s | 54 +
> .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 37 +
> .../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 247 +++++
> .../Library/SerialIoLib/U500SerialPortLib.uni | 22 +
> Platform/RiscV/SiFive/U500Pkg/Readme.md | 62 ++
> Platform/RiscV/SiFive/U500Pkg/U500.dec | 40 +
> Platform/RiscV/SiFive/U500Pkg/U500.dsc | 555 ++++++++++
> Platform/RiscV/SiFive/U500Pkg/U500.fdf | 342 ++++++
> Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc | 58 +
> Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
> Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
> .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 133 +++
> .../FvbServicesRuntimeDxe.inf | 88 ++
> .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1129 ++++++++++++++++++++
> .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 193 ++++
> .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 156 +++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 151 +++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 92 ++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 26 +
> .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c | 317 ++++++
> .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h | 179 ++++
> .../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni | Bin 0 -> 1678 bytes
> .../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf | 54 +
> .../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni | Bin 0 -> 1374 bytes
> .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 55 +
> .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 80 ++
> .../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 319 ++++++
> .../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 97 ++
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 82 ++
> Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc | 85 ++
> Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 ++++++++
> Platform/RiscV/Universal/Sec/SecMain.c | 529 +++++++++
> Platform/RiscV/Universal/Sec/SecMain.h | 56 +
> Platform/RiscV/Universal/Sec/SecMain.inf | 81 ++
> Readme.md | 11 +
> .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 248 +++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 57 +
> Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++
> Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++
> .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 61 ++
> Silicon/SiFive/SiFive.dec | 45 +
> .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 300 ++++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 57 +
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 191 ++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 56 +
> 68 files changed, 9406 insertions(+)
> create mode 100644 Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
> create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
> create mode 100644 Platform/RiscV/Readme.md
> create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
> create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
> create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf
> create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc
> create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
> create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c
> create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h
> create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
> create mode 100644 Silicon/SiFive/SiFive.dec
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
>
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-09-06 16:40 UTC | newest]
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2019-09-05 1:23 [PATCH 00/15] [platforms/devel-riscv-v2]: Add SiFive U500 VC707 FPGA Platform Gilbert Chen
2019-09-06 16:40 ` [edk2-devel] " Leif Lindholm
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