From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=WrX5cun3; spf=pass (domain: linaro.org, ip: 209.85.221.68, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by groups.io with SMTP; Tue, 17 Sep 2019 07:14:23 -0700 Received: by mail-wr1-f68.google.com with SMTP id r3so3352664wrj.6 for ; Tue, 17 Sep 2019 07:14:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=NP9wmEVIOZwK2cc+KouoMgsRBZZR729u0koma9OLm8g=; b=WrX5cun3n9jrWOZ4cJAafO4mKcvyYeWAvA8430Ah3GZLmcaARBn1XT8YfvLFlHyh1x EaPL/cclKBp6AZc2FqIu69l/F9nwKCmZl9H0oTPpV+3GKSZX+0NU7r7UMJzvH5xA9Ds6 jVYiG7Ovagb0BQGXmQdDYv8nGyPxUfPQH8bt5xyv6uGdlIqMWzH7FsNRqu8yA4yLPTGC sc3+bBi7rEXbkoIFaRmTwAiseaE1SUVR3TMG0NGCMnBa/4Mfo+YUFd0LSVaDQQjFFGkO q4VrrvEPEOnWlMBEx8o27hNF9IJ0cHPVzfG32AI0RJUXdsk/475I4bq2QOdBkMPE+NXZ nJtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=NP9wmEVIOZwK2cc+KouoMgsRBZZR729u0koma9OLm8g=; b=JLfIxgmr4Z08k9ILVQFzMWsH38EHyFfJb5uJWvSKsck/VCTbAx72aenpvWc/62K+ol O5pfB0xo21YWR73CPAeleyH/Jr5vzZR+LuAT0opUONbuKZOAc0RwgpdX+GYs9Wl1yuKC moakO4yx7l+Lb9ZrNOQ5PyRYKzt70UdZERMQfVWJUeIhaWuw4wlmv9Y6/SOLt14SYKAR RtSEe/Syj94i5qm4LlrYt+V0V+PMe2c0yPzSWUSCGFVeRuKAMmNI0rg+YYA1rZstf68Q tDFTV7GSJbcZQOBwZ9V7AMLVELo3/98YV/6g0JkWmbj14xOiIGeUz+migQ8SEt26C2KI eJlA== X-Gm-Message-State: APjAAAXskdJlyU5O9La8ItX0NMtIv3YIkUjfbEyjzU06qywzSvXJpGI3 +Bp9dPPAmE+iGLoFtFnCIosWXAxTGfk= X-Google-Smtp-Source: APXvYqxCxH6Ynba1v0/e77aCTHtQeLGPxV/veIwt2qMkG4i9mncmSX3zHNnBHm4qLHH6ygsFn3UhnA== X-Received: by 2002:adf:e390:: with SMTP id e16mr3327597wrm.29.1568729661811; Tue, 17 Sep 2019 07:14:21 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v11sm3907231wrv.54.2019.09.17.07.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2019 07:14:21 -0700 (PDT) Date: Tue, 17 Sep 2019 15:14:19 +0100 From: "Leif Lindholm" To: "Chang, Abner (HPS SW/FW Technologist)" Cc: "devel@edk2.groups.io" Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 07/22]: MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. Message-ID: <20190917141419.GH28454@bivouac.eciton.net> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> <1567593797-26216-8-git-send-email-abner.chang@hpe.com> <20190905142814.GY29255@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 16, 2019 at 05:37:51AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote: > > -----Original Message----- > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org] > > Sent: Thursday, September 5, 2019 10:28 PM > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) > > > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 07/22]: > > MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. > > > > On Wed, Sep 04, 2019 at 06:43:02PM +0800, Abner Chang wrote: > > > RISC-V MMIO library instance. RISC-V only supports memory map I/O. > > > However the first implementation of RISC-V EDK2 port uses PC/AT as the > > > RISC-V platform spec. We have to keep the I/O functions as the temporary > > solution. > > > > Can you expand on the I/O port situation? > > Since the architecture doesn't support it, what do these functions do? > > > > For the pure MMIO ops using compliant C, we really don't need yet another > > implementation pretending it's architecture specific. We should just have a > > single IoLibMmio.c and an IoLibMmioNonCompliant.c if the x86 folks want to > > keep their current one. > > Hmm. That was for the old RISC-V PC/AT QEUM version back to 2016. We > pulled in some X86 peripherals to build up RISC-V PC/AT like > platform . will remove this. Excellent, thanks. / Leif