From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: john.e.lofgren@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Tue, 17 Sep 2019 15:49:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2019 15:49:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,518,1559545200"; d="scan'208";a="189072271" Received: from jelofgre-desk.amr.corp.intel.com ([10.78.26.249]) by orsmga003.jf.intel.com with ESMTP; 17 Sep 2019 15:49:15 -0700 From: "John E Lofgren" To: devel@edk2.groups.io Subject: [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock Date: Tue, 17 Sep 2019 15:49:10 -0700 Message-Id: <20190917224910.28040-1-john.e.lofgren@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 V3 changes: change to mov instruction (non locking instuction) instead of xchg to simplify design. V2 changes: Add xchg 16 bit instructions to handle sgdt and sidt base 63:48 bits and 47:32 bits. Add comment to explain why xchg 64bit isnt being used Split lock happens when a locking instruction is used on mis-aligned data that crosses two cachelines. If close source platform enables Alignment Check Exception(#AC), They can hit a double fault due to split lock being in CpuExceptionHandlerLib. sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. The data is mis-aligned, can cross two cacheline, and a xchg instruction(locking instuction) is being utilize. Signed-off-by: John E Lofgren --- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 4db1a09f28..7b7642b290 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -180,21 +180,29 @@ HasErrorCode: push qword [rbp + 24] ;; UINT64 Gdtr[2], Idtr[2]; + ; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes = limit. + ; To avoid #AC split lock when separating base and limit into their + ; own separate 64 bit memory, we can’t use 64 bit xchg since base [63:48] bits + ; may cross the cache line. xor rax, rax push rax push rax sidt [rsp] - xchg rax, [rsp + 2] - xchg rax, [rsp] - xchg rax, [rsp + 8] + xchg eax, [rsp + 2] + xchg eax, [rsp] + xchg eax, [rsp + 8] + xchg ax, [rsp + 6] + xchg ax, [rsp + 4] xor rax, rax push rax push rax sgdt [rsp] - xchg rax, [rsp + 2] - xchg rax, [rsp] - xchg rax, [rsp + 8] + xchg eax, [rsp + 2] + xchg eax, [rsp] + xchg eax, [rsp + 8] + xchg ax, [rsp + 6] + xchg ax, [rsp + 4] ;; UINT64 Ldtr, Tr; xor rax, rax -- 2.16.2.windows.1