From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=X5lT7uD9; spf=pass (domain: linaro.org, ip: 209.85.128.68, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by groups.io with SMTP; Thu, 19 Sep 2019 04:25:35 -0700 Received: by mail-wm1-f68.google.com with SMTP id v17so3511387wml.4 for ; Thu, 19 Sep 2019 04:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=DuHkVxHjNQFp2X5pLAnOaVhTL8FUspynBGGUqyXYV+Y=; b=X5lT7uD9OuGcf1r1te0F8SroU8etSl1F0eAz7HdVZeV+AbfzFnEa69D8FovQd8GYtA 3kL/K7OaV3mgIfKJ40b6CCYj105QQKj7LWzfOFwCcf/3c7dxuxpVWWf5lA/gd6LSKSwT BP0Qd0EnIVi7XMA+keEyaAggGLI/Cbb00vJA0+Q2DKGXnS2JokpP6dln63m6Cqs3B1mh MdQAZdTVYUDH4H30DBB9vrpsOqpCJs3zvmVgWwjzydDxOinSM8f9ucyOjIh+gBgNy5yw NAjJ3eKPF8ex4RQI0psO+CoRqK8iDwXVuGRSzHGYP8cjFWQ57essh1h9MhhqGBvcjRsJ 3LvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=DuHkVxHjNQFp2X5pLAnOaVhTL8FUspynBGGUqyXYV+Y=; b=JcFpxx/82D72J9pLHGT+4UCuO7WWtcmJEH6dkMe543Zx569tnu7s5iQgH71uzvIUdB uo35yiUfL35MyhcWUK3hM4JPsbZbB7tYMwT9MdZF9pzgTTPNQb80g/VryekwsKVOrNZD p6oTelC6OCkUE9uVSfe1z04BYesJ9NSPJ230+6hoKgqyMuKR01k1IuOri0IBeyp4y/jd KtDvi7/fASAnVHIoHujjGpI6pOo0vHnXrH51wP0CNQVkUaiQX9SbJ8hPDWx2TqhRE+Fy Lwvrl03uEbzpnEPLiasEh4xg+BNMBfLj70Pt7Y88pTkLErgHpzDX51qU+sA9YkCZ2hm6 ZpAw== X-Gm-Message-State: APjAAAXF9fIcqaGJAWPNrq/pKxoJ0BdrnQj4uxNeP7wr+M8ysKFqS+zz V3E7KsfLiNAEpYGEZ+Mcff8fGw== X-Google-Smtp-Source: APXvYqxWTzHw5G0+wT4G/xz5XMxcWk9UgOmaA5imsjsYh+Lg7JS+fLRk3uzUjdJOxZ9WvxOJ2xgh6A== X-Received: by 2002:a1c:a54c:: with SMTP id o73mr2382327wme.68.1568892333528; Thu, 19 Sep 2019 04:25:33 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id s9sm7469517wme.36.2019.09.19.04.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2019 04:25:32 -0700 (PDT) Date: Thu, 19 Sep 2019 12:25:31 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: Baptiste Gerondeau , edk2-devel-groups-io , "Kinney, Michael D" , "Gao, Liming" , "Zhang, Shenglei" , Baptiste GERONDEAU Subject: Re: [PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT Message-ID: <20190919112531.GU28454@bivouac.eciton.net> References: <0d024d72b50b7f5a6d3d908d309810f350c5b1f5.1568808805.git.baptiste.gerondeau@linaro.org> <20190919094846.GO28454@bivouac.eciton.net> <20190919100921.GR28454@bivouac.eciton.net> <20190919104711.GT28454@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 19, 2019 at 01:53:35PM +0300, Ard Biesheuvel wrote: > > > I mean that I'd prefer to assemble the .asm files in ARM mode, > > > especially since I am not convinced that the startup code we have is > > > guaranteed to switch into the right mode after the CPU comes out of > > > reset in ARM mode. > > > > That could be resolved with a trivial branch at that point (or just > > forcing ARM for the whole entry file) though. > > > > Of course. > > The problem is that the first branch instruction is patched into the > FV files by the BaseTools, and so the startup code is entered in ARM > mode by default. > > So that means we'll either have to > 1) switch to ARM mode > 2) emit one branch instruction > 3) switch back to Thumb mode I was thinking more like tying down the entry function (or as I said, the whole file) as ARM, then letting the toolchain decide for the bits where we don't have instuction-set dependent ABIs. > 4) fix up all the code so it assembles in Thumb mode Which is what Baptiste has done in this set. > 1) switch to ARM mode In all 48 files (+3 in edk2-platforms), or just the ones where not doing so triggers build errors? Currently. I'm OK with restricting ourselves to just setting ARM in the triggering files for simplicity, especially in order to streamline the toolchain migration from RVCT to VS (and the subsequent purge of PVCT support). I'm not seeing it as a solution. / Leif