[PATCH 0/1] Fix eMMC bus timing switch issue

["Albecki, Mateusz" <mateusz.albecki@intel.com>]

SD host controller specification section 3.9 recommends that controller's bus timing
should be switched after card's bus timing has been switched. In current eMMC
driver implementation every host controller switch has been done before call to
EmmcSwitchBusTiming which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when
switching the host controller timing. Stopping the clock before bus timing
switch is only neccessary if preset value enable is set in host controller.
Current code doesn't check if this field is enabled or doesn't support
this feature for any other bus timing change so it has been removed.

Tests performed:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been failing
with old driver and one that has been passing with old driver. Both controllers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both new flow
and old flow was failing with this speed. I suspect it is a hardware problem.

Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>

Albecki, Mateusz (1):
  MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++----------------------
 1 file changed, 5 insertions(+), 49 deletions(-)

-- 
2.14.1.windows.1

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