From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Tue, 24 Sep 2019 04:35:17 -0700 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2C5EB18C4285; Tue, 24 Sep 2019 11:35:17 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-118.rdu2.redhat.com [10.10.120.118]) by smtp.corp.redhat.com (Postfix) with ESMTP id 82885600CC; Tue, 24 Sep 2019 11:35:14 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Boris Ostrovsky , Brijesh Singh , Igor Mammedov , Jiewen Yao , Joao M Martins , Jordan Justen , Jun Nakajima , Michael Kinney , Paolo Bonzini , Phillip Goerl , Yingwen Chen Subject: [PATCH wave 1 02/10] OvmfPkg/IndustryStandard: increase vertical whitespace in Q35 macro defs Date: Tue, 24 Sep 2019 13:34:57 +0200 Message-Id: <20190924113505.27272-3-lersek@redhat.com> In-Reply-To: <20190924113505.27272-1-lersek@redhat.com> References: <20190924113505.27272-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.62]); Tue, 24 Sep 2019 11:35:17 +0000 (UTC) Content-Transfer-Encoding: quoted-printable In a subsequent patch, we'll introduce new DRAM controller macros in "Q35MchIch9.h". Their names are too long for the currently available vertical whitespace, so increase the latter first. There is no functional change in this patch ("git show -b" displays nothing). Cc: Ard Biesheuvel Cc: Boris Ostrovsky Cc: Brijesh Singh Cc: Igor Mammedov Cc: Jiewen Yao Cc: Joao M Martins Cc: Jordan Justen Cc: Jun Nakajima Cc: Michael Kinney Cc: Paolo Bonzini Cc: Phillip Goerl Cc: Yingwen Chen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1512 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 100 ++++++++++---------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Incl= ude/IndustryStandard/Q35MchIch9.h index 391cb4622226..614699ab38f1 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -27,56 +27,56 @@ // #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) =20 -#define MCH_EXT_TSEG_MB 0x50 -#define MCH_EXT_TSEG_MB_QUERY 0xFFFF - -#define MCH_GGC 0x52 -#define MCH_GGC_IVD BIT1 - -#define MCH_PCIEXBAR_LOW 0x60 -#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF -#define MCH_PCIEXBAR_BUS_FF 0 -#define MCH_PCIEXBAR_EN BIT0 - -#define MCH_PCIEXBAR_HIGH 0x64 -#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 - -#define MCH_PAM0 0x90 -#define MCH_PAM1 0x91 -#define MCH_PAM2 0x92 -#define MCH_PAM3 0x93 -#define MCH_PAM4 0x94 -#define MCH_PAM5 0x95 -#define MCH_PAM6 0x96 - -#define MCH_SMRAM 0x9D -#define MCH_SMRAM_D_LCK BIT4 -#define MCH_SMRAM_G_SMRAME BIT3 - -#define MCH_ESMRAMC 0x9E -#define MCH_ESMRAMC_H_SMRAME BIT7 -#define MCH_ESMRAMC_E_SMERR BIT6 -#define MCH_ESMRAMC_SM_CACHE BIT5 -#define MCH_ESMRAMC_SM_L1 BIT4 -#define MCH_ESMRAMC_SM_L2 BIT3 -#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) -#define MCH_ESMRAMC_TSEG_8MB BIT2 -#define MCH_ESMRAMC_TSEG_2MB BIT1 -#define MCH_ESMRAMC_TSEG_1MB 0 -#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) -#define MCH_ESMRAMC_T_EN BIT0 - -#define MCH_GBSM 0xA4 -#define MCH_GBSM_MB_SHIFT 20 - -#define MCH_BGSM 0xA8 -#define MCH_BGSM_MB_SHIFT 20 - -#define MCH_TSEGMB 0xAC -#define MCH_TSEGMB_MB_SHIFT 20 - -#define MCH_TOLUD 0xB0 -#define MCH_TOLUD_MB_SHIFT 4 +#define MCH_EXT_TSEG_MB 0x50 +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF + +#define MCH_GGC 0x52 +#define MCH_GGC_IVD BIT1 + +#define MCH_PCIEXBAR_LOW 0x60 +#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF +#define MCH_PCIEXBAR_BUS_FF 0 +#define MCH_PCIEXBAR_EN BIT0 + +#define MCH_PCIEXBAR_HIGH 0x64 +#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 + +#define MCH_PAM0 0x90 +#define MCH_PAM1 0x91 +#define MCH_PAM2 0x92 +#define MCH_PAM3 0x93 +#define MCH_PAM4 0x94 +#define MCH_PAM5 0x95 +#define MCH_PAM6 0x96 + +#define MCH_SMRAM 0x9D +#define MCH_SMRAM_D_LCK BIT4 +#define MCH_SMRAM_G_SMRAME BIT3 + +#define MCH_ESMRAMC 0x9E +#define MCH_ESMRAMC_H_SMRAME BIT7 +#define MCH_ESMRAMC_E_SMERR BIT6 +#define MCH_ESMRAMC_SM_CACHE BIT5 +#define MCH_ESMRAMC_SM_L1 BIT4 +#define MCH_ESMRAMC_SM_L2 BIT3 +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) +#define MCH_ESMRAMC_TSEG_8MB BIT2 +#define MCH_ESMRAMC_TSEG_2MB BIT1 +#define MCH_ESMRAMC_TSEG_1MB 0 +#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) +#define MCH_ESMRAMC_T_EN BIT0 + +#define MCH_GBSM 0xA4 +#define MCH_GBSM_MB_SHIFT 20 + +#define MCH_BGSM 0xA8 +#define MCH_BGSM_MB_SHIFT 20 + +#define MCH_TSEGMB 0xAC +#define MCH_TSEGMB_MB_SHIFT 20 + +#define MCH_TOLUD 0xB0 +#define MCH_TOLUD_MB_SHIFT 4 =20 // // B/D/F/Type: 0/0x1f/0/PCI --=20 2.19.1.3.g30247aa5d201