From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: michael.a.kubacki@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Tue, 24 Sep 2019 11:13:29 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2019 11:13:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,545,1559545200"; d="scan'208";a="340160769" Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga004.jf.intel.com with ESMTP; 24 Sep 2019 11:13:27 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Ankit Sinha , Jeremy Soller Subject: [edk2-platforms][PATCH V2 09/15] KabylakeOpenBoardPkg/GalagoPro3: Add library instances Date: Tue, 24 Sep 2019 11:12:42 -0700 Message-Id: <20190924181248.12816-10-michael.a.kubacki@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20190924181248.12816-1-michael.a.kubacki@intel.com> References: <20190924181248.12816-1-michael.a.kubacki@intel.com> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2207 Adds the library class instances for System 76 Galago Pro 3 board support. * PeiSiliconPolicyNotifyLib * PeiSiliconPolicyUpdateLibFsp * BasePlatformHookLib * BoardAcpiLib * BoardInitLib * DxeSiliconPolicyUpdateLib Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Jeremy Soller Signed-off-by: Michael Kubacki --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 43 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 146 +++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf | 51 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 47 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf | 48 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 47 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 48 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf | 53 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 131 ++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 55 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 130 ++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 49 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 28 + Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 30 + Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitLib.h | 42 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h | 64 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c | 103 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 115 ++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 87 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 186 ++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 155 +++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 248 ++++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 84 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 75 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.c | 662 ++++++++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 36 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeGalagoPro3AcpiTableLib.c | 74 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 43 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 62 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmGalagoPro3AcpiEnableLib.c | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 81 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 168 +++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3GpioTable.c | 370 +++++++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HdaVerbTables.c | 232 +++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HsioPtssTables.c | 105 ++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.c | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 105 ++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3Detect.c | 66 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPostMemLib.c | 209 ++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 236 +++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c | 40 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c | 82 +++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 175 ++++++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 65 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c | 54 ++ 46 files changed, 5047 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf new file mode 100644 index 0000000000..13c12655f6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf @@ -0,0 +1,43 @@ +## @file +# Component information file for Silicon Policy Notify Library. +# This library implements constructor function to register notify call back +# when policy PPI installed. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPreMemSiliconPolicyNotifyLib + FILE_GUID = 6D231E12-C088-47C8-8B16-61F07293EEF8 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiPreMemSiliconPolicyNotifyLibConstructor + +[LibraryClasses] + BaseLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiPreMemSiliconPolicyNotifyLib.c + +[Guids] + gSaMiscPeiPreMemConfigGuid + +[Ppis] + gSiPreMemPolicyPpiGuid + +[Pcd] + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..41deee1c97 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,146 @@ +## @file +# FSP wrapper silicon policy update library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconPolicyUpdateLibFsp + FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiFspPolicyUpdateLib.c + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSaPolicyUpdate.c + PeiFspMiscUpdUpdateLib.c + PcieDeviceTable.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeFspBinPkg/KabylakeFspBinPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses.IA32] + FspWrapperApiLib + OcWdtLib + PchResetLib + FspWrapperPlatformLib + BaseMemoryLib + CpuPlatformLib + DebugLib + HobLib + IoLib + PcdLib + PostCodeLib + SmbusLib + MmPciLib + ConfigBlockLib + PeiSaPolicyLib + PchGbeLib + PchInfoLib + PchHsioLib + PchPcieRpLib + MemoryAllocationLib + CpuMailboxLib + DebugPrintErrorLevelLib + SiPolicyLib + PchGbeLib + TimerLib + GpioLib + PeiLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 + gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 + gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable + + gBoardModuleTokenSpaceGuid.PcdAudioConnector + + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + +[Guids] + gFspNonVolatileStorageHobGuid ## CONSUMES + gTianoLogoGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid + +[Depex] + gEdkiiVTdInfoPpiGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..b985d23f80 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,51 @@ +### @file +# Platform Hook Library instance for System 76 GalagoPro3 board. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BasePlatformHookLib + FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PlatformHookLib +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + MmPciLib + PciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf new file mode 100644 index 0000000000..c527f3fc0e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf @@ -0,0 +1,47 @@ +### @file +# System 76 GalagoPro3 board DXE ACPI table functionality. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeBoardAcpiTableLib + FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiTableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable + gMinPlatformPkgTokenSpaceGuid.PcdPciExpNative + gMinPlatformPkgTokenSpaceGuid.PcdNativeAspmEnable + gMinPlatformPkgTokenSpaceGuid.PcdLowPowerS0Idle + gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeGalagoPro3AcpiTableLib.c + DxeBoardAcpiTableLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..fba5053d47 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf @@ -0,0 +1,48 @@ +### @file +# System 76 GalagoPro3 board multi-board DXE ACPI table support functionality. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeGalagoPro3MultiBoardAcpiTableLib + FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL + CONSTRUCTOR = DxeGalagoPro3MultiBoardAcpiSupportLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable + gBoardModuleTokenSpaceGuid.PcdPciExpNative + gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable + gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle + gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeGalagoPro3AcpiTableLib.c + DxeMultiBoardAcpiSupportLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..36c4219bf8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,47 @@ +### @file +# System 76 GalagoPro3 board SMM ACPI table enable/disable functionality. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmBoardAcpiEnableLib + FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmGalagoPro3AcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..ea15c7ffc2 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,48 @@ +### @file +# SMM multi-board ACPI support functionality. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmGalagoPro3MultiBoardAcpiSupportLib + FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL + CONSTRUCTOR = SmmGalagoPro3MultiBoardAcpiSupportLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmGalagoPro3AcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmMultiBoardAcpiSupportLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..8a57f1f6d0 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,53 @@ +## @file +# Component information file for GalagoPro3InitLib in PEI post memory phase. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardPostMemInitLib + FILE_GUID = 7fcc3900-d38d-419f-826b-72481e8b5509 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiGalagoPro3InitPostMemLib.c + GalagoPro3GpioTable.c + GalagoPro3HdaVerbTables.c + PeiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..53e70310e4 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,131 @@ +## @file +# Component information file for PEI GalagoPro3 Board Init Pre-Mem Library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardInitPreMemLib + FILE_GUID = ec3675bc-1470-417d-826e-37378140213d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiGalagoPro3Detect.c + PeiGalagoPro3InitPreMemLib.c + GalagoPro3HsioPtssTables.c + PeiBoardInitPreMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # CA Vref Configuration + + # Root Port Clock Info + gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..19e8e0144c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,55 @@ +## @file +# Component information file for GalagoPro3InitLib in PEI post memory phase. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiGalagoPro3MultiBoardInitLib + FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiGalagoPro3MultiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + SiliconInitLib + MultiBoardInitSupportLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiGalagoPro3InitPostMemLib.c + GalagoPro3GpioTable.c + GalagoPro3HdaVerbTables.c + PeiMultiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..cba590b3e3 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,130 @@ +## @file +# Component information file for PEI GalagoPro3 Board Init Pre-Mem Library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiGalagoPro3MultiBoardInitPreMemLib + FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiGalagoPro3MultiBoardInitPreMemLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + SiliconInitLib + MultiBoardInitSupportLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiGalagoPro3InitPreMemLib.c + GalagoPro3HsioPtssTables.c + PeiMultiBoardInitPreMemLib.c + PeiGalagoPro3Detect.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # CA Vref Configuration + + # Root Port Clock Info + gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo + gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..c9b73fc2bb --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,49 @@ +## @file +# Component information file for DXE silicon policy update library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSiliconUpdateLib + FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + DxeSiliconPolicyUpdateLib.c + DxeGopPolicyInit.c + DxeSaPolicyUpdate.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gSaPolicyProtocolGuid ## CONSUMES + gDxeSiPolicyProtocolGuid ## PRODUCES + gGopPolicyProtocolGuid ## PRODUCES + +[Guids] + gMiscDxeConfigGuid + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h new file mode 100644 index 0000000000..9f6b236e42 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,28 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h new file mode 100644 index 0000000000..c006dbcd68 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include + +#include +#include +#include + +extern EFI_GUID gTianoLogoGuid; + +#endif + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitLib.h b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitLib.h new file mode 100644 index 0000000000..81d99f7295 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitLib.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ +#define _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern const UINT8 mDqByteMapSklRvp3[2][6][2]; +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; +extern const UINT8 mSkylakeRvp3Spd110[]; +extern const UINT16 mSkylakeRvp3Spd110Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_GalagoPro3[]; +extern UINT16 PchLpHsioPtss_Bx_GALAGO_PRO_3_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_GalagoPro3[]; +extern UINT16 PchLpHsioPtss_Cx_GALAGO_PRO_3_Size; + +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3; +extern GPIO_INIT_CONFIG mGpioTableGalagoPro3UcmcDevice[]; +extern UINT16 mGpioTableGalagoPro3UcmcDeviceSize; + +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; +extern UINT16 mGpioTableIoExpanderSize; +extern GPIO_INIT_CONFIG mGpioTableGalagoPro3Touchpanel; +extern GPIO_INIT_CONFIG mGpioTableGalagoPro3[]; +extern UINT16 mGpioTableGalagoPro3Size; + +#endif // _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h new file mode 100644 index 0000000000..f4ab1a5bca --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h @@ -0,0 +1,39 @@ +/** @file +Header file for the GopPolicyInitDxe Driver. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _GOP_POLICY_INIT_DXE_H_ +#define _GOP_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +GopPolicyInitDxe( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h new file mode 100644 index 0000000000..bb4b4369ad --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h @@ -0,0 +1,64 @@ +/** @file + Header file for the SaPolicyInitDxe Driver. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SA_POLICY_INIT_DXE_H_ +#define _SA_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include + +#include + + +/** + SA DXE Policy Driver Entry Point \n + - Introduction \n + System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. + Platform policy Protocol is initialized with default settings in this funciton. + This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization required. + + - @result + SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c new file mode 100644 index 0000000000..0fedd81cd0 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c @@ -0,0 +1,103 @@ +/** @file + This library implements constructor function to register notify call back + when policy PPI installed. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include + +/** + Callback function to update policy when policy PPI installed. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor The notification structure this PEIM registered on install. + @param[in] Ppi The memory discovered PPI. Not used. + + @retval EFI_SUCCESS Succeeds. + @retval Others Error code returned by sub-functions. +**/ +EFI_STATUS +EFIAPI +SiPreMemPolicyPpiNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + DEBUG ((DEBUG_INFO, "SiPreMemPolicyPpiNotify() Start\n")); + + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + if (SiPreMemPolicyPpi != NULL) { + // + // Get requisite IP Config Blocks which needs to be used here + // + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update SpdAddressTable policy when it is installed. + // + if (MiscPeiPreMemConfig != NULL) { + MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[0] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[0])); + MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[1] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[1])); + MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[2] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[2])); + MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[3] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[3])); + } + } + return Status; +} + +static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyPpiNotifyList[] = { + { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gSiPreMemPolicyPpiGuid, + SiPreMemPolicyPpiNotify + } +}; + +/** + The library constructuor. + The function register a policy install notify callback. + + @param[in] ImageHandle The firmware allocated handle for the UEFI image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for now. + It will ASSERT on error for debug version. +**/ +EFI_STATUS +EFIAPI +PeiPreMemSiliconPolicyNotifyLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + // + // Register call back after PPI produced + // + Status = PeiServicesNotifyPpi (mSiPreMemPolicyPpiNotifyList); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c new file mode 100644 index 0000000000..7898dc3592 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c @@ -0,0 +1,115 @@ +/** @file + Intel PCH PEI Policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c new file mode 100644 index 0000000000..9d6c0176f6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,87 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN VariableSize; + VOID *MemorySavedData; + UINT8 MorControl; + VOID *MorControlPtr; + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // + VariableSize = 0; + MemorySavedData = NULL; + Status = PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData; + + if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) { + // + // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]), + // after memory Data is saved to NVRAM. + // + PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB); + } + + // + // MOR + // + MorControl = 0; + MorControlPtr = &MorControl; + VariableSize = sizeof (MorControl); + Status = PeiGetVariable ( + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + &MorControlPtr, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c new file mode 100644 index 0000000000..c665f7888d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,186 @@ +/** @file + Provides FSP policy update functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +VOID +InternalPrintVariableData ( + IN UINT8 *Data8, + IN UINTN DataSize + ) +{ + UINTN Index; + + for (Index = 0; Index < DataSize; Index++) { + if (Index % 0x10 == 0) { + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); + } + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + + FspmUpdDataPtr = FspmUpd; + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); + + return FspmUpd; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + + FspsUpdDataPtr = FspsUpd; + PeiFspSaPolicyUpdate (FspsUpdDataPtr); + PeiFspPchPolicyUpdate (FspsUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); + + return FspsUpd; +} + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c new file mode 100644 index 0000000000..9cd2bc4d17 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,155 @@ +/** @file + Intel PCH PEI Policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; + +/** + Add verb table helper function. + This function calculates verbtable number and shows verb table information. + + @param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table + @param[in,out] VerbTableArray Pointer to array of VerbTable + @param[in] VerbTable VerbTable which is going to add into array +**/ +STATIC +VOID +InternalAddVerbTable ( + IN OUT UINT8 *VerbTableEntryNum, + IN OUT UINT32 *VerbTableArray, + IN HDAUDIO_VERB_TABLE *VerbTable + ) +{ + if (VerbTable == NULL) { + DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n")); + return; + } + + VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable; + *VerbTableEntryNum += 1; + + DEBUG ((DEBUG_INFO, + "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n", + VerbTable->Header.VendorId, + VerbTable->Header.DeviceId, + VerbTable->Header.DataDwords) + ); +} + +enum HDAUDIO_CODEC_SELECT { + PchHdaCodecPlatformOnboard = 0, + PchHdaCodecExternalKit = 1 +}; + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HDAudie config block + @param[in] CodecType Platform codec type indicator + @param[in] AudioConnectorType Platform audio connector type +**/ +STATIC +VOID +InternalAddPlatformVerbTables ( + IN OUT FSPS_UPD *FspsUpd, + IN UINT8 CodecType, + IN UINT8 AudioConnectorType + ) +{ + UINT8 VerbTableEntryNum; + UINT32 VerbTableArray[32]; + UINT32 *VerbTablePtr; + + VerbTableEntryNum = 0; + + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable)); + + if (CodecType == PchHdaCodecPlatformOnboard) { + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); + if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) { + if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); + } else { //Stacked Jack Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n")); + } + } else { + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + } + } else { + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); + } + + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum; + + VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum); + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum); + FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + + FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID; + + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable; + + InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector)); + +DEBUG_CODE_BEGIN(); +if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) && + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) { + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart; + } +DEBUG_CODE_END(); + + FspsUpd->FspsConfig.PchSirqMode = PchContinuousMode; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 0000000000..5a62f9bb72 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,248 @@ +/** @file + Intel PCH PEI Policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +InstallPlatformHsioPtssTable ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + EFI_STATUS Status; + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); + MaxPciePorts = GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + + //Populate PCIe topology based on lane configuration + for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); + } + for (Index = 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); + } + + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + PtssTables = SpecificPtssTables; + TableSize = SpecificTableSize; + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 1b: PCIe + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 2: BoardId is unknown, Topology is known/unknown + if (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + InstallPlatformHsioPtssTable (FspmUpd); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c new file mode 100644 index 0000000000..133b8c963f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,84 @@ +/** @file + Intel System Agent policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + FspsUpd->FspsConfig.GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer; + FspsUpd->FspsConfig.LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + FspsUpd->FspsConfig.LogoPtr = 0; + FspsUpd->FspsConfig.LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 0000000000..93d79c2313 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,75 @@ +/** @file + Intel System Agent policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + VOID *Buffer; + +// +// Update UPD:DqPinsInterleaved +// + FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved); + + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig); + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..5c5d6a25b4 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -0,0 +1,662 @@ +/** @file + Platform Hook Library + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define COM1_BASE 0x3f8 +#define COM2_BASE 0x2f8 + +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690 + +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20 + +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F + +typedef struct { + UINT8 Register; + UINT8 Value; +} EFI_SIO_TABLE; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = { + {0x002, 0x88}, // Power On UARTs + {0x024, COM1_BASE >> 2}, + {0x025, COM2_BASE >> 2}, + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4, + {0x029, 0x080}, // SIRQ_CLKRUN_EN + {0x02A, 0x000}, + {0x02B, 0x0DE}, + {0x00A, 0x040}, + {0x00C, 0x00E}, + {0x02c, 0x002}, + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, + {0x03a, 0x00A}, // LPC Docking Enabling + {0x031, 0x01f}, + {0x032, 0x000}, + {0x033, 0x004}, + {0x038, 0x0FB}, + {0x035, 0x0FE}, + {0x036, 0x000}, + {0x037, 0x0FF}, + {0x039, 0x000}, + {0x034, 0x001}, + {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, // Relocate configuration ports base address + {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} // to ensure SIO config address can be accessed in OS +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = { + {0x002, 0x88}, // Power On UARTs + {0x007, 0x00}, + {0x024, COM1_BASE >> 2}, + {0x025, COM2_BASE >> 2}, + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4, + {0x029, 0x080}, // SIRQ_CLKRUN_EN + {0x02A, 0x000}, + {0x02B, 0x0DE}, + {0x00A, 0x040}, + {0x00C, 0x00E}, + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, + {0x03a, 0x00A}, // LPC Docking Enabling + {0x031, 0x01f}, + {0x032, 0x000}, + {0x033, 0x004}, + {0x038, 0x0FB}, + {0x035, 0x0FE}, + {0x036, 0x000}, + {0x037, 0x0FE}, + {0x039, 0x000}, + {0x034, 0x001} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = { + {0x29, 0x0A0}, // Enable super I/O clock and set to 48MHz + {0x22, 0x003}, // + {0x07, 0x003}, // Select UART0 device + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x004}, // Set to IRQ4 + {0x30, 0x001}, // Enable it with Activation bit + {0x07, 0x002}, // Select UART1 device + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x003}, // Set to IRQ3 + {0x30, 0x001}, // Enable it with Activation bit + {0x07, 0x007}, // Select GPIO device + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address MSB + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address LSB + {0x30, 0x001}, // Enable it with Activation bit + {0x21, 0x001}, // Global Device Enable + {0x26, 0x000} // Fast Enable UART 0 & 1 as their enable & activation bit +}; + +// +// National PC8374L +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = { + {0x007, 0x03}, // Select Com1 + {0x061, 0xF8}, // 0x3F8 + {0x060, 0x03}, // 0x3F8 + {0x070, 0x04}, // IRQ4 + {0x030, 0x01} // Active +}; + +// +// IT8628 +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = { + {0x023, 0x09}, // Clock Selection register + {0x007, 0x01}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select + {0x030, 0x01}, // Serial Port 1 Activate + {0x007, 0x02}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select + {0x030, 0x01} // Serial Port 2 Activate +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = { + {0x007, 0x03}, // Parallel Port Logical Device Number select + {0x030, 0x00}, // Parallel port Activate + {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register + {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register + {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register + {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register + {0x0F0, 0x03} // Special Configuration register +}; + + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = { + {0x07, 0x03}, // Select UART0 device + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x04}, // Set to IRQ4 + {0x30, 0x01} // Enable it with Activation bit +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = { + {0x07, 0x02}, // Set logical device SP Serial port Com0 + {0x61, 0xF8}, // Write Base Address LSB register 0x3F8 + {0x60, 0x03}, // Write Base Address MSB register 0x3F8 + {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard + {0x30, 0x01} // Enable serial port with Activation bit +}; + +/** + Detect if a National 393 SIO is docked. If yes, enable the docked SIO + and its serial port, and disable the onboard serial port. + + @retval EFI_SUCCESS Operations performed successfully. +**/ +STATIC +VOID +CheckNationalSio ( + VOID + ) +{ + UINT8 Data8; + + // + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). + // We use (0x2e, 0x2f) which is determined by BADD default strapping + // + + // + // Read the Pc87393 signature + // + IoWrite8 (0x2e, 0x20); + Data8 = IoRead8 (0x2f); + + if (Data8 == 0xea) { + // + // Signature matches - National PC87393 SIO is docked + // + + // + // Enlarge the LPC decode scope to accommodate the Docking LPC Switch + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at + // SIO_BASE_ADDRESS + 0x10) + // + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20); + + // + // Enable port switch + // + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); + + // + // Turn on docking power + // + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); + + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); + + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); + + // + // Enable port switch + // + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); + + // + // GPIO setting + // + IoWrite8 (0x2e, 0x24); + IoWrite8 (0x2f, 0x29); + + // + // Enable chip clock + // + IoWrite8 (0x2e, 0x29); + IoWrite8 (0x2f, 0x1e); + + + // + // Enable serial port + // + + // + // Select com1 + // + IoWrite8 (0x2e, 0x7); + IoWrite8 (0x2f, 0x3); + + // + // Base address: 0x3f8 + // + IoWrite8 (0x2e, 0x60); + IoWrite8 (0x2f, 0x03); + IoWrite8 (0x2e, 0x61); + IoWrite8 (0x2f, 0xf8); + + // + // Interrupt: 4 + // + IoWrite8 (0x2e, 0x70); + IoWrite8 (0x2f, 0x04); + + // + // Enable bank selection + // + IoWrite8 (0x2e, 0xf0); + IoWrite8 (0x2f, 0x82); + + // + // Activate + // + IoWrite8 (0x2e, 0x30); + IoWrite8 (0x2f, 0x01); + + // + // Disable onboard serial port + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); + + // + // Power Down UARTs + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); + + // + // Dissable COM1 decode + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); + + // + // Disable COM2 decode + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); + + // + // Disable interrupt + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); + + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + + // + // Enable floppy + // + + // + // Select floppy + // + IoWrite8 (0x2e, 0x7); + IoWrite8 (0x2f, 0x0); + + // + // Base address: 0x3f0 + // + IoWrite8 (0x2e, 0x60); + IoWrite8 (0x2f, 0x03); + IoWrite8 (0x2e, 0x61); + IoWrite8 (0x2f, 0xf0); + + // + // Interrupt: 6 + // + IoWrite8 (0x2e, 0x70); + IoWrite8 (0x2f, 0x06); + + // + // DMA 2 + // + IoWrite8 (0x2e, 0x74); + IoWrite8 (0x2f, 0x02); + + // + // Activate + // + IoWrite8 (0x2e, 0x30); + IoWrite8 (0x2f, 0x01); + + } else { + + // + // No National pc87393 SIO is docked, turn off dock power and + // disable port switch + // + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); + // IoWrite8 (0x690, 0); + + // + // If no National pc87393, just return + // + return; + } +} + + +/** +Check whether the IT8628 SIO present on LPC. If yes, enable its serial +ports, parallel port, and port 80. + +@retval EFI_SUCCESS Operations performed successfully. +**/ +STATIC +VOID +It8628SioSerialPortInit ( + VOID + ) +{ + UINT8 ChipId0 = 0; + UINT8 ChipId1 = 0; + UINT16 LpcIoDecondeRangeSet = 0; + UINT16 LpcIoDecoodeSet = 0; + UINT8 Index; + UINTN LpcBaseAddr; + + + // + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh. + // + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD); + LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE); + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8))); + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE))); + + // + // Enter MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); + + // + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); + ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); + ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + // + // Enable Serial Port 1, Port 2 + // + if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) { + for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value); + } + } + + // + // Exit MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02); + + return; +} + + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + UINT16 ConfigPort; + UINT16 IndexPort; + UINT16 DataPort; + UINT16 DeviceId; + UINT8 Index; + UINT16 AcpiBase; + + // + // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit + // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use. + // + IndexPort = 0; + DataPort = 0; + Index = 0; + AcpiBase = 0; + PchAcpiBaseGet (&AcpiBase); + if (AcpiBase == 0) { + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); + } + + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + // Configure Sio IT8628 + It8628SioSerialPortInit (); + + DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID); + if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) { + // + // if no EC, it is SV Bidwell Bar board + // + if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) { + // + // Super I/O initialization for SMSC SI1007 + // + ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort); + DataPort = PcdGet16 (PcdLpcSioDataDefaultPort); + IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort); + + // + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; + // + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10); + + // + // Program and Enable Default Super IO Configuration Port Addresses and range + // + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10); + + // + // Enter Config Mode + // + IoWrite8 (ConfigPort, 0x55); + + // + // Check for SMSC SIO1007 + // + IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is 0x0D + if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is 0x20 + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTable[Index].Register); + IoWrite8 (DataPort, mSioTable[Index].Value); + } + + // + // Exit Config Mode + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + + // + // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH + // + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f); + } + + // + // Check if a National Pc87393 SIO is docked + // + CheckNationalSio (); + + // + // Super I/O initialization for SMSC SIO1000 + // + ConfigPort = PcdGet16 (PcdLpcSioIndexPort); + IndexPort = PcdGet16 (PcdLpcSioIndexPort); + DataPort = PcdGet16 (PcdLpcSioDataPort); + + // + // Enter Config Mode + // + IoWrite8 (ConfigPort, 0x55); + + // + // Check for SMSC SIO1000 + // + if (IoRead8 (ConfigPort) != 0xFF) { + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register); + IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value); + } + + // + // Exit Config Mode + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + } + + // + // Super I/O initialization for Winbond WPCN381U + // + IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2; + DataPort = LPC_SIO_DATA_DEFAULT_PORT_2; + + // + // Check for Winbond WPCN381U + // + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID is 0xF4 + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register); + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value); + } + } + } //EC is not exist, skip mobile board detection for SV board + + // + //add for SV Bidwell Bar board + // + if (IoRead8 (COM1_BASE) == 0xFF) { + // + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC) + // Looking for LDC2 card first + // + IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55); + if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) { + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; + } else { + IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; + } + + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1 + for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register); + IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value); + } + } + }// end of Bidwell Bar SIO initialization + } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) { + // + // If we are in debug mode, we will allow serial status codes + // + + // + // National PC8374 SIO & Winbond WPCD374 (LDC2) + // + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + + IoWrite8 (IndexPort, 0x55); + if (IoRead8 (IndexPort) == 0x55) { + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; + } else { + IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; + } + + // + // Configure SIO + // + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1 + for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mDesktopSioTable[Index].Register); + //PrePpiStall (200); + IoWrite8 (DataPort, mDesktopSioTable[Index].Value); + //PrePpiStall (200); + } + return RETURN_SUCCESS; + } + // + // Configure Pilot3 SIO + // + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode. + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot3 SIO Device ID register is 0x20. + if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { // Pilot3 SIO Device ID register is 0x03. + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register); + IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value); + } + } + IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode. + } + + + return RETURN_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c new file mode 100644 index 0000000000..42c2982a82 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c @@ -0,0 +1,36 @@ +/** @file + DXE board-specific ACPI functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + GalagoPro3BoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeGalagoPro3AcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeGalagoPro3AcpiTableLib.c new file mode 100644 index 0000000000..76a8da9cda --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeGalagoPro3AcpiTableLib.c @@ -0,0 +1,74 @@ +/** @file + System 76 GalagoPro3 board DXE ACPI table functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea; + +VOID +GalagoPro3UpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + // + // Enable PowerState + // + mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c + + mGlobalNvsArea.Area->NativePCIESupport = PcdGet8 (PcdPciExpNative); + + // + // Enable APIC + // + mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE; + + // + // Low Power S0 Idle - Enabled/Disabled + // + mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle); + + mGlobalNvsArea.Area->Ps2MouseEnable = PcdGet8 (PcdPs2KbMsEnable); + mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8 (PcdPs2KbMsEnable); +} + +EFI_STATUS +EFIAPI +GalagoPro3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { + GalagoPro3UpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..639524c7d0 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c @@ -0,0 +1,43 @@ +/** @file + DXE multi-board ACPI table support functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +BOARD_ACPI_TABLE_FUNC mGalagoPro3BoardAcpiTableFunc = { + GalagoPro3BoardUpdateAcpiTable +}; + +EFI_STATUS +EFIAPI +DxeGalagoPro3MultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () == BoardIdGalagoPro3) { + return RegisterBoardAcpiTableFunc (&mGalagoPro3BoardAcpiTableFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..1037989b9a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,62 @@ +/** @file + System 76 GalagoPro3 board SMM ACPI table enable/disable functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return GalagoPro3BoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return GalagoPro3BoardDisableAcpi (DisableSci); +} + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmGalagoPro3AcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmGalagoPro3AcpiEnableLib.c new file mode 100644 index 0000000000..ee897e422a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmGalagoPro3AcpiEnableLib.c @@ -0,0 +1,39 @@ +/** @file + Platform Hook Library instances + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +GalagoPro3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..c4c1e116c8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,81 @@ +/** @file + SMM multi-board ACPI support functionality. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +GalagoPro3MultiBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return GalagoPro3BoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +GalagoPro3MultiBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return GalagoPro3BoardDisableAcpi (DisableSci); +} + +BOARD_ACPI_ENABLE_FUNC mGalagoPro3BoardAcpiEnableFunc = { + GalagoPro3MultiBoardEnableAcpi, + GalagoPro3MultiBoardDisableAcpi, +}; + +EFI_STATUS +EFIAPI +SmmGalagoPro3MultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () == BoardIdGalagoPro3) { + return RegisterBoardAcpiEnableFunc (&mGalagoPro3BoardAcpiEnableFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..1baa8daa70 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,168 @@ +/** @file + SMM ACPI enable library. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 OutputValue; + UINT32 SmiEn; + UINT32 SmiSts; + UINT32 ULKMC; + UINTN LpcBaseAddress; + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + LpcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + // + // Get the ACPI Base Address + // + PchAcpiBaseGet (&AcpiBaseAddr); + + // + // BIOS must also ensure that CF9GR is cleared and locked before handing control to the + // OS in order to prevent the host from issuing global resets and resetting ME + // + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset + // MmioWrite32 ( + // PmcBaseAddress + R_PCH_PMC_ETR3), + // PmInit); + + // + // Clear Port 80h + // + IoWrite8 (0x80, 0); + + // + // Disable SW SMI Timer and clean the status + // + SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN); + SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB); + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn); + + SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS); + SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB; + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts); + + // + // Disable port 60/64 SMI trap if they are enabled + // + ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN); + MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC); + + // + // Disable PM sources except power button + // + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN); + + // + // Clear PM status except Power Button status for RapidStart Resume + // + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD); + IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0); + + // + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) + // + OutputValue = IoRead32 (AcpiBaseAddr + 0x38); + OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition)); + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); + + + // + // Enable SCI + // + if (EnableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + // + // Get the ACPI Base Address + // + PchAcpiBaseGet (&AcpiBaseAddr); + + // + // Disable SCI + // + if (DisableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3GpioTable.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3GpioTable.c new file mode 100644 index 0000000000..f6009d0b28 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3GpioTable.c @@ -0,0 +1,370 @@ +/** @file + GPIO definition table for GalagoPro3 + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GALAGO_PRO_3_GPIO_TABLE_H_ +#define _GALAGO_PRO_3_GPIO_TABLE_H_ + +#include +#include +#include +#include +#include + + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +GPIO_INIT_CONFIG mGpioTableGalagoPro3[] = +{ + {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //RCINB_TIME_SYNC_1 + {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //LAD_0_ESPI_IO_0 + {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LAD_1_ESPI_IO_1 + {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //LAD_2_ESPI_IO_2 + {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LAD_3_ESPI_IO_3 + {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LFRAMEB_ESPI_CSB + {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SERIRQ + {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PIRQAB_GSPI0_CS1B + {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CLKRUNB + {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //CLKOUT_LPC_0_ESPI_CLK + {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //CLKOUT_LPC_1 + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //PMEB_GSPI1_CS1B + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //BM_BUSYB_ISH_GP_6 + {GPIO_SKL_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SUSWARNB_SUSPWRDNACK + {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SUS_STATB_ESPI_RESETB + {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //SUSACKB + {GPIO_SKL_LP_GPP_A16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD_1P8_SEL + {GPIO_SKL_LP_GPP_A17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD_VDD1_PWR_EN_B_ISH_GP_7 + {GPIO_SKL_LP_GPP_A18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_GP_0 + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_GP_1 + {GPIO_SKL_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_GP_2 + {GPIO_SKL_LP_GPP_A21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //ISH_GP_3 + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //ISH_GP_4 + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //ISH_GP_5 + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CORE_VID_0 + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CORE_VID_1 + {GPIO_SKL_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //VRALERTB + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU_GP_2 + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU_GP_3 + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_0 + {GPIO_SKL_LP_GPP_B6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_1 + {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_2 + {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_3 + {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_4 + {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRCCLKREQB_5 + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EXT_PWR_GATEB + {GPIO_SKL_LP_GPP_B12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SLP_S0B + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PLTRSTB + {GPIO_SKL_LP_GPP_B14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //SPKR + {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI0_CS0B + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI0_CLK + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI0_MISO + {GPIO_SKL_LP_GPP_B18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //GSPI0_MOSI + {GPIO_SKL_LP_GPP_B19, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI1_CS0B + {GPIO_SKL_LP_GPP_B20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI1_CLK_NFC_CLK + {GPIO_SKL_LP_GPP_B21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSPI1_MISO_NFC_CLKREQ + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //GSPI1_MOSI + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML1ALERTB_PCHHOTB + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_0_SD3_CMD + {GPIO_SKL_LP_GPP_G1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_1_SD3_D0_SD4_RCLK_P + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_2_SD3_D1_SD4_RCLK_N + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_3_SD3_D2 + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_4_SD3_D3 + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_5_SD3_CDB + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_6_SD3_CLK + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPPC_G_7_SD3_WP + {GPIO_SKL_LP_GPP_D0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_CSB_BK_0 + {GPIO_SKL_LP_GPP_D1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_CLK_BK_1 + {GPIO_SKL_LP_GPP_D2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_MISO_IO_1_BK_2 + {GPIO_SKL_LP_GPP_D3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_MOSI_IO_0_BK_3 + {GPIO_SKL_LP_GPP_D4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IMGCLKOUT_0_BK_4 + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_I2C0_SDA + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_I2C0_SCL + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_I2C1_SDA + {GPIO_SKL_LP_GPP_D8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_I2C1_SCL + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_SPI_CSB + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_SPI_CLK + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_SPI_MISO_GP_BSSB_CLK + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_SPI_MOSI_GP_BSSB_DI + {GPIO_SKL_LP_GPP_D13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_UART0_RXD_SML0BDATA + {GPIO_SKL_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_UART0_TXD_SML0BCLK + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_UART0_RTSB_GSPI2_CS1B + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH_UART0_CTSB_SML0BALERTB + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMIC_CLK_1_SNDW3_CLK + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMIC_DATA_1_SNDW3_DATA + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMIC_CLK_0_SNDW4_CLK + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMIC_DATA_0_SNDW4_DATA + {GPIO_SKL_LP_GPP_D21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_IO_2 + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI1_IO_3 + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SSP_MCLK + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_GNSS_PA_BLANKING + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_GNSS_FTA + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_GNSS_SYSCK + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_BRI_DT_UART0_RTSB + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_BRI_RSP_UART0_RXD + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_RGI_DT_UART0_TXD + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_RGI_RSP_UART0_CTSB + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_MFUART2_RXD + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV_MFUART2_TXD + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_CMD + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA0 + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA1 + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA2 + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA3 + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA4 + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA5 + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA6 + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_DATA7 + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_RCLK + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_CLK + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMMC_RESETB + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}}, //A4WP_PRESENT + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //BATLOWB + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNative}}, //ACPRESENT + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetDefault, GpioTermNone}}, //LAN_WAKEB + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermWpu20K}}, //PWRBTNB + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_S3B + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_S4B + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_AB + {GPIO_SKL_LP_GPD7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, // + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SUSCLK + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_WLANB + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_S5B + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //LANPHYPC + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SMBCLK + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SMBDATA + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //SMBALERTB + {GPIO_SKL_LP_GPP_C3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML0CLK + {GPIO_SKL_LP_GPP_C4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML0DATA + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML0ALERTB + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML1CLK + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML1DATA + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART0_RXD + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART0_TXD + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART0_RTSB + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART0_CTSB + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART1_RXD_ISH_UART1_RXD + {GPIO_SKL_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermNone}}, //UART1_TXD_ISH_UART1_TXD + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART1_RTSB_ISH_UART1_RTSB + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART1_CTSB_ISH_UART1_CTSB + {GPIO_SKL_LP_GPP_C16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C0_SDA + {GPIO_SKL_LP_GPP_C17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C0_SCL + {GPIO_SKL_LP_GPP_C18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C1_SDA + {GPIO_SKL_LP_GPP_C19, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone}}, //I2C1_SCL + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART2_RXD + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART2_TXD + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART2_RTSB + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UART2_CTSB + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}}, //SATAXPCIE_0_SATAGP_0 + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SATAXPCIE_1_SATAGP_1 + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SATAXPCIE_2_SATAGP_2 + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutLow, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU_GP_0 + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA_DEVSLP_0 + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA_DEVSLP_1 + {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SATA_DEVSLP_2 + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU_GP_1 + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SATA_LEDB + {GPIO_SKL_LP_GPP_E9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB2_OCB_0_GP_BSSB_CLk + {GPIO_SKL_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB2_OCB_1_GP_BSSB_DI + {GPIO_SKL_LP_GPP_E11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB2_OCB_2 + {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB2_OCB_3 + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDSP_HPD_0_DISP_MISC_0 + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDSP_HPD_1_DISP_MISC_1 + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}}, //DDSP_HPD_2_DISP_MISC_2 + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}}, //DDSP_HPD_3_DISP_MISC_3 + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EDP_HPD_DISP_MISC_4 + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDPB_CTRLCLK + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDPB_CTRLDATA + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDPC_CTRLCLK + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDPC_CTRLDATA + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}}, //DDPD_CTRLCLK + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDPD_CTRLDATA + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table +}; + +UINT16 mGpioTableGalagoPro3Size = sizeof (mGpioTableGalagoPro3) / sizeof (GPIO_INIT_CONFIG) - 1; + +GPIO_INIT_CONFIG mGpioTableGalagoPro3UcmcDevice[] = +{ + { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B0 + { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B1 +}; + +UINT16 mGpioTableGalagoPro3UcmcDeviceSize = sizeof (mGpioTableGalagoPro3UcmcDevice) / sizeof (GPIO_INIT_CONFIG); + +GPIO_INIT_CONFIG mGpioTableGalagoPro3Touchpanel = + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}}; + +GPIO_INIT_CONFIG mGpioTableGalagoPro3SdhcSidebandCardDetect = + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_CDB D3 + +//IO Expander Table for SKL RVP7, RVP13 and RVP15 +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP +}; + +UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +//IO Expander Table for KBL -Refresh +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//Unused pin + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R + // We want the initial state to be high. + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N + // Turn off WWAN power and will turn it on later. + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP +}; +UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof (mGpioTableIoExpanderKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +//IO Expander Table for KBL -kc +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN + {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL + {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R +}; +UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG); +//IO Expander Table Full table for N 1XX WU +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderGalagoPro3[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD) +//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD) + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD) +//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD) + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD) + {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD) +}; + +UINT16 mGpioTableIoExpanderGalagoPro3Size = sizeof (mGpioTableIoExpanderGalagoPro3) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +#endif // _GALAGO_PRO_3_GPIO_TABLE_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HdaVerbTables.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HdaVerbTables.c new file mode 100644 index 0000000000..0a5c9b6125 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HdaVerbTables.c @@ -0,0 +1,232 @@ +/** @file + HDA Verb table for GalagoPro3 + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GALAGO_PRO_3_HDA_VERB_TABLES_H_ +#define _GALAGO_PRO_3_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC286) for RVP3 + // Revision ID = 0xff + // Codec Verb Table for SKL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0286 + // + 0x10EC, 0x0286, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.2.9 + //Realtek HD Audio Codec : ALC286 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E + //The number of verb command block : 16 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x9017011F + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x03A11040 + // NID 0x19 : 0x411111F0 + // NID 0x1A : 0x411111F0 + // NID 0x1D : 0x4066A22D + // NID 0x1E : 0x411111F0 + // NID 0x21 : 0x03211020 + + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC108E + 0x0017208E, + 0x00172110, + 0x001722EC, + 0x00172310, + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - SPEAKER-OUT (Port-D) + 0x01771C1F, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - MIC1 (Port-B) + 0x01871C40, + 0x01871D10, + 0x01871EA1, + 0x01871F03, + //Pin widget 0x19 - I2S-IN + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C2D, + 0x01D71DA2, + 0x01D71E66, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x21 - HP-OUT (Port-A) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F03, + //Widget node 0x20 : + 0x02050071, + 0x02040014, + 0x02050010, + 0x02040C22, + //Widget node 0x20 - 1 : + 0x0205004F, + 0x02045029, + 0x0205004F, + 0x02045029, + //Widget node 0x20 - 2 : + 0x0205002B, + 0x02040DD0, + 0x0205002D, + 0x02047020, + //Widget node 0x20 - 3 : + 0x0205000E, + 0x02046C80, + 0x01771F90, + 0x01771F90, + //TI AMP settings : + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040000, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040011, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x0204000D, + 0x02050025, + 0x02040010, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040025, + 0x02050025, + 0x02040008, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040003, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010 +); + +#endif // _GALAGO_PRO_3_HDA_VERB_TABLES_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HsioPtssTables.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HsioPtssTables.c new file mode 100644 index 0000000000..a52a0fec37 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/GalagoPro3HsioPtssTables.c @@ -0,0 +1,105 @@ +/** @file + GalagoPro3 HSIO PTSS H File + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef GalagoPro3_HSIO_PTSS_H_ +#define GalagoPro3_HSIO_PTSS_H_ + +#include + +#ifndef HSIO_PTSS_TABLE_SIZE +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES) +#endif + +//BoardId GalagoPro3 +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_GalagoPro3[] = { + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoM2}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchSataTopoM2}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown} +}; + +UINT16 PchLpHsioPtss_Cx_GALAGO_PRO_3_Size = sizeof(PchLpHsioPtss_Cx_GalagoPro3) / sizeof(HSIO_PTSS_TABLES); + +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_GalagoPro3[] = { + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, +}; + +UINT16 PchLpHsioPtss_Bx_GALAGO_PRO_3_Size = sizeof(PchLpHsioPtss_Bx_GalagoPro3) / sizeof(HSIO_PTSS_TABLES); + +#endif // GalagoPro3_HSIO_PTSS_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..6ea997fc74 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,39 @@ +/** @file + Board post-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + GalagoPro3BoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..148205401e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,105 @@ +/** @file + Board post-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +GalagoPro3BoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + GalagoPro3BoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + GalagoPro3BoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return GalagoPro3BoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + GalagoPro3BoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3Detect.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3Detect.c new file mode 100644 index 0000000000..b6bd772f46 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3Detect.c @@ -0,0 +1,66 @@ +/** @file + System 76 GalagoPro3 board detection. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiGalagoPro3InitLib.h" + +#include +#include + +BOOLEAN +IsGalagoPro3 ( + VOID + ) +{ + // TBD: Do detection - BoardIdGalagoPro3 v.s. BoardIdGalagoPro3 + return TRUE; +} + +EFI_STATUS +EFIAPI +GalagoPro3BoardDetect ( + VOID + ) +{ + if (LibPcdGetSku () != 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "GalagoPro3DetectionCallback\n")); + + if (IsGalagoPro3 ()) { + LibPcdSetSku (BoardIdGalagoPro3); + + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + ASSERT (LibPcdGetSku() == BoardIdGalagoPro3); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPostMemLib.c new file mode 100644 index 0000000000..f1a1ef4ced --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPostMemLib.c @@ -0,0 +1,209 @@ +/** @file + System 76 GalagoPro3 board post-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiGalagoPro3InitLib.h" + +/** + N 1XX WU board configuration init function for PEI post memory phase. + + PEI_BOARD_CONFIG_PCD_INIT + + @param Content pointer to the buffer contain init information for board init. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +GalagoPro3Init ( + VOID + ) +{ + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3); + + // + // Assign the GPIO table with pin configs to be used for UCMC + // + PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableGalagoPro3UcmcDevice); + PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableGalagoPro3UcmcDeviceSize); + + return EFI_SUCCESS; +} + +#define EXPANDERS 2 // defines expander's quantity + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status = GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +VOID +SetBit ( + IN OUT UINT32 *Value, + IN UINT32 BitNumber, + IN BOOLEAN NewBitValue + ) +{ + if (NewBitValue) { + *Value |= 1 << BitNumber; + } else { + *Value &= ~(1 << BitNumber); + } +} + +/** + Configures IO Expander GPIO device + + @param[in] IOExpGpioDefinition Point to IO Expander Gpio table + @param[in] IOExpGpioTableCount Number of Gpio table entries + +**/ +void +ConfigureIoExpanderGpio ( + IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition, + IN UINT16 IoExpGpioTableCount + ) +{ + UINT8 Index; + UINT32 Direction[EXPANDERS] = {0x00FFFFFF, 0x00FFFFFF}; + UINT32 Level[EXPANDERS] = {0}; + UINT32 Polarity[EXPANDERS] = {0}; + + // IoExpander {TCA6424A} + DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n")); + for (Index = 0; Index < IoExpGpioTableCount; Index++) { //Program IO Expander as per the table defined in PeiPlatformHooklib.c + SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection); + SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel); + SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion); + } + for (Index = 0; Index < EXPANDERS; Index++) { + GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Index]); + } + DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n")); + return; +} + +/** + Configure GPIO behind IoExpander. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor + @param[in] Interface + + @retval EFI_SUCCESS Operation success. +**/ +VOID +ExpanderGpioInit ( + VOID + ) +{ + ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize); +} + +/** + Configure single GPIO pad for touchpanel interrupt + +**/ +VOID +TouchpanelGpioInit ( + VOID + ) +{ + GPIO_INIT_CONFIG* TouchpanelPad; + GPIO_PAD_OWN PadOwnVal; + + PadOwnVal = 0; + TouchpanelPad = &mGpioTableGalagoPro3Touchpanel; + + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); + if (PadOwnVal == GpioPadOwnHost) { + GpioConfigurePads (1, TouchpanelPad); + } +} + + +/** + Configure GPIO + +**/ +VOID +GpioInit ( + VOID + ) +{ + ConfigureGpio (mGpioTableGalagoPro3, mGpioTableGalagoPro3Size); + + TouchpanelGpioInit(); + + return; +} + + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeSiliconInit ( + VOID + ) +{ + GalagoPro3Init (); + + GpioInit (); + ExpanderGpioInit (); + + /// + /// Do Late PCH init + /// + LateSiliconInit (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c new file mode 100644 index 0000000000..ca32ab2514 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c @@ -0,0 +1,236 @@ +/** @file + System 76 GalagoPro3 board pre-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiGalagoPro3InitLib.h" + +#include +#include + +// +// Reference RCOMP resistors on motherboard - for SKL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 }; +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 }; + +// +// Reference RCOMP resistors on motherboard - for SKL RVP2 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX_RCOMP] = { 121, 81, 100 }; +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP2 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20, 26 }; + +/** + N 1XX WU board configuration init function for PEI pre-memory phase. + + PEI_BOARD_CONFIG_PCD_INIT + + @param Content pointer to the buffer contain init information for board init. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +GalagoPro3InitPreMem ( + VOID + ) +{ + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 8); + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + // + // HSIO PTSS Table + // + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_GalagoPro3); + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_GALAGO_PRO_3_Size); + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_GalagoPro3); + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_GALAGO_PRO_3_Size); + + // + // DRAM related definition + // + PcdSet8S (PcdSaMiscUserBd, 5); + + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); + + + PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE); + PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2); + PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2); + PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards + + PcdSetBoolS (PcdIoExpanderPresent, TRUE); + + return EFI_SUCCESS; +} + +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status = GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO Before Memory is not ready. + +**/ +VOID +GpioInitPreMem ( + VOID + ) +{ + // ConfigureGpio (); +} + +/** + Configure Super IO + +**/ +VOID +SioInit ( + VOID + ) +{ + // + // Program and Enable Default Super IO Configuration Port Addresses and range + // + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10); + + // + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; + // + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); + + return; +} + +/** + Configues the IC2 Controller on which GPIO Expander Communicates. + This Function is to enable the I2CGPIOExapanderLib to programm the Gpios + Complete intilization will be done in later Stage + +**/ +VOID +EFIAPI +I2CGpioExpanderInitPreMem( + VOID + ) +{ + ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden); + SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V); +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeMemoryInit ( + VOID + ) +{ + GalagoPro3InitPreMem (); + + // + // Configures the I2CGpioExpander + // + if (PcdGetBool (PcdIoExpanderPresent)) { + I2CGpioExpanderInitPreMem(); + } + + GpioInitPreMem (); + SioInit (); + + /// + /// Do basic PCH init + /// + SiliconInit (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +GalagoPro3BoardDebugInit ( + VOID + ) +{ + /// + /// Do Early PCH init + /// + EarlySiliconInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +GalagoPro3BoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..5ddf04dece --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file + Multi-board post-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeSiliconInit ( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mGalagoPro3BoardInitFunc = { + GalagoPro3BoardInitBeforeSiliconInit, + NULL, // BoardInitAfterSiliconInit +}; + +EFI_STATUS +EFIAPI +PeiGalagoPro3MultiBoardInitLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () == BoardIdGalagoPro3) { + return RegisterBoardPostMemInit (&mGalagoPro3BoardInitFunc); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..12e03b37cb --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,82 @@ +/** @file + Board pre-memory initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +GalagoPro3BoardDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +GalagoPro3MultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +GalagoPro3BoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +GalagoPro3BoardInitBeforeMemoryInit ( + VOID + ); + +BOARD_DETECT_FUNC mGalagoPro3BoardDetectFunc = { + GalagoPro3MultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mGalagoPro3BoardPreMemInitFunc = { + GalagoPro3BoardDebugInit, + GalagoPro3BoardBootModeDetect, + GalagoPro3BoardInitBeforeMemoryInit, + NULL, // BoardInitAfterMemoryInit + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +GalagoPro3MultiBoardDetect ( + VOID + ) +{ + GalagoPro3BoardDetect (); + if (LibPcdGetSku () == BoardIdGalagoPro3) { + RegisterBoardPreMemInit (&mGalagoPro3BoardPreMemInitFunc); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiGalagoPro3MultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mGalagoPro3BoardDetectFunc); +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c new file mode 100644 index 0000000000..99c7d42c4e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c @@ -0,0 +1,175 @@ +/** @file + DXE GOP policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeGopPolicyInit.h" +#include + +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0; + +// +// Function implementations +// + +/** + + @param[out] CurrentLidStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ) +{ + return EFI_UNSUPPORTED; +} +/** + + @param[out] CurrentDockStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + + @param[out] VbtAddress + @param[out] VbtSize + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND +**/ +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Index; + UINT32 AuthenticationStatus; + UINT8 *Buffer; + UINTN VbtBufferSize; + + + Status = EFI_NOT_FOUND; + if ( mVbtAddress == 0) { + Fv = NULL; + + Buffer = 0; + FvHandles = NULL; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < FvProtocolCount; Index++) { + Status = gBS->HandleProtocol ( + FvHandles[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + VbtBufferSize = 0; + Status = Fv->ReadSection ( + Fv, + PcdGetPtr (PcdGraphicsVbtGuid), + EFI_SECTION_RAW, + 0, + (VOID **) &Buffer, + &VbtBufferSize, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize = (UINT32)VbtBufferSize; + mVbtAddress = *VbtAddress; + mVbtSize = *VbtSize; + Status = EFI_SUCCESS; + break; + } + } + } else { + Status = EFI_NOT_FOUND; + } + + if (FvHandles != NULL) { + FreePool (FvHandles); + FvHandles = NULL; + } + } else { + *VbtAddress = mVbtAddress; + *VbtSize = mVbtSize; + Status = EFI_SUCCESS; + } + + return Status; +} + + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ + +EFI_STATUS +EFIAPI +GopPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + // + // Initialize the EFI Driver Library + // + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); + + mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03; + mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; + mGOPPolicy.GetVbtData = GetVbtData; + mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gGopPolicyProtocolGuid, + &mGOPPolicy, + NULL + ); + + return Status; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c new file mode 100644 index 0000000000..d140237576 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c @@ -0,0 +1,65 @@ +/** @file + This file is the library for SA DXE Policy initialization. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeSaPolicyInit.h" + +#define SA_VTD_RMRR_USB_LENGTH 0x20000 + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress; +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize; + +/** + Update RMRR Base and Limit Address for USB. + +**/ +VOID +UpdateRmrrUsbAddress ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + MISC_DXE_CONFIG *MiscDxeConfig; + + Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + if (1) { + mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); + mAddress = SIZE_4GB; + + Status = (gBS->AllocatePages) ( + AllocateMaxAddress, + EfiReservedMemoryType, + mSize, + &mAddress + ); + ASSERT_EFI_ERROR (Status); + + MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress; + MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1; + } +} + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + UpdateRmrrUsbAddress (SaPolicy); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..5c7f388213 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c @@ -0,0 +1,54 @@ +/** @file + DXE silicon policy update library. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "DxeSaPolicyInit.h" +#include "DxeGopPolicyInit.h" + +/** + Performs silicon late policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a Protocol, etc. + + The input Policy must be returned by SiliconPolicyDoneLate(). + + In FSP or non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + SA_POLICY_PROTOCOL *SaPolicy; + EFI_STATUS Status; + + SaPolicy = Policy; + UpdateDxeSaPolicy (SaPolicy); + + if (PcdGetBool(PcdIntelGopEnable)) { + // + // GOP Dxe Policy Initialization + // + Status = GopPolicyInitDxe(gImageHandle); + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR(Status); + } + + return Policy; +} + -- 2.16.2.windows.1