From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Wed, 25 Sep 2019 17:10:07 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2019 17:10:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,549,1559545200"; d="scan'208";a="364500419" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.9]) by orsmga005.jf.intel.com with ESMTP; 25 Sep 2019 17:10:05 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek Subject: [PATCH 1/2] UefiCpuPkg/PiSmmCpu: Remove hard code when getting physical line size Date: Thu, 26 Sep 2019 08:09:03 +0800 Message-Id: <20190926000904.187532-2-ray.ni@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190926000904.187532-1-ray.ni@intel.com> References: <20190926000904.187532-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The code replaces the hard code with macros defined in MdePkg\Include\Register\Intel\CpuId.h. No functionality impact. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index e5c4788c13..b8e95bf6ed 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -151,30 +151,28 @@ GetSubEntriesNum ( @return the maximum support address. **/ UINT8 -CalculateMaximumSupportAddress ( +GetPhysicalAddressBits ( VOID ) { - UINT32 RegEax; - UINT8 PhysicalAddressBits; - VOID *Hob; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunctionId; + VOID *Hob; // // Get physical address bits supported. // Hob = GetFirstHob (EFI_HOB_TYPE_CPU); if (Hob != NULL) { - PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; + return ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; } else { - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >= 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits = (UINT8) RegEax; - } else { - PhysicalAddressBits = 36; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL); + if (MaxExtendedFunctionId < CPUID_VIR_PHY_ADDRESS_SIZE) { + return 36; } + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL); + return (UINT8) VirPhyAddressSize.Bits.PhysicalAddressBits; } - return PhysicalAddressBits; } /** @@ -354,7 +352,7 @@ SmmInitPageTable ( mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess); m1GPageTableSupport = Is1GPageSupport (); m5LevelPagingNeeded = Is5LevelPagingNeeded (); - mPhysicalAddressBits = CalculateMaximumSupportAddress (); + mPhysicalAddressBits = GetPhysicalAddressBits (); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPagingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTableSupport)); -- 2.21.0.windows.1