From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: mateusz.albecki@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Thu, 26 Sep 2019 07:28:06 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 07:28:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,552,1559545200"; d="scan'208";a="364746378" Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by orsmga005.jf.intel.com with ESMTP; 26 Sep 2019 07:28:03 -0700 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: "Albecki, Mateusz" , Hao A Wu , Marcin Wojtas Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue Date: Thu, 26 Sep 2019 16:27:41 +0200 Message-Id: <20190926142744.3356-1-mateusz.albecki@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 SD host controller specification section 3.9 recommends that controller's bus timing should be switched after card's bus timing has been switched. In current eMMC driver implementation every host controller switch has been done before call to EmmcSwitchBusTiming which is causing issues on some eMMC controllers. In HS200 switch sequence we removed stopping and starting the SD clock when switching the host controller timing. Stopping the clock before bus timing switch is only neccessary if preset value enable is set in host controller. Current code doesn't check if this field is enabled or doesn't support this feature for any other bus timing change so it has been removed. Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that was introduced when we implemented v3 of override protocol. In new flow we allowed EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of the logic in that function is ready to service this speed mode. Tests performed on patch series v1: - eMMC enumeration and OS boot in HS400 - eMMC enumeration and OS boot in HS200 - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz Tests have been performed on 2 eMMC host controllers. One that has been failing with old driver and one that has been passing with old driver. Both controllers pass all tests with multiple eMMC devices used. Note: We were unable to test DDR speed mode because on test machines both new flow and old flow was failing with this speed. I suspect it is a hardware problem. Tests performed on patch series v2: -eMMC enumeration and OS boot in backwards compatible legacy timing. Performed on single host controller and 2 eMMC devices(Samsung and SanDisk) Cc: Hao A Wu Cc: Marcin Wojtas Albecki, Mateusz (3): MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200 switch MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing handling MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 ++++++++---------------- 1 file changed, 33 insertions(+), 74 deletions(-) -- 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.