From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ZIWYg299; spf=pass (domain: linaro.org, ip: 209.85.128.45, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by groups.io with SMTP; Thu, 26 Sep 2019 15:29:14 -0700 Received: by mail-wm1-f45.google.com with SMTP id 3so4143672wmi.3 for ; Thu, 26 Sep 2019 15:29:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Ebyo1VEfpwf59eP5ijl8IXJeLwL6JozLi5DLH5gLaSs=; b=ZIWYg29987eq5n0s+VWwPR9oBR5BkRogIbCtAcIWnsMVlYfXPTPAMl33fmEgsFH3bZ DTId93zKLj7c8K3n1RS595F7NP9vpAXfo1PBsychZgnB+tJMaZVLdEajWzy7yDBB3Mos +HF97hXLHmaVmBmB+BpYEX76R9n6HF33s4lwQjQTTqmt6FGVYmaKWGYEs9k6TpDZC6uM Odp4loQj1LcBoGWH4Vx7Qy8vmPSdKYcvQLMg6wPA7NgbQVp+Yw6lbLOxh+shwvmuUBkE 8oaE+fFTU+sYsTQ2kgGKkzZoGRTm0jJ9onjzEd2a9ZkT1AbwGn3LE8ept39ZIbkAHtRf oe5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Ebyo1VEfpwf59eP5ijl8IXJeLwL6JozLi5DLH5gLaSs=; b=XG1VU2JU8uWtddUp/rqjpi5MLxcw8aPL2tGYzafsACH+LdduP+1njVFGSjIGvrWX2w sK7N16REDMK9lQSgYy+KU8Spba7KnP4Nf+xTjnV2gRrm1g/+VpeUp6xf4UVJqmXPO2yi wxn4Wqj/VTef4Wl+7ziUhzKeB4B+xOOKKEx33/EHzJpzpEbOa9yrY7ns8Alq4n1F2XcY aIog2MYyrgmzqt33Dbeqb7ToDPZmRpxtcoyuy54zwrRH2ueCUbSomguxU1cvfOLxO/ZH PTRTNIaxCGtRfN2acuSTdEUD8+4yVZbe7iWUAJYn9WJclNzkhU7KjB0IQxdCalwT1Z5r 2c7w== X-Gm-Message-State: APjAAAVrodToEcAgeaG8JwfwkEwCpp+xmZRw8m9UjWzV2PKp2etYb5Bn Z7ZWmHQBu41ErVsCDvIzNNAahaMsclS/Xw== X-Google-Smtp-Source: APXvYqxtfs2VVGNImpA1HRNXcP5I2sRXf38i1RlG4NSCh0ZGW1yaKNxb6nHYgsYYJN9zjhflr3izUw== X-Received: by 2002:a1c:9988:: with SMTP id b130mr4960140wme.164.1569536952103; Thu, 26 Sep 2019 15:29:12 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o22sm1344685wra.96.2019.09.26.15.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 15:29:11 -0700 (PDT) Date: Thu, 26 Sep 2019 23:29:10 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Message-ID: <20190926222910.GD25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-3-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-3-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:27AM +0800, Abner Chang wrote: > RISC-V package library definitions. > > IndustryStandard/RiscV.h > -Add RiscV.h which conform with RISC-V Privilege Spec v1.10. > > RiscV.h > -Definition of EDK2 RISC-V implementation. > > Signed-off-by: Abner Chang > --- > RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++++++++++++++++++++++++++++ > RiscVPkg/Include/RiscV.h | 72 +++++++++++++++++++++ > 2 files changed, 174 insertions(+) > create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h > create mode 100644 RiscVPkg/Include/RiscV.h > > diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h > new file mode 100644 > index 0000000..d4d5002 > --- /dev/null > +++ b/RiscVPkg/Include/IndustryStandard/RiscV.h > @@ -0,0 +1,102 @@ > +/** @file > + RISC-V package definitions. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _RISCV_INDUSTRY_STANDARD_H_ > +#define _RISCV_INDUSTRY_STANDARD_H_ Please delete leading _ in above two lines. > + > +#if defined (MDE_CPU_RISCV64) > +#define RISC_V_XLEN_BITS 64 > +#else > +#endif > + > +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0) > +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1) > +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2) > +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3) > +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4) > +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5) > +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6) > +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7) > +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8) > +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9) > +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10) > +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11) > +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12) > +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13) > +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14) > +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15) > +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16) > +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17) > +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18) > +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19) > +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20) > +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21) > +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22) > +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23) > +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24) > +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25) > + > +// > +// RISC-V CSR definitions. > +// > +// > +// Machine information > +// > +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 > +#define RISCV_CSR_MACHINE_MARCHID 0xF12 > +#define RISCV_CSR_MACHINE_MIMPID 0xF13 > +#define RISCV_CSR_MACHINE_HARRID 0xF14 > +// > +// Machine Trap Setup. > +// > +#define RISCV_CSR_MACHINE_MSTATUS 0x300 > +#define RISCV_CSR_MACHINE_MISA 0x301 > +#define RISCV_CSR_MACHINE_MEDELEG 0x302 > +#define RISCV_CSR_MACHINE_MIDELEG 0x303 > +#define RISCV_CSR_MACHINE_MIE 0x304 > +#define RISCV_CSR_MACHINE_MTVEC 0x305 > + > +#define RISCV_TIMER_COMPARE_BITS 32 > +// > +// Machine Timer and Counter. > +// > +//#define RISCV_CSR_MACHINE_MTIME 0x701 > +//#define RISCV_CSR_MACHINE_MTIMEH 0x741 > +// > +// Machine Trap Handling. > +// > +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 > +#define RISCV_CSR_MACHINE_MEPC 0x341 > +#define RISCV_CSR_MACHINE_MCAUSE 0x342 > + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f > + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) > +#define RISCV_CSR_MACHINE_MBADADDR 0x343 > +#define RISCV_CSR_MACHINE_MIP 0x344 > + > +// > +// Machine Protection and Translation. > +// > +#define RISCV_CSR_MACHINE_MBASE 0x380 > +#define RISCV_CSR_MACHINE_MBOUND 0x381 > +#define RISCV_CSR_MACHINE_MIBASE 0x382 > +#define RISCV_CSR_MACHINE_MIBOUND 0x383 > +#define RISCV_CSR_MACHINE_MDBASE 0x384 > +#define RISCV_CSR_MACHINE_MDBOUND 0x385 > +// > +// Machine Read-Write Shadow of Hypervisor Read-Only Registers > +// > +#define RISCV_CSR_HTIMEW 0xB01 > +#define RISCV_CSR_HTIMEHW 0xB81 > +// > +// Machine Host-Target Interface (Non-Standard Berkeley Extension) > +// > +#define RISCV_CSR_MTOHOST 0x780 > +#define RISCV_CSR_MFROMHOST 0x781 > + > +#endif > diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h > new file mode 100644 > index 0000000..1c3ab55 > --- /dev/null > +++ b/RiscVPkg/Include/RiscV.h > @@ -0,0 +1,72 @@ > +/** @file > + RISC-V package definitions. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _RISCV_H_ > +#define _RISCV_H_ Please delete leading _ in above two lines. With that change in both these files: Reviewed-by: Leif Lindholm > + > +#include > + > +// > +// Structure for 128-bit value > +// > +typedef struct { > + UINT64 Value64_L; > + UINT64 Value64_H; > +} RISCV_UINT128; > + > +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 > +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; > + > +/// > +/// Exception handlers in context. > +/// > +typedef struct _EXCEPTION_HANDLER_CONTEXT { > + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; > + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; > + EFI_PHYSICAL_ADDRESS IllegalInstHander; > + EFI_PHYSICAL_ADDRESS BreakpointHander; > + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; > + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; > + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; > + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; > + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; > + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; > + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; > + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; > +} EXCEPTION_HANDLER_CONTEXT; > + > +/// > +/// Exception handlers in context. > +/// > +typedef struct _INTERRUPT_HANDLER_CONTEXT { > + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; > + EFI_PHYSICAL_ADDRESS TimerIntHandler; > +} INTERRUPT_HANDLER_CONTEXT; > + > +/// > +/// Interrupt handlers in context. > +/// > +typedef struct _TRAP_HANDLER_CONTEXT { > + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; > + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; > +} TRAP_HANDLER_CONTEXT; > + > +/// > +/// Machine mode context used for saveing hart-local context. > +/// > +typedef struct _RISCV_MACHINE_MODE_CONTEXT { > + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. > + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler. > + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler. > + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler. > + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler. > + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode. > +} RISCV_MACHINE_MODE_CONTEXT; > + > +#endif > -- > 2.7.4 > > > >