From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=Dcvq4pHz; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Thu, 26 Sep 2019 15:45:58 -0700 Received: by mail-wr1-f67.google.com with SMTP id r5so505077wrm.12 for ; Thu, 26 Sep 2019 15:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SzVSKhhLHipltpagBWYSNi8m85x+aGr/3iXy5tVJB74=; b=Dcvq4pHzGvbz4dhtRleGPoIcKMmK3TAkdim7ra/VmmDdrygyMJKWQLjTCru75QHaLG pqyiL8trIt5yzzqxU1i2kdUzUMUgP2MM0MSzr8Bzu9FMFDv3+109mACmaKEji6JE9ADn yFMUmnFNHEeNHRIfw+lTqh2d17+6FvXcUOd+dry6pZ3kkbvej6gQKIW/VHPD1T8eB379 WasJspQVhwr8EANjtTB9FnH1RCErOBmJGOhOYm2iEbOzwefWGVAPBJL0g1rBiFi9C4oC YfL4sjge+Yyhdaek+PHycTs7I6HLqIyydtaI3UZPz/EYOQWjyj/gCkN80e6DYcuL2xIr rkSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=SzVSKhhLHipltpagBWYSNi8m85x+aGr/3iXy5tVJB74=; b=GfwoDNY7W5yOhM5YtmbiItbtLlOGUQi+EO9e54zIIJxpBkwAofvUxjalpzx1X91j+/ mBvG8HOo/icx1Mp/k2GvBx8vReQbvHdfo1iiL8Eg7Mjh2wFm0DSK1pc1r39kuKmqdTuC 6lxIzI+hjhns47rbDANciGzg9Mphn/+e8bjF9lIUJMB9xjwSXi71UxZ14kfZ23Q0GkQE awqXs5YYHdIeMmWqOJBaSOZ0wyKeOV8AaoDqJLE/u/aXSGOslW/LBT8BVAIx3hK3pDkv r3tgkSu+O+ybkEXniH03WlVhwIJCH7SAvdGPTMpvt6cxw5rj+N40cd4UK07uAg/mJZV6 XK/Q== X-Gm-Message-State: APjAAAUboIz8mKPmy35fFiz+zoSAaPzviDH6LaQJ5hZCgVAdI2k1dz/r N7DlSkZDqgh9sNxQgohYKJPzpNSDHYR5iw== X-Google-Smtp-Source: APXvYqz9XUK9XtTUO8N1EAr9hc8SZVHeVNdMLM0z1C3G3ens5HXP8IOH6jVAsCdy8F4VraYR2V36eQ== X-Received: by 2002:adf:cd81:: with SMTP id q1mr546217wrj.185.1569537956541; Thu, 26 Sep 2019 15:45:56 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id q192sm7307997wme.23.2019.09.26.15.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 15:45:55 -0700 (PDT) Date: Thu, 26 Sep 2019 23:45:54 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions. Message-ID: <20190926224554.GG25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-6-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-6-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:30AM +0800, Abner Chang wrote: > Add RISC-V processor related definitions. > > Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm > --- > MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++ > MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++++++++++ > MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++ > MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++ > MdePkg/Include/Uefi/UefiSpec.h | 5 +++ > 5 files changed, 89 insertions(+) > > diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h > index 720bb08..ca3fd0b 100644 > --- a/MdePkg/Include/IndustryStandard/PeImage.h > +++ b/MdePkg/Include/IndustryStandard/PeImage.h > @@ -9,6 +9,8 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define IMAGE_FILE_MACHINE_X64 0x8664 > #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 > #define IMAGE_FILE_MACHINE_ARM64 0xAA64 > +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 > +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 > > // > // EXE file formats > @@ -494,6 +499,13 @@ typedef struct { > #define EFI_IMAGE_REL_BASED_DIR64 10 > > /// > +/// Relocation types of RISC-V processor. > +/// > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 > + > +/// > /// Line number format. > /// > typedef struct { > diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h > index 800e771..1a29cc0 100644 > --- a/MdePkg/Include/Protocol/DebugSupport.h > +++ b/MdePkg/Include/Protocol/DebugSupport.h > @@ -7,6 +7,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -603,6 +604,59 @@ typedef struct { > UINT64 FAR; // Fault Address Register > } EFI_SYSTEM_CONTEXT_AARCH64; > > +/// > +/// RISC-V processor exception types. > +/// > +#define EXCEPT_RISCV_INST_MISALIGNED 0 > +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 > +#define EXCEPT_RISCV_ILLEGAL_INST 2 > +#define EXCEPT_RISCV_BREAKPOINT 3 > +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 > +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 > +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 > +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 > +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 > +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 > +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 > +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 > + > +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 > +#define EXCEPT_RISCV_TIMER_INT 0x1 > + > +typedef struct { > + UINT64 X0; > + UINT64 X1; > + UINT64 X2; > + UINT64 X3; > + UINT64 X4; > + UINT64 X5; > + UINT64 X6; > + UINT64 X7; > + UINT64 X8; > + UINT64 X9; > + UINT64 X10; > + UINT64 X11; > + UINT64 X12; > + UINT64 X13; > + UINT64 X14; > + UINT64 X15; > + UINT64 X16; > + UINT64 X17; > + UINT64 X18; > + UINT64 X19; > + UINT64 X20; > + UINT64 X21; > + UINT64 X22; > + UINT64 X23; > + UINT64 X24; > + UINT64 X25; > + UINT64 X26; > + UINT64 X27; > + UINT64 X28; > + UINT64 X29; > + UINT64 X30; > + UINT64 X31; > +} EFI_SYSTEM_CONTEXT_RISCV64; > > /// > /// Universal EFI_SYSTEM_CONTEXT definition. > @@ -614,6 +668,7 @@ typedef union { > EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; > EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; > EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; > + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; > } EFI_SYSTEM_CONTEXT; > > // > diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h > index b02d270..8a9e4a1 100644 > --- a/MdePkg/Include/Protocol/PxeBaseCode.h > +++ b/MdePkg/Include/Protocol/PxeBaseCode.h > @@ -3,6 +3,8 @@ > devices for network access and network booting. > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > @par Revision Reference: > @@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; > #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A > #elif defined (MDE_CPU_AARCH64) > #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B > +#elif defined (MDE_CPU_RISCV64) > +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B > #endif > > > diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h > index a62f13d..d979412 100644 > --- a/MdePkg/Include/Uefi/UefiBaseType.h > +++ b/MdePkg/Include/Uefi/UefiBaseType.h > @@ -3,6 +3,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -240,6 +241,12 @@ typedef union { > /// > #define EFI_IMAGE_MACHINE_AARCH64 0xAA64 > > +/// > +/// PE32+ Machine type for RISC-V 32/64/128 > +/// > +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 > +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 > +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 > > #if defined (MDE_CPU_IA32) > > @@ -268,6 +275,12 @@ typedef union { > > #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > > +#elif defined (MDE_CPU_RISCV64) > +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ > + ((Machine) == EFI_IMAGE_MACHINE_RISCV64) > + > +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) > + > #elif defined (MDE_CPU_EBC) > > /// > diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h > index 44a0a6a..e2d4539 100644 > --- a/MdePkg/Include/Uefi/UefiSpec.h > +++ b/MdePkg/Include/Uefi/UefiSpec.h > @@ -6,6 +6,8 @@ > by this include file. > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -2178,6 +2180,7 @@ typedef struct { > #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" > #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" > #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" > +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI" > > #if defined (MDE_CPU_IA32) > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 > @@ -2188,6 +2191,8 @@ typedef struct { > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM > #elif defined (MDE_CPU_AARCH64) > #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 > +#elif defined (MDE_CPU_RISCV64) > + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 > #else > #error Unknown Processor Type > #endif > -- > 2.7.4 > > > >