* [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on
@ 2019-09-23 0:31 Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
` (44 more replies)
0 siblings, 45 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
This branch "RISC-V-V2" is used to contribute RISC-V architecture on EDK2.
Compare to the old branch "RISC-V", this branch "RISC-V-V2" is created based on
the most recent edk2/master @37eef910. This is easier for reviewers to have
clear ideas of edk2 code changes for RISC-V EDK2 implementation.
Because of the code changes made on old branch "RISC-V" is stale and not
compliant with the latest RISC-V spec, this new branch has the fresh changes
for RISC-V EDK2 implementation.
The main changes of these series of patches are,
- Add RiscVPkg which conform with RISC-V Privilege Spec v1.10.
- Incorporate and leverage RISC-V OpenSBI to provide EDK2 port OpenSBI library.
- Provide RISC-V platform implementation specific drivers to EDK2 RISC-V platform
package.
- Provide generic RISC-V SMBIOS DXE drive to create SMBIOS type 4, 7 and 44 records,
in which the SMBIOS type 44 record is introduced in SMBIOS spec 3.3.0.
Abner Chang (29):
RiscVPkg: RISC-V processor package.
RiscVPkg/Include: Add header files of RISC-V CPU package
RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
MdePkg: RISC-V RV64 binding in MdePkg
MdePkg/Include: RISC-V definitions.
MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
implementation.
MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
MdePkg/BaseSynchronizationLib: RISC-V cache related code.
MdeModulePkg/Logo
NetworkPkg
RiscVPkg/Library: RISC-V CPU library
RiscVPkg/Library: Add RISC-V exception library
RiscVPkg/Library: Add RISC-V timer library
RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service
Table Pointer library
RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary
Memory library
RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
BaseTools: BaseTools changes for RISC-V platform.
BaseTools/Scripts
RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
platforms.
edk2-staging/RISC-V-V2: Add submodule
edk2-staging/RISC-V-V2: Add ReadMe
edk2-staging: Update Maintainers.txt
.gitmodules | 16 +-
BaseTools/Conf/build_rule.template | 62 ++-
BaseTools/Conf/tools_def.template | 64 ++-
BaseTools/Scripts/GccBaseRiscV.lds | 66 +++
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++-
BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 62 +++
.../Source/C/Include/IndustryStandard/PeImage.h | 6 +
BaseTools/Source/Python/Common/DataType.py | 7 +-
Maintainers.txt | 5 +
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +-
MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 +++
MdeModulePkg/Logo/Logo.inf | 2 +-
.../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +-
MdePkg/Include/IndustryStandard/PeImage.h | 12 +
MdePkg/Include/Library/BaseLib.h | 26 +
MdePkg/Include/Protocol/DebugSupport.h | 55 ++
MdePkg/Include/Protocol/PxeBaseCode.h | 4 +
MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++
MdePkg/Include/Uefi/UefiBaseType.h | 13 +
MdePkg/Include/Uefi/UefiSpec.h | 5 +
.../BaseCacheMaintenanceLib.inf | 4 +
.../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +
MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +
MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 +
MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 +
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +
MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++
.../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++
MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 ++
.../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +
MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 ++
.../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++
MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++
.../BaseSynchronizationLib.inf | 6 +
.../RiscV64/Synchronization.c | 183 +++++++
.../RiscV64/SynchronizationAsm.S | 78 +++
MdePkg/MdePkg.dec | 5 +-
NetworkPkg/Network.dsc.inc | 2 +-
RiscVEdk2Readme.md | 34 ++
RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++
RiscVPkg/Include/Library/RiscVCpuLib.h | 68 +++
RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++
.../Library/RiscVPlatformTempMemoryInitLib.h | 17 +
RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++
RiscVPkg/Include/RiscV.h | 72 +++
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++
RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++
RiscVPkg/Include/sbi/sbi.h | 96 ++++
RiscVPkg/Include/sbi/sbi_bits.h | 17 +
RiscVPkg/Include/sbi/sbi_types.h | 18 +
.../PeiServicesTablePointerLibOpenSbi.inf | 38 ++
.../PeiServicesTablePointerLibOpenSbi.uni | 23 +
.../PeiServicesTablePointerOpenSbi.c | 121 +++++
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 ++++
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 ++
.../RiscVDxeIplHandoffLib.inf | 32 ++
.../RiscVDxeIplHandoffOpenSbiLib.c | 102 ++++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 33 ++
.../RiscVExceptionLib/CpuExceptionHandler.S | 88 +++
.../CpuExceptionHandlerDxeLib.inf | 42 ++
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 +
.../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++
.../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++
.../Riscv64/TempMemInit.S | 26 +
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +
RiscVPkg/RiscVPkg.dec | 42 ++
RiscVPkg/RiscVPkg.uni | 13 +
RiscVPkg/RiscVPkgExtra.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 +++++++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 ++++++++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
.../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
RiscVPkg/opensbi | 1 +
100 files changed, 6085 insertions(+), 66 deletions(-)
create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
create mode 100644 RiscVEdk2Readme.md
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
create mode 100644 RiscVPkg/Include/RiscV.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
create mode 100644 RiscVPkg/Include/sbi/sbi.h
create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
create mode 160000 RiscVPkg/opensbi
--
2.7.4
^ permalink raw reply [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:26 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
` (43 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
- Add RiscVPkg package which provides RISC-V processor related
drivers and libraries.
- Support RISC-V OpenSBI and RISC-V platforms
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/RiscVPkg.dec | 27 +++++++++++++++++++++++++++
RiscVPkg/RiscVPkg.uni | 13 +++++++++++++
| 13 +++++++++++++
3 files changed, 53 insertions(+)
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
new file mode 100644
index 0000000..74314e8
--- /dev/null
+++ b/RiscVPkg/RiscVPkg.dec
@@ -0,0 +1,27 @@
+## @file RiscVPkg.dec
+# This Package provides UEFI RISC-V modules and libraries.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVPkg
+ PACKAGE_UNI_FILE = RiscVPkg.uni
+ PACKAGE_GUID = 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+ opensbi # OpebSBI header file reference ("include/sbi/...")
+ opensbi/include # Header file reference from opensbi files, ("sbi/...")
+ opensbi/lib/utils/libfdt
+
+[Guids]
+ gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVPkgExtra.uni
diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni
new file mode 100644
index 0000000..5ec7a99
--- /dev/null
+++ b/RiscVPkg/RiscVPkg.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V modules and libraries."
+
--git a/RiscVPkg/RiscVPkgExtra.uni b/RiscVPkg/RiscVPkgExtra.uni
new file mode 100644
index 0000000..b50a6b4
--- /dev/null
+++ b/RiscVPkg/RiscVPkgExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RiscV package"
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:29 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
` (42 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RISC-V package library definitions.
IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.
RiscV.h
-Definition of EDK2 RISC-V implementation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++++++++++++++++++++++++++++
RiscVPkg/Include/RiscV.h | 72 +++++++++++++++++++++
2 files changed, 174 insertions(+)
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
create mode 100644 RiscVPkg/Include/RiscV.h
diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000..d4d5002
--- /dev/null
+++ b/RiscVPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,102 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _RISCV_INDUSTRY_STANDARD_H_
+#define _RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+ #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+ #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
+
+#endif
diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h
new file mode 100644
index 0000000..1c3ab55
--- /dev/null
+++ b/RiscVPkg/Include/RiscV.h
@@ -0,0 +1,72 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _RISCV_H_
+#define _RISCV_H_
+
+#include <IndustryStandard/RiscV.h>
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:41 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
` (41 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add EDK2 RISC-V OpenSBI header files and opensbi-HOWTO.txt for users to build RISC-V platform with RISC-V OpenSBI library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++++++++++++
RiscVPkg/Include/sbi/sbi.h | 96 +++++++++++++++++++++++++++++++
RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++
RiscVPkg/Include/sbi/sbi_types.h | 18 ++++++
4 files changed, 169 insertions(+)
create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
create mode 100644 RiscVPkg/Include/sbi/sbi.h
create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
new file mode 100644
index 0000000..498faf4
--- /dev/null
+++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
@@ -0,0 +1,38 @@
+/** @file
+ RISC-V OpesbSBI Platform Firmware context definition
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SBI_FIRMWARE_CONTEXT_H_
+#define _SBI_FIRMWARE_CONTEXT_H_
+
+#include <RiscV.h>
+
+#define RISC_V_MAX_HART_SUPPORTED 16
+
+//
+// keep the structure member in 64-bit alignment.
+//
+#pragma pack(push)
+#pragma pack(8)
+
+typedef struct {
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
+
+typedef struct {
+ VOID *PeiServiceTable; // PEI Service table
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+#pragma pack(pop)
+#endif
+
diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
new file mode 100644
index 0000000..89d5016
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi.h
@@ -0,0 +1,96 @@
+/** @file
+ SBI inline function calls.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SBI_H_
+#define _SBI_H_
+
+#include <sbi/sbi_types.h> // Reference to header file wrapper
+#include <include/sbi/riscv_asm.h> // Reference to header file in opensbi
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({ \
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
+ asm volatile ("ecall" \
+ : "+r" (a0) \
+ : "r" (a1), "r" (a2), "r" (a7) \
+ : "memory"); \
+ a0; \
+})
+
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+ SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+ return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+ SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+ SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+ SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+ SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+ SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h
new file mode 100644
index 0000000..1e6bda3
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_bits.h
@@ -0,0 +1,17 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _EDK2_SBI_BITS_H_
+#define _EDK2_SBI_BITS_H_
+
+#undef MAX
+#undef MIN
+
+#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi
+
+#endif
diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h
new file mode 100644
index 0000000..d7ff227
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_types.h
@@ -0,0 +1,18 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _EDK2_SBI_TYPES_H_
+#define _EDK2_SBI_TYPES_H_
+
+#undef TRUE
+#undef FALSE
+#undef NULL
+
+#include "opensbi/include/sbi/sbi_types.h" // Reference to header file in opensbi
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (2 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:44 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
` (40 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++++++++++
MdePkg/MdePkg.dec | 5 +-
2 files changed, 177 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h
new file mode 100644
index 0000000..c3d4ef7
--- /dev/null
+++ b/MdePkg/Include/RiscV64/ProcessorBind.h
@@ -0,0 +1,173 @@
+/** @file
+ Processor or Compiler specific defines and types for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_RISCV64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined(__GNUC__)
+#pragma pack()
+#endif
+
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long UINT64 __attribute__ ((aligned (8)));
+///
+/// 8-byte signed value
+///
+typedef long long INT64 __attribute__ ((aligned (8)));
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int UINT32 __attribute__ ((aligned (4)));
+///
+/// 4-byte signed value
+///
+typedef int INT32 __attribute__ ((aligned (4)));
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16 __attribute__ ((aligned (2)));
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
+///
+/// 2-byte signed value
+///
+typedef short INT16 __attribute__ ((aligned (2)));
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64 UINTN __attribute__ ((aligned (8)));
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64 INTN __attribute__ ((aligned (8)));
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x8000000000000000ULL
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC000000000000000ULL
+
+///
+/// Maximum legal RV64 address
+///
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)
+///
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+///
+/// Maximum legal RISC-V INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// The stack alignment required for RISC-V
+///
+#define CPU_STACK_ALIGNMENT 16
+
+///
+/// Page allocation granularity for RISC-V
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#ifdef EFIAPI
+ ///
+ /// If EFIAPI is already defined, then we use that definition.
+ ///
+#elif defined(__GNUC__)
+ ///
+ /// Define the standard calling convention regardless of optimization level
+ /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
+ /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+ /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+ /// x64. Warning the assembly code in the MDE x64 does not follow the correct
+ /// ABI for the standard x64 (x86-64) GCC.
+ ///
+ #define EFIAPI
+#else
+ ///
+ /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+ /// is the standard.
+ ///
+ #define EFIAPI
+#endif
+
+#if defined(__GNUC__)
+ ///
+ /// For GNU assembly code, .global or .globl can declare global symbols.
+ /// Define this macro to unify the usage.
+ ///
+ #define ASM_GLOBAL .globl
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On x64 CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 3fd7d16..1aaa97d 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -6,7 +6,7 @@
#
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,6 +39,9 @@
[Includes.AARCH64]
Include/AArch64
+[Includes.RISCV64]
+ Include/RiscV64
+
[LibraryClasses]
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
# and the standard requests defined in Usb 1.1 spec.
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (3 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:45 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
` (39 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISC-V processor related definitions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++
MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++++++++++
MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++
MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++
MdePkg/Include/Uefi/UefiSpec.h | 5 +++
5 files changed, 89 insertions(+)
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 720bb08..ca3fd0b 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -9,6 +9,8 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
#define IMAGE_FILE_MACHINE_ARM64 0xAA64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+#define IMAGE_FILE_MACHINE_RISCV128 0x5128
//
// EXE file formats
@@ -494,6 +499,13 @@ typedef struct {
#define EFI_IMAGE_REL_BASED_DIR64 10
///
+/// Relocation types of RISC-V processor.
+///
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+
+///
/// Line number format.
///
typedef struct {
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 800e771..1a29cc0 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -7,6 +7,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -603,6 +604,59 @@ typedef struct {
UINT64 FAR; // Fault Address Register
} EFI_SYSTEM_CONTEXT_AARCH64;
+///
+/// RISC-V processor exception types.
+///
+#define EXCEPT_RISCV_INST_MISALIGNED 0
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
+#define EXCEPT_RISCV_ILLEGAL_INST 2
+#define EXCEPT_RISCV_BREAKPOINT 3
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
+
+#define EXCEPT_RISCV_SOFTWARE_INT 0x0
+#define EXCEPT_RISCV_TIMER_INT 0x1
+
+typedef struct {
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 X29;
+ UINT64 X30;
+ UINT64 X31;
+} EFI_SYSTEM_CONTEXT_RISCV64;
///
/// Universal EFI_SYSTEM_CONTEXT definition.
@@ -614,6 +668,7 @@ typedef union {
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
} EFI_SYSTEM_CONTEXT;
//
diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index b02d270..8a9e4a1 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -3,6 +3,8 @@
devices for network access and network booting.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A
#elif defined (MDE_CPU_AARCH64)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
#endif
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index a62f13d..d979412 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -3,6 +3,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -240,6 +241,12 @@ typedef union {
///
#define EFI_IMAGE_MACHINE_AARCH64 0xAA64
+///
+/// PE32+ Machine type for RISC-V 32/64/128
+///
+#define EFI_IMAGE_MACHINE_RISCV32 0x5032
+#define EFI_IMAGE_MACHINE_RISCV64 0x5064
+#define EFI_IMAGE_MACHINE_RISCV128 0x5128
#if defined (MDE_CPU_IA32)
@@ -268,6 +275,12 @@ typedef union {
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
#elif defined (MDE_CPU_EBC)
///
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index 44a0a6a..e2d4539 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -6,6 +6,8 @@
by this include file.
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -2178,6 +2180,7 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
#if defined (MDE_CPU_IA32)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
@@ -2188,6 +2191,8 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
#elif defined (MDE_CPU_AARCH64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
+#elif defined (MDE_CPU_RISCV64)
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
#else
#error Unknown Processor Type
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (4 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
` (38 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
index 9da4507..84f3688 100644
--- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -5,6 +5,7 @@
# the capsule runtime services are ready.
#
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -21,20 +22,20 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
CapsuleService.c
CapsuleService.h
-[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
SaveLongModeContext.c
-[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
CapsuleCache.c
-[Sources.Ia32, Sources.X64, Sources.EBC]
+[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
CapsuleReset.c
[Sources.ARM, Sources.AARCH64]
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (5 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:56 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
` (37 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISC-V RV64 BaseLib functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Include/Library/BaseLib.h | 26 ++
MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++
MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +++
MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++
MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++
MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 +++
.../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++
MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++
.../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++
MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++
.../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++
MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++++++++++++++
15 files changed, 670 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 2a75bc0..b8c8512 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4,6 +4,8 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -124,6 +126,30 @@ typedef struct {
#endif // defined (MDE_CPU_AARCH64)
+#if defined (MDE_CPU_RISCV64)
+///
+/// The RISC-V architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT64 RA;
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 S9;
+ UINT64 S10;
+ UINT64 S11;
+ UINT64 SP;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_RISCV64)
//
// String Services
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3586beb..28d5795 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,7 +21,7 @@
LIBRARY_CLASS = BaseLib
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
@@ -381,6 +382,21 @@
AArch64/CpuBreakpoint.asm | MSFT
AArch64/SpeculationBarrier.asm | MSFT
+[Sources.RISCV64]
+ Math64.c
+ RiscV64/Unaligned.c
+ RiscV64/InternalSwitchStack.c
+ RiscV64/CpuBreakpoint.c
+ RiscV64/GetInterruptState.c
+ RiscV64/DisableInterrupts.c
+ RiscV64/EnableInterrupts.c
+ RiscV64/CpuPause.c
+ RiscV64/RiscVSetJumpLongJump.S | GCC
+ RiscV64/RiscVCpuBreakpoint.S | GCC
+ RiscV64/RiscVCpuPause.S | GCC
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
new file mode 100644
index 0000000..d82b1d5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
@@ -0,0 +1,27 @@
+/** @file
+ CPU breakpoint for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuBreakpoint (VOID);
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ RiscVCpuBreakpoint ();
+}
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
new file mode 100644
index 0000000..8eb6b65
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
@@ -0,0 +1,29 @@
+/** @file
+ CPU pause for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuPause (VOID);
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ RiscVCpuPause ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
new file mode 100644
index 0000000..7ee5eb1
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
@@ -0,0 +1,24 @@
+/** @file
+ CPU disable interrupt function for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BaseLibInternals.h"
+
+extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ RiscVDisableSupervisorModeInterrupts ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
new file mode 100644
index 0000000..9aa0d9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
@@ -0,0 +1,25 @@
+/** @file
+ CPU enable interrupt function for RISC-V
+
+ Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ RiscVEnableSupervisorModeInterrupt ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
new file mode 100644
index 0000000..0ef0213
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -0,0 +1,21 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V cache operation.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+.align 3
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+
+ASM_PFX(RiscVInvalidateInstCacheAsm):
+ fence.i
+ ret
+
+ASM_PFX(RiscVInvalidateDataCacheAsm):
+ fence
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
new file mode 100644
index 0000000..8f764fb
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
@@ -0,0 +1,35 @@
+/** @file
+ CPU get interrupt state function for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE is interrupts are currently enabled. Otherwise
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ unsigned long RetValue;
+
+ RetValue = RiscVGetSupervisorModeInterrupts ();
+ return RetValue? TRUE: FALSE;
+}
+
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
new file mode 100644
index 0000000..1082d4e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
@@ -0,0 +1,55 @@
+/** @file
+ Switch stack function for RISC-V
+
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+{
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
+
+ DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
+ EntryPoint, Context1, Context2, NewStack));
+ JumpBuffer.RA = (UINTN)EntryPoint;
+ JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
+ JumpBuffer.S0 = (UINT64)(UINTN)Context1;
+ JumpBuffer.S1 = (UINT64)(UINTN)Context2;
+ LongJump (&JumpBuffer, (UINTN)-1);
+ ASSERT(FALSE);
+}
diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
new file mode 100644
index 0000000..a62b882
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
@@ -0,0 +1,32 @@
+/** @file
+ Long jump implementation of RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer.
+ This function never returns to the caller.
+ Instead is resumes execution based on the state of JumpBuffer.
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is restored.
+
+**/
+VOID
+EFIAPI
+InternalLongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ )
+{
+ ASSERT (FALSE);
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
new file mode 100644
index 0000000..1a45e2a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------
+//
+// CpuBreakpoint for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
+ASM_PFX(RiscVCpuBreakpoint):
+ ebreak
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
new file mode 100644
index 0000000..ceba0c0
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------
+//
+// CpuPause for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuPause)
+ASM_PFX(RiscVCpuPause):
+ nop
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
new file mode 100644
index 0000000..8fdb544
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V Supervisor Mode interrupt enable/disable
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
+ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
+ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
+
+# define MSTATUS_SIE 0x00000002
+# define CSR_SSTATUS 0x100
+
+ASM_PFX(RiscVDisableSupervisorModeInterrupts):
+ li a1, MSTATUS_SIE
+ csrc CSR_SSTATUS, a1
+ ret
+
+ASM_PFX(RiscVEnableSupervisorModeInterrupt):
+ li a1, MSTATUS_SIE
+ csrs CSR_SSTATUS, a1
+ ret
+
+ASM_PFX(RiscVGetSupervisorModeInterrupts):
+ csrr a0, CSR_SSTATUS
+ andi a0, a0, MSTATUS_SIE
+ ret
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
new file mode 100644
index 0000000..e72dd7f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+//
+// Set/Long jump for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+# define REG_S sd
+# define REG_L ld
+# define SZREG 8
+.align 3
+ .globl SetJump
+
+SetJump:
+ REG_S ra, 0*SZREG(a0)
+ REG_S s0, 1*SZREG(a0)
+ REG_S s1, 2*SZREG(a0)
+ REG_S s2, 3*SZREG(a0)
+ REG_S s3, 4*SZREG(a0)
+ REG_S s4, 5*SZREG(a0)
+ REG_S s5, 6*SZREG(a0)
+ REG_S s6, 7*SZREG(a0)
+ REG_S s7, 8*SZREG(a0)
+ REG_S s8, 9*SZREG(a0)
+ REG_S s9, 10*SZREG(a0)
+ REG_S s10,11*SZREG(a0)
+ REG_S s11,12*SZREG(a0)
+ REG_S sp, 13*SZREG(a0)
+ li a0, 0
+ ret
+
+ .globl InternalLongJump
+InternalLongJump:
+ REG_L ra, 0*SZREG(a0)
+ REG_L s0, 1*SZREG(a0)
+ REG_L s1, 2*SZREG(a0)
+ REG_L s2, 3*SZREG(a0)
+ REG_L s3, 4*SZREG(a0)
+ REG_L s4, 5*SZREG(a0)
+ REG_L s5, 6*SZREG(a0)
+ REG_L s6, 7*SZREG(a0)
+ REG_L s7, 8*SZREG(a0)
+ REG_L s8, 9*SZREG(a0)
+ REG_L s9, 10*SZREG(a0)
+ REG_L s10,11*SZREG(a0)
+ REG_L s11,12*SZREG(a0)
+ REG_L sp, 13*SZREG(a0)
+
+ add a0, s0, 0
+ add a1, s1, 0
+ add a2, s2, 0
+ add a3, s3, 0
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
new file mode 100644
index 0000000..012d913
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
@@ -0,0 +1,264 @@
+/** @file
+ RISC-V specific functionality for (un)aligned memory read/write.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Reads a 16-bit value from memory that may be unaligned.
+
+ This function returns the 16-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 16-bit value that may be unaligned.
+
+ @return The 16-bit value read from Buffer.
+
+**/
+UINT16
+EFIAPI
+ReadUnaligned16 (
+ IN CONST UINT16 *Buffer
+ )
+{
+ UINT16 Value;
+ INT8 Count;
+
+ ASSERT (Buffer != NULL);
+
+ for (Count = sizeof (UINT16) - 1, Value = 0; Count >= 0 ; Count --) {
+ Value = Value << 8;
+ Value |= *((UINT8*)Buffer + Count);
+ }
+ return Value;
+}
+
+/**
+ Writes a 16-bit value to memory that may be unaligned.
+
+ This function writes the 16-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 16-bit value that may be unaligned.
+ @param Value 16-bit value to write to Buffer.
+
+ @return The 16-bit value to write to Buffer.
+
+**/
+UINT16
+EFIAPI
+WriteUnaligned16 (
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
+ )
+{
+ INT8 Count;
+ UINT16 ValueTemp;
+
+ ASSERT (Buffer != NULL);
+
+ for (Count = 0, ValueTemp = Value; Count < sizeof (UINT16) ; Count ++) {
+ *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
+ ValueTemp = ValueTemp >> 8;
+ }
+ return Value;
+}
+
+/**
+ Reads a 24-bit value from memory that may be unaligned.
+
+ This function returns the 24-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 24-bit value that may be unaligned.
+
+ @return The 24-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned24 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ UINT32 Value;
+ INT8 Count;
+
+ ASSERT (Buffer != NULL);
+ for (Count = 2, Value = 0; Count >= 0 ; Count --) {
+ Value = Value << 8;
+ Value |= *((UINT8*)Buffer + Count);
+ }
+ return Value;
+}
+
+/**
+ Writes a 24-bit value to memory that may be unaligned.
+
+ This function writes the 24-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 24-bit value that may be unaligned.
+ @param Value 24-bit value to write to Buffer.
+
+ @return The 24-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned24 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ INT8 Count;
+ UINT32 ValueTemp;
+
+ ASSERT (Buffer != NULL);
+ for (Count = 0, ValueTemp = Value; Count < 3 ; Count ++) {
+ *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
+ ValueTemp = ValueTemp >> 8;
+ }
+ return Value;
+}
+
+/**
+ Reads a 32-bit value from memory that may be unaligned.
+
+ This function returns the 32-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 32-bit value that may be unaligned.
+
+ @return The 32-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned32 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ UINT32 Value;
+ INT8 Count;
+
+ ASSERT (Buffer != NULL);
+
+ for (Count = sizeof (UINT32) - 1, Value = 0; Count >= 0 ; Count --) {
+ Value = Value << 8;
+ Value |= *((UINT8*)Buffer + Count);
+ }
+ return Value;
+}
+
+/**
+ Writes a 32-bit value to memory that may be unaligned.
+
+ This function writes the 32-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 32-bit value that may be unaligned.
+ @param Value The 32-bit value to write to Buffer.
+
+ @return The 32-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned32 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ INT8 Count;
+ UINT32 ValueTemp;
+
+ ASSERT (Buffer != NULL);
+ for (Count = 0, ValueTemp = Value; Count < sizeof (UINT32) ; Count ++) {
+ *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
+ ValueTemp = ValueTemp >> 8;
+ }
+ return Value;
+}
+
+/**
+ Reads a 64-bit value from memory that may be unaligned.
+
+ This function returns the 64-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 64-bit value that may be unaligned.
+
+ @return The 64-bit value read from Buffer.
+
+**/
+UINT64
+EFIAPI
+ReadUnaligned64 (
+ IN CONST UINT64 *Buffer
+ )
+{
+ UINT64 Value;
+ INT8 Count;
+
+ ASSERT (Buffer != NULL);
+ for (Count = sizeof (UINT64) - 1, Value = 0; Count >= 0 ; Count --) {
+ Value = Value << 8;
+ Value |= *((UINT8*)Buffer + Count);
+ }
+ return Value;
+}
+
+/**
+ Writes a 64-bit value to memory that may be unaligned.
+
+ This function writes the 64-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 64-bit value that may be unaligned.
+ @param Value The 64-bit value to write to Buffer.
+
+ @return The 64-bit value to write to Buffer.
+
+**/
+UINT64
+EFIAPI
+WriteUnaligned64 (
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
+ )
+{
+ INT8 Count;
+ UINT64 ValueTemp;
+
+ ASSERT (Buffer != NULL);
+ for (Count = 0, ValueTemp = Value; Count < sizeof (UINT64) ; Count ++) {
+ *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
+ ValueTemp = ValueTemp >> 8;
+ }
+ return Value;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (6 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-10-01 8:44 ` [edk2-devel] " Philippe Mathieu-Daudé
2019-09-23 0:31 ` Abner Chang
` (36 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Implement RISC-V cache maintenance functions in
BaseCacheMaintenanceLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../BaseCacheMaintenanceLib.inf | 4 +
.../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++
2 files changed, 254 insertions(+)
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index ec7feec..d9bfa04 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -6,6 +6,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +42,9 @@
[Sources.AARCH64]
ArmCache.c
+[Sources.RISCV64]
+ RiscVCache.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
new file mode 100644
index 0000000..d8e4665
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -0,0 +1,250 @@
+/** @file
+ RISC-V specific functionality for cache.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ RiscVInvalidateInstCacheAsm ();
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ RiscVInvalidateDataCacheAsm ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (7 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 23:30 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
` (35 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Implement RISC-V cache maintenance functions in
BaseCacheMaintenanceLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../BaseCacheMaintenanceLib.inf | 4 +
.../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++
2 files changed, 254 insertions(+)
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index ec7feec..d9bfa04 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -6,6 +6,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +42,9 @@
[Sources.AARCH64]
ArmCache.c
+[Sources.RISCV64]
+ RiscVCache.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
new file mode 100644
index 0000000..d8e4665
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -0,0 +1,250 @@
+/** @file
+ RISC-V specific functionality for cache.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ RiscVInvalidateInstCacheAsm ();
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ RiscVInvalidateDataCacheAsm ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ return Address;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (8 preceding siblings ...)
2019-09-23 0:31 ` Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 23:39 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
` (34 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RISC-V MMIO library instance. RISC-V only supports memory map I/O.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
2 files changed, 607 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 457cce9..fbb568e 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -2,13 +2,14 @@
# Instance of I/O Library using compiler intrinsics.
#
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
-# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
+# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated into MMIO requests.
# MMIO requests are forwarded directly to memory. For EBC, I/O port requests
# ASSERT().
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
@@ -55,6 +56,9 @@
[Sources.AARCH64]
IoLibArm.c
+[Sources.RISCV64]
+ IoLibRiscV.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
new file mode 100644
index 0000000..789928b
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
@@ -0,0 +1,601 @@
+/** @file
+ Common I/O Library routines for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "BaseIoLibIntrinsicInternal.h"
+
+/**
+ Reads an 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioRead8 (
+ IN UINTN Address
+ )
+{
+ return *(volatile UINT8*)Address;
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT8
+EFIAPI
+MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ *(volatile UINT8 *)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioRead16 (
+ IN UINTN Address
+ )
+{
+ return *(volatile UINT16 *)Address;
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT16
+EFIAPI
+MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ *(volatile UINT16 *)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioRead32 (
+ IN UINTN Address
+ )
+{
+ return *(volatile UINT32 *)Address;
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The valu return *(volatile UINT8*)Address;
+ to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT32
+EFIAPI
+MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ *(volatile UINT32 *)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioRead64 (
+ IN UINTN Address
+ )
+{
+ return *(volatile UINT64 *)Address;
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ *(volatile UINT64 *)Address = Value;
+ return Value;
+}
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoRead64 (
+ IN UINTN Port
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 64-bit I/O port.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
+ ASSERT (FALSE);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (9 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 23:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
` (33 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Support RISC-V image relocation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++++++++++++++++++
5 files changed, 152 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
index 07bb62f..97e0ff4 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
@@ -1,6 +1,6 @@
/** @file
Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
- only supports relocating IA32, x64, IPF, and EBC images.
+ only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
Caution: This file requires additional review when modified.
This library will have external input - PE/COFF image.
@@ -17,6 +17,7 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index 395c140..b190494 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -3,6 +3,7 @@
# The IPF version library supports loading IPF and EBC PE/COFF image.
# The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+# The RISC-V version library support loading RISC-V images.
#
# Caution: This module requires additional review when modified.
# This library will have external input - PE/COFF image.
@@ -11,6 +12,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +43,9 @@
[Sources.ARM]
Arm/PeCoffLoaderEx.c
+[Sources.RISCV64]
+ RiscV/PeCoffLoaderEx.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
index b0ea702..8616ca3 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
@@ -4,6 +4,7 @@
// The IPF version library supports loading IPF and EBC PE/COFF image.
// The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
// The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
//
// Caution: This module requires additional review when modified.
// This library will have external input - PE/COFF image.
@@ -12,6 +13,7 @@
//
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index b74277f..9c33703 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -2,6 +2,7 @@
Declaration of internal functions in PE/COFF Lib.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
new file mode 100644
index 0000000..8eb37f9
--- /dev/null
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -0,0 +1,142 @@
+/** @file
+ PE/Coff loader for RISC-V PE image
+
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BasePeCoffLibInternals.h"
+#include <Library/BaseLib.h>
+
+//
+// RISC-V definition.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+
+/**
+ Performs an RISC-V specific relocation fixup and is a no-op on
+ other instruction sets.
+ RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
+ types. We have to know the lower 12-bit fixup first then we can deal
+ carry over on high 20-bit fixup. So we log the high 20-bit in
+ FixupData.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 *RiscVHi20Fixup;
+
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ break;
+
+ default:
+ return RETURN_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ @param Machine Machine type from the PE Header.
+
+ @return TRUE if this PE/COFF loader can load the image
+
+**/
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+{
+ if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine == IMAGE_FILE_MACHINE_RISCV64)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Performs an Itanium-based specific re-relocation fixup and is a no-op on other
+ instruction sets. This is used to re-relocated the image into the EFI virtual
+ space for runtime calls.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeHotRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (10 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 23:47 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
` (32 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Implement RISC-V CPU related functions in BaseCpuLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++-
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++--
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++
3 files changed, 27 insertions(+), 3 deletions(-)
create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index a7cb381..a95d8a0 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -7,6 +7,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,7 +25,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources.IA32]
@@ -59,6 +60,9 @@
AArch64/CpuFlushTlb.asm | MSFT
AArch64/CpuSleep.asm | MSFT
+[Sources.RISCV64]
+ RiscV/Cpu.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
index fc95cda..85d56ce 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
@@ -1,12 +1,13 @@
// /** @file
// Instance of CPU Library for various architecture.
//
-// CPU Library implemented using ASM functions for IA-32 and X64,
+// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
// PAL CALLs for IPF, and empty functions for EBC.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -15,5 +16,5 @@
#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
-#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC."
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
new file mode 100644
index 0000000..703b1e8
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
@@ -0,0 +1,19 @@
+//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+ wfi
+ ret
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (11 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-27 0:19 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
` (31 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../BaseSynchronizationLib.inf | 6 +
.../RiscV64/Synchronization.c | 183 +++++++++++++++++++++
.../RiscV64/SynchronizationAsm.S | 78 +++++++++
3 files changed, 267 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19..c16ef9d 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -78,6 +79,11 @@
AArch64/Synchronization.S | GCC
AArch64/Synchronization.asm | MSFT
+[Sources.RISCV64]
+ Synchronization.c
+ RiscV64/Synchronization.c | GCC
+ RiscV64/SynchronizationAsm.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
new file mode 100644
index 0000000..e210b74
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
@@ -0,0 +1,183 @@
+/** @file
+ Implementation of synchronization functions on RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+
+UINT32
+SyncCompareExchange32 (
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
+);
+
+UINT64
+SyncCompareExchange64 (
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+);
+
+UINT32
+SyncSyncIncrement32 (
+ IN volatile UINT32 *Value
+ );
+
+UINT32
+SyncSyncDecrement32 (
+ IN volatile UINT32 *Value
+ );
+
+/**
+ Performs an atomic compare exchange operation on a 16-bit
+ unsigned integer.
+
+ Performs an atomic compare exchange operation on the 16-bit
+ unsigned integer specified by Value. If Value is equal to
+ CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to
+ CompareValue, then Value is returned. The compare exchange
+ operation must be performed using MP safe mechanisms.
+
+ @param Value A pointer to the 16-bit value for the
+ compare exchange operation.
+ @param CompareValue 16-bit value used in compare operation.
+ @param ExchangeValue 16-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+ IN volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO operation\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Performs an atomic compare exchange operation on a 32-bit
+ unsigned integer.
+
+ Performs an atomic compare exchange operation on the 32-bit
+ unsigned integer specified by Value. If Value is equal to
+ CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to
+ CompareValue, then Value is returned. The compare exchange
+ operation must be performed using MP safe mechanisms.
+
+ @param Value A pointer to the 32-bit value for the
+ compare exchange operation.
+ @param CompareValue 32-bit value used in compare operation.
+ @param ExchangeValue 32-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
+ )
+{
+
+ if (((UINTN)Value % sizeof (UINT32)) != 0) {
+ DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ }
+ return SyncCompareExchange32(Value, CompareValue, ExchangeValue);
+}
+
+/**
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
+ The compare exchange operation must be performed using MP safe mechanisms.
+
+ @param Value A pointer to the 64-bit value for the compare exchange
+ operation.
+ @param CompareValue 64-bit value used in compare operation.
+ @param ExchangeValue 64-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+{
+ if (((UINTN)Value % sizeof (UINT64)) != 0) {
+ DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ }
+ return SyncCompareExchange64 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+ Performs an atomic increment of an 32-bit unsigned integer.
+
+ Performs an atomic increment of the 32-bit unsigned integer specified by
+ Value and returns the incremented value. The increment operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param Value A pointer to the 32-bit value to increment.
+
+ @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+ IN volatile UINT32 *Value
+ )
+{
+ if (((UINTN)Value % sizeof (UINT32)) != 0) {
+ DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ }
+ return SyncSyncIncrement32 (Value);
+}
+
+/**
+ Performs an atomic decrement of an 32-bit unsigned integer.
+
+ Performs an atomic decrement of the 32-bit unsigned integer specified by
+ Value and returns the decrement value. The decrement operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param Value A pointer to the 32-bit value to decrement.
+
+ @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+ IN volatile UINT32 *Value
+ )
+{
+ if (((UINTN)Value % sizeof (UINT32)) != 0) {
+ DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
+ ASSERT (FALSE);
+ }
+ return SyncSyncDecrement32 (Value);
+}
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
new file mode 100644
index 0000000..943e274
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(SyncCompareExchange32)
+.global ASM_PFX(SyncCompareExchange64)
+.global ASM_PFX(SyncSyncIncrement32)
+.global ASM_PFX(SyncSyncDecrement32)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange32):
+ lr.w a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.w a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit:
+ mv a0, a3
+ ret
+
+.global ASM_PFX(SyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+ lr.d a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.d a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit2:
+ mv a0, a3
+ ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (SyncSyncIncrement32):
+ li a1, 1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (SyncSyncDecrement32):
+ li a1, -1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (12 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
` (30 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISCV64 Arch.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdeModulePkg/Logo/Logo.inf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
index 0182025..243748c 100644
--- a/MdeModulePkg/Logo/Logo.inf
+++ b/MdeModulePkg/Logo/Logo.inf
@@ -19,7 +19,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Binaries]
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (13 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
` (29 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISCV64 Arch.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
NetworkPkg/Network.dsc.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
index c7f4328..b484f9b 100644
--- a/NetworkPkg/Network.dsc.inc
+++ b/NetworkPkg/Network.dsc.inc
@@ -34,7 +34,7 @@
!include NetworkPkg/NetworkComponents.dsc.inc
!else
-[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
+[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64]
!include NetworkPkg/NetworkComponents.dsc.inc
!endif
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (14 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 18:31 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
` (28 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 +++++++++++++++++++++++++++
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++
3 files changed, 217 insertions(+)
create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h
new file mode 100644
index 0000000..c84d599
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVCpuLib.h
@@ -0,0 +1,68 @@
+/** @file
+ RISC-V CPU library definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _RISCV_CPU_LIB_H_
+#define _RISCV_CPU_LIB_H_
+
+#include "RiscV.h"
+
+/**
+ RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+ VOID
+ );
+
+VOID
+RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+
+UINT32
+RiscVGetScratch (VOID);
+
+UINT32
+RiscVGetTrapCause (VOID);
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+UINT64
+RiscVReadMachineIE(VOID);
+
+UINT64
+RiscVReadMachineIP(VOID);
+
+UINT64
+RiscVReadMachineStatus(VOID);
+
+VOID
+RiscVWriteMachineStatus(UINT64);
+
+UINT64
+RiscVReadMachineTvec(VOID);
+
+UINT64
+RiscVReadMisa (VOID);
+
+UINT64
+RiscVReadMVendorId (VOID);
+
+UINT64
+RiscVReadMArchId (VOID);
+
+UINT64
+RiscVReadMImplId (VOID);
+
+#endif
diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
new file mode 100644
index 0000000..f372397
--- /dev/null
+++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
@@ -0,0 +1,115 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscV.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVSetScratch)
+.global ASM_PFX(RiscVGetScratch)
+.global ASM_PFX(RiscVGetMachineTrapCause)
+.global ASM_PFX(RiscVReadMachineIE)
+.global ASM_PFX(RiscVReadMachineIP)
+.global ASM_PFX(RiscVReadMachineStatus)
+.global ASM_PFX(RiscVWriteMachineStatus)
+.global ASM_PFX(RiscVReadMachineTvec)
+.global ASM_PFX(RiscVReadMisa)
+.global ASM_PFX(RiscVReadMVendorId)
+.global ASM_PFX(RiscVReadMArchId)
+.global ASM_PFX(RiscVReadMImplId)
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_PFX (RiscVSetScratch):
+ csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+ ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_PFX (RiscVGetScratch):
+ csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+ ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_PFX (RiscVGetMachineTrapCause):
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ ret
+
+//
+// Get machine interrupt enable
+//
+ASM_PFX (RiscVReadMachineIE):
+ csrr a0, RISCV_CSR_MACHINE_MIE
+ ret
+
+//
+// Get machine interrupt pending
+//
+ASM_PFX (RiscVReadMachineIP):
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_PFX(RiscVReadMachineStatus):
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_PFX(RiscVWriteMachineStatus):
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_PFX(RiscVReadMachineTvec):
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_PFX(RiscVReadMisa):
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_PFX(RiscVReadMVendorId):
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
+ ret
+
+//
+// Read machine architecture ID
+//
+ASM_PFX(RiscVReadMArchId):
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_PFX(RiscVReadMImplId):
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
new file mode 100644
index 0000000..fc9131b
--- /dev/null
+++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V RV64 CPU library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCpuLib
+ FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCpuLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Cpu.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (15 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 19:15 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
` (27 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Initial RISC-V Supervisor Mode trap handler
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RiscVExceptionLib/CpuExceptionHandler.S | 88 ++++++++++
.../CpuExceptionHandlerDxeLib.inf | 42 +++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++++++++++++++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 ++
4 files changed, 325 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
new file mode 100644
index 0000000..cffe485
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
@@ -0,0 +1,88 @@
+/** @file
+ RISC-V Processor supervisor mode trap handler
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <RiscV.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _strap_handler
+_strap_handler:
+ addi sp, sp, -34*8
+ /* Save all general regisers except SP and T0 */
+ sd ra, 1*8(sp)
+ sd gp, 2*8(sp)
+ sd tp, 3*8(sp)
+ sd t1, 4*8(sp)
+ sd t2, 5*8(sp)
+ sd s0, 6*8(sp)
+ sd s1, 7*8(sp)
+ sd a0, 8*8(sp)
+ sd a1, 9*8(sp)
+ sd a2, 10*8(sp)
+ sd a3, 11*8(sp)
+ sd a4, 12*8(sp)
+ sd a5, 13*8(sp)
+ sd a6, 14*8(sp)
+ sd a7, 15*8(sp)
+ sd s2, 16*8(sp)
+ sd s3, 17*8(sp)
+ sd s4, 18*8(sp)
+ sd s5, 19*8(sp)
+ sd s6, 20*8(sp)
+ sd s7, 21*8(sp)
+ sd s8, 22*8(sp)
+ sd s9, 23*8(sp)
+ sd s10, 24*8(sp)
+ sd s11, 25*8(sp)
+ sd t3, 26*8(sp)
+ sd t4, 27*8(sp)
+ sd t5, 28*8(sp)
+ sd t6, 29*8(sp)
+
+ /* Call C routine */
+ call RiscVSupervisorModeTrapHandler
+
+ /* Restore all general regisers except SP and T0 */
+ ld ra, 1*8(sp)
+ ld gp, 2*8(sp)
+ ld tp, 3*8(sp)
+ ld t1, 4*8(sp)
+ ld t2, 5*8(sp)
+ ld s0, 6*8(sp)
+ ld s1, 7*8(sp)
+ ld a0, 8*8(sp)
+ ld a1, 9*8(sp)
+ ld a2, 10*8(sp)
+ ld a3, 11*8(sp)
+ ld a4, 12*8(sp)
+ ld a5, 13*8(sp)
+ ld a6, 14*8(sp)
+ ld a7, 15*8(sp)
+ ld s2, 16*8(sp)
+ ld s3, 17*8(sp)
+ ld s4, 18*8(sp)
+ ld s5, 19*8(sp)
+ ld s6, 20*8(sp)
+ ld s7, 21*8(sp)
+ ld s8, 22*8(sp)
+ ld s9, 23*8(sp)
+ ld s10, 24*8(sp)
+ ld s11, 25*8(sp)
+ ld t3, 26*8(sp)
+ ld t4, 27*8(sp)
+ ld t5, 28*8(sp)
+ ld t6, 29*8(sp)
+ addi sp, sp, 34*8
+ sret
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
new file mode 100644
index 0000000..e5871dc
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
@@ -0,0 +1,42 @@
+## @file
+# RISC-V CPU Exception Handler Library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuExceptionHandlerLib
+ MODULE_UNI_FILE = CpuExceptionHandlerLib.uni
+ FILE_GUID = 16309FCF-E900-459C-B071-052118394D11
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuExceptionHandlerLib
+ CONSTRUCTOR = CpuExceptionHandlerLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources.RISCV64]
+ CpuExceptionHandler.S
+
+[Sources.common]
+ CpuExceptionHandlerLib.c
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ BaseLib
+ DebugLib
+ RiscVCpuLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
new file mode 100644
index 0000000..8c75be0
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -0,0 +1,182 @@
+/** @file
+ RISC-V Exception Handler library implementition.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_types.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+
+
+extern void _strap_handler(void);
+EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2];
+/**
+ Initializes all CPU exceptions entries and provides the default exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
+ with default exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
+ with default interrupt/exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Registers a function to be called from the processor interrupt handler.
+
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+ NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+ InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+ @param[in] InterruptType Defines which interrupt or exception to hook.
+ @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
+ or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+
+ DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler));
+ gInterruptHandlers[InterruptType] = InterruptHandler;
+ return EFI_SUCCESS;
+}
+/**
+ Machine mode trap handler.
+
+**/
+VOID
+RiscVSupervisorModeTrapHandler (
+ VOID
+ )
+{
+ EFI_SYSTEM_CONTEXT RiscVSystemContext;
+
+ //
+ // Check scasue register.
+ //
+ if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) {
+ gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
+ }
+}
+
+/**
+ Initializes all CPU exceptions entries with optional extra initializations.
+
+ By default, this method should include all functionalities implemented by
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
+ This could be done by calling InitializeCpuExceptionHandlers() directly
+ in this method besides the extra works.
+
+ InitData is optional and its use and content are processor arch dependent.
+ The typical usage of it is to convey resources which have to be reserved
+ elsewhere and are necessary for the extra initializations of exception.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+ @param[in] InitData Pointer to data optional for extra initializations
+ of exception.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid
+ content.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlersEx (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ )
+{
+ return InitializeCpuExceptionHandlers (VectorInfo);
+}
+
+/**
+ The constructor function to initial interrupt handlers in
+ RISCV_MACHINE_MODE_CONTEXT.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The destructor completed successfully.
+ @retval Other value The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuExceptionHandlerLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Set Superviosr mode trap handler.
+ //
+ csr_write(CSR_STVEC, _strap_handler);
+
+ return EFI_SUCCESS;
+}
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
new file mode 100644
index 0000000..00cca22
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys."
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys."
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (16 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 19:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
` (26 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Timer library for RISC-V
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++++++++++++++++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +++
RiscVPkg/RiscVPkg.dec | 9 +
4 files changed, 259 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
new file mode 100644
index 0000000..af27049
--- /dev/null
+++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V Timer Library Instance.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = BaseRiscVTimerLib
+ FILE_GUID = FB648CF5-91BE-4737-9023-FD807AC6D96D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+[Sources]
+ RiscVTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
new file mode 100644
index 0000000..acb8c77
--- /dev/null
+++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -0,0 +1,195 @@
+/** @file
+ RISC-V instance of Timer Library.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <RiscVTimerLib.h>
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+ Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks = RiscVReadMachineTimer () + Delay;
+ Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+ while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000u
+ )
+ );
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000000u
+ )
+ );
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)RiscVReadMachineTimer ();
+}
+
+/**return
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = 32 - 1;
+ }
+
+ return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 NanoSeconds;
+ UINT32 Remainder;
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u);
+
+ //
+ // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+ // will not overflow 64-bit.
+ //
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
+
+ return NanoSeconds;
+}
diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
new file mode 100644
index 0000000..bac3a70
--- /dev/null
+++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
@@ -0,0 +1,21 @@
+/** @file
+ RISC-V timer library definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef _RISCV_TIMER_LIB_INTERNAL_H_
+#define _RISCV_TIMER_LIB_INTERNAL_H_
+
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <Library/RiscVCpuLib.h>
+
+#endif // _RISCV_TIMER_LIB_INTERNAL_H_
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index 74314e8..a91392f 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -23,5 +23,14 @@
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
+[PcdsFixedAtBuild]
+ #
+ # 1000000000
+ # PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
+ # PcdRiscVMachineTimerFrequencyInHerz
+ #
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UINT64|0x00001010
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011
+
[UserExtensions.TianoCore."ExtraFiles"]
RiscVPkgExtra.uni
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (17 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 20:03 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
` (25 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
EDK2 RISC-V OpenSBI library which pull in external source files under
RiscVPkg/opensbi to the build process.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000..640ffba
--- /dev/null
+++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,52 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiLib
+ FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiLib
+
+[Sources]
+ ../../opensbi/lib/sbi/riscv_asm.c
+ ../../opensbi/lib/sbi/riscv_atomic.c
+ ../../opensbi/lib/sbi/riscv_hardfp.S
+ ../../opensbi/lib/sbi/riscv_locks.c
+ ../../opensbi/lib/sbi/riscv_unpriv.c
+ ../../opensbi/lib/sbi/sbi_console.c
+ ../../opensbi/lib/sbi/sbi_ecall.c
+ ../../opensbi/lib/sbi/sbi_emulate_csr.c
+ ../../opensbi/lib/sbi/sbi_fifo.c
+ ../../opensbi/lib/sbi/sbi_hart.c
+ ../../opensbi/lib/sbi/sbi_illegal_insn.c
+ ../../opensbi/lib/sbi/sbi_init.c
+ ../../opensbi/lib/sbi/sbi_ipi.c
+ ../../opensbi/lib/sbi/sbi_misaligned_ldst.c
+ ../../opensbi/lib/sbi/sbi_scratch.c
+ ../../opensbi/lib/sbi/sbi_string.c
+ ../../opensbi/lib/sbi/sbi_system.c
+ ../../opensbi/lib/sbi/sbi_timer.c
+ ../../opensbi/lib/sbi/sbi_tlb.c
+ ../../opensbi/lib/sbi/sbi_trap.c
+ ../../opensbi/lib/utils/sys/clint.c
+ ../../opensbi/lib/utils/irqchip/plic.c
+ ../../opensbi/lib/utils/serial/sifive-uart.c
+ ../../opensbi/lib/utils/serial/uart8250.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (18 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 20:15 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
` (24 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE
phase.
RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI
interface.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++
.../RiscVDxeIplHandoffLib.inf | 32 +++++++
.../RiscVDxeIplHandoffOpenSbiLib.c | 102 +++++++++++++++++++++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++
4 files changed, 208 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
new file mode 100644
index 0000000..211b4e8
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
@@ -0,0 +1,41 @@
+/** @file
+ RISC-V platform level DXE core hand off library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
new file mode 100644
index 0000000..986db1d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
new file mode 100644
index 0000000..c640fd2
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
@@ -0,0 +1,102 @@
+/** @file
+ RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_init.h>
+#include <sbi/riscv_encoding.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVPlatformDxeIpl.h>
+
+/**
+ RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
+ This function is executed in RISC-V Supervisor mode.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVDxeIplHandoffOpenSbiHandler (
+ IN UINTN HardId,
+ IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
+ )
+{
+ DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n"));
+
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
+ ThisSwitchContext->HobList.Raw,
+ NULL,
+ ThisSwitchContext->TopOfStack
+ );
+
+ //
+ // Shold never came back.
+ //
+ __builtin_unreachable();
+}
+
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ struct sbi_scratch *ThisScratch;
+ OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
+
+ DEBUG ((DEBUG_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n"));
+ //
+ // Setup next address in OpenSBI scratch
+ //
+ OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
+ OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
+ OpenSbiSwitchModeContext.HobList = HobList;
+ OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
+ ThisScratch = sbi_scratch_thishart_ptr ();
+ ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext;
+ ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler;
+ ThisScratch->next_mode = PRV_S;
+
+ DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
+ DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack));
+ DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList));
+ DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
+ sbi_init (ThisScratch);
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
new file mode 100644
index 0000000..262071d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffOpenSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (19 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 20:31 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
` (23 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Implementation of RISC-V platform level DxeIPL
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++-
MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 ++++++++++++++++++++++
RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 +++++++++++++
3 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 98bc17f..5532323 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -7,6 +7,7 @@
#
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
#
[Sources]
@@ -49,6 +50,9 @@
[Sources.ARM, Sources.AARCH64]
Arm/DxeLoadFunc.c
+[Sources.RISCV64]
+ RiscV64/DxeLoadFunc.c
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
@@ -56,6 +60,9 @@
[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec
+[Packages.RISCV64]
+ RiscVPkg/RiscVPkg.dec
+
[LibraryClasses]
PcdLib
MemoryAllocationLib
@@ -75,6 +82,10 @@
[LibraryClasses.ARM, LibraryClasses.AARCH64]
ArmMmuLib
+[LibraryClasses.RISCV64]
+ RiscVPlatformDxeIplLib
+ RiscVOpensbiLib
+
[Ppis]
gEfiDxeIplPpiGuid ## PRODUCES
gEfiPeiDecompressPpiGuid ## PRODUCES
diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
new file mode 100644
index 0000000..d3c7f9d
--- /dev/null
+++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
@@ -0,0 +1,71 @@
+/** @file
+ RISC-V specific functionality for DxeLoad.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "DxeIpl.h"
+#include "Library/RiscVPlatformDxeIpl.h"
+
+typedef
+VOID*
+(EFIAPI *DXEENTRYPOINT) (
+ IN VOID *HobStart
+ );
+
+/**
+ Transfers control to DxeCore.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+HandOffToDxeCore (
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ VOID *BaseOfStack;
+ VOID *TopOfStack;
+ EFI_STATUS Status;
+ //
+ //
+ // Allocate 128KB for the Stack
+ //
+ BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
+ ASSERT (BaseOfStack != NULL);
+
+ //
+ // Compute the top of the stack we were allocated. Pre-allocate a UINTN
+ // for safety.
+ //
+ TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+ TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
+
+ //
+ // End of PEI phase signal
+ //
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
+ //
+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
+
+ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack));
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList);
+}
+
diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
new file mode 100644
index 0000000..4763397
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file of RISC-V platform DXE IPL
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _RISC_V_PLATFORM_DXEIPL_H_
+#define _RISC_V_PLATFORM_DXEIPL_H_
+
+typedef struct {
+ VOID *TopOfStack;
+ VOID *BaseOfStack;
+ EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;
+ EFI_PEI_HOB_POINTERS HobList;
+} OPENSBI_SWITCH_MODE_CONTEXT;
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ );
+#endif
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (20 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 20:54 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
` (22 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Implementation of RISC-V PEI Service Table Pointer library using
RISC-V OpenSbi.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiServicesTablePointerLibOpenSbi.inf | 38 +++++++
.../PeiServicesTablePointerLibOpenSbi.uni | 23 ++++
.../PeiServicesTablePointerOpenSbi.c | 121 +++++++++++++++++++++
3 files changed, 182 insertions(+)
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
new file mode 100644
index 0000000..0b029ae
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -0,0 +1,38 @@
+## @file
+# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+#
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the
+# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PeiServicesTablePointerLibOpenSbi
+ MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni
+ FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
+
+ CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiServicesTablePointerOpenSbi.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
new file mode 100644
index 0000000..f6fad8b
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
@@ -0,0 +1,23 @@
+// /** @file
+//
+// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+//
+// PEI Services Table Pointer Library implementation that retrieves a pointer to the
+// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
+
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
new file mode 100644
index 0000000..915964f
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -0,0 +1,121 @@
+/** @file
+ PEI Services Table Pointer Library.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/SbiFirmwareContext.h>
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+ Pre-EFI Initialization Core Interface Specification.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
+
+ DEBUG ((DEBUG_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Context at 0x%x\n",
+ PeiServicesTablePointer,
+ ThisSbiPlatform->firmware_context
+ ));
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
+}
+
+/**
+ The constructor function caches the pointer to PEI services.
+
+ The constructor function caches the pointer to PEI services.
+ It will always return EFI_SUCCESS.
+
+ @param FileHandle The handle of FFS header the loaded driver.
+ @param PeiServices The pointer to the PEI services.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesTablePointerLibOpenSbiConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ SetPeiServicesTablePointer (PeiServices);
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+ a dedicated CPU register. This means that there is no memory storage
+ associated with storing the PEI Services Table pointer, so no additional
+ migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ )
+{
+ //
+ // PEI Services Table pointer is cached in the global variable. No additional
+ // migration actions are required.
+ //
+ return;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (21 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 20:56 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
` (21 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
NULL instance of RISC-V Platform Temporary Memory library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/RiscVPlatformTempMemoryInitLib.h | 17 +++++++++++
.../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++++++++++++++++++++++
.../Riscv64/TempMemInit.S | 26 +++++++++++++++++
3 files changed, 77 insertions(+)
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
new file mode 100644
index 0000000..11dfcfb
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
@@ -0,0 +1,17 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _RISCV_PLATFORM_TEMP_MEM_LIB_H_
+#define _RISCV_PLATFORM_TEMP_MEM_LIB_H_
+
+#include "RiscV.h"
+
+VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID);
+#endif
diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
new file mode 100644
index 0000000..12fa497
--- /dev/null
+++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V platform temporary memory library.
+#
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTempMemoryInitLibNull
+ FILE_GUID = 67294857-C0F8-4ACB-8237-D91FE506B710
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTempMemoryInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Riscv64/TempMemInit.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+
diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
new file mode 100644
index 0000000..61a9923
--- /dev/null
+++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
@@ -0,0 +1,26 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V RiscVPlatformTemporaryMemInit.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVPlatformTemporaryMemInit)
+
+//
+// @retval a0 Temporary memory base.
+// a1 Temporary memory size.
+//
+ASM_PFX(RiscVPlatformTemporaryMemInit):
+ li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
+ li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (22 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 21:11 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
` (20 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V
platform level timer library.
Due to RISC-V timer CSR is platform implementation specific,
RISC-V CPU DXE driver invokes platform level timer library
to access to timer CSRs.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 ++++++++++++++++++++++++++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++++++++++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 ++
| 14 ++
5 files changed, 607 insertions(+)
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
new file mode 100644
index 0000000..30d1115
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
@@ -0,0 +1,318 @@
+/** @file
+ RISC-V CPU DXE driver.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuDxe.h"
+
+//
+// Global Variables
+//
+BOOLEAN InterruptState = FALSE;
+EFI_HANDLE mCpuHandle = NULL;
+BOOLEAN mIsFlushingGCD;
+
+EFI_CPU_ARCH_PROTOCOL gCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 1, // NumberOfTimers
+ 4 // DmaBufferAlignment
+};
+
+//
+// CPU Arch Protocol Functions
+//
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+ InterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ DisableInterrupts ();
+ InterruptState = FALSE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = InterruptState;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
+}
+
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ if (TimerValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (TimerIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ if (TimerPeriod != NULL) {
+ *TimerPeriod = DivU64x32 (
+ 1000000000000000u,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ );
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
+
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ Attributes specified an illegal combination of attributes that
+ cannot be set together.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a:Set memory attributes not supported yet\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpu (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Machine mode handler is initiated in CpuExceptionHandlerLibConstructor in
+ // CpuExecptionHandlerLib.
+ //
+
+ //
+ // Make sure interrupts are disabled
+ //
+ DisableInterrupts ();
+
+ //
+ // Install CPU Architectural Protocol
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid, &gCpu,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
new file mode 100644
index 0000000..e423fae
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
@@ -0,0 +1,206 @@
+/** @file
+ RISC-V CPU DXE module header file.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CPU_DXE_H_
+#define _CPU_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/TimerLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ );
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ );
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ );
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ );
+
+/**
+ Set memory cacheability attributes for given range of memeory.
+
+ @param This Protocol instance structure
+ @param BaseAddress Specifies the start address of the
+ memory range
+ @param Length Specifies the length of the memory range
+ @param Attributes The memory cacheability for the memory range
+
+ @retval EFI_SUCCESS If the cacheability of that memory range is
+ set successfully
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,
+ such as Length = 0
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif
+
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
new file mode 100644
index 0000000..1931f45
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
@@ -0,0 +1,56 @@
+## @file
+# RISC-V CPU DXE module.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuDxe
+ MODULE_UNI_FILE = CpuDxe.uni
+ FILE_GUID = 1A1E4886-9517-440e-9FDE-3BE44CEE2136
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeCpu
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ CpuLib
+ DebugLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ CpuExceptionHandlerLib
+ TimerLib
+ SynchronizationLib
+ HobLib
+ ReportStatusCodeLib
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
+[Sources]
+ CpuDxe.c
+ CpuDxe.h
+
+[Protocols]
+ gEfiCpuArchProtocolGuid ## PRODUCES
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[Depex]
+ TRUE
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ CpuDxeExtra.uni
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
new file mode 100644
index 0000000..460141a
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V CPU Architecture Protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver installs CPU Architecture Protocol."
+
--git a/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
new file mode 100644
index 0000000..6f819f0
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
@@ -0,0 +1,14 @@
+// /** @file
+// CpuDxe Localized Strings and Content
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V Architectural DXE Driver"
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (23 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:09 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
` (19 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
BaseTools changes for building EDK2 RISC-V platform.
The changes made to build_rule.template is to avoid build errors
cause by GCC711RISCV tool chain.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Conf/build_rule.template | 62 ++---
BaseTools/Conf/tools_def.template | 64 ++++-
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
.../Source/C/Include/IndustryStandard/PeImage.h | 6 +
BaseTools/Source/Python/Common/DataType.py | 7 +-
10 files changed, 659 insertions(+), 45 deletions(-)
diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
index db06d3a..fab3926 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -1,6 +1,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -145,14 +146,6 @@
<Command.GCC, Command.RVCT>
"$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src}
-[C-Header-File]
- <InputFile>
- *.h, *.H
-
- <OutputFile>
-
- <Command>
-
[Assembly-Code-File.COMMON.COMMON]
<InputFile.MSFT, InputFile.INTEL, InputFile.RVCT>
?.asm, ?.Asm, ?.ASM
@@ -266,10 +259,10 @@
<Command.GCC>
$(RM) ${dst}
"$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST)
-
+
<Command.RVCT>
"$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST)
-
+
<Command.RVCTCYGWIN>
# $(OBJECT_FILES_LIST) has wrong paths for cygwin
"$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES)
@@ -304,8 +297,8 @@
<Command.XCODE>
"$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
-
-
+
+
[Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64, Static-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM]
<InputFile>
*.lib
@@ -321,6 +314,21 @@
"$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
+[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32]
+ <InputFile>
+ *.lib
+
+ <ExtraDependency>
+ $(MAKE_FILE)
+
+ <OutputFile>
+ $(DEBUG_DIR)(+)$(MODULE_NAME).dll
+
+ <Command.GCC>
+ "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
+ "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
+
+
[Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION]
<InputFile>
*.lib
@@ -346,8 +354,8 @@
<Command.XCODE>
"$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
-
-
+
+
[Dynamic-Library-File]
<InputFile>
?.dll
@@ -360,7 +368,7 @@
$(CP) ${dst} $(DEBUG_DIR)
$(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
-$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
- -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
+ -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
<Command.GCC>
$(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
$(OBJCOPY) --strip-unneeded -R .eh_frame ${src}
@@ -375,7 +383,7 @@
$(CP) ${dst} $(DEBUG_DIR)
$(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
-$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
-
+
<Command.XCODE>
# tool to convert Mach-O to PE/COFF
"$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).pecoff
@@ -414,13 +422,13 @@
<Command.MSFT, Command.INTEL>
Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
"$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
- Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
+ Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
"$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
<Command.GCC>
Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
"$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
- Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
+ Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
"$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
[C-Code-File.AcpiTable]
@@ -462,14 +470,14 @@
"$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(CC_FLAGS) $(ASLCC_FLAGS) $(INC) ${src}
"$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
"$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(GENFW_FLAGS)
-
- <Command.XCODE>
+
+ <Command.XCODE>
"$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASLCC_FLAGS) $(INC) ${src}
"$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
"$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff
"$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff $(GENFW_FLAGS)
-
-
+
+
[Masm16-Code-File]
<InputFile>
?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16
@@ -492,14 +500,14 @@
Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
"$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
"$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) $(LIBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group
-
+
<Command.XCODE>
"$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
"$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
"$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${dst}
-
+
[Nasm-to-Binary-Code-File]
<InputFile>
@@ -635,8 +643,8 @@
<Command.GCC>
"$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
"$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
-
+
<Command.XCODE, Command.RVCT>
GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
-
-
+
+
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 8f0e6cb..54c3dc5 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -3,7 +3,7 @@
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -231,11 +231,12 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
# GCC5 -Linux,Windows- Requires:
-# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
+# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
# Optional:
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
+#
# CLANG35 -Linux,Windows- Requires:
# Clang v3.5 or later, and GNU binutils targeting aarch64-linux-gnu or arm-linux-gnueabi
# Optional:
@@ -1735,6 +1736,7 @@ DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386
DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
+DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv - B riscv64 --rename-section .data=.hii
DEFINE GCC48_ALL_CC_FLAGS = -g -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
DEFINE GCC48_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-n,-q,--gc-sections -z common-page-size=0x20
@@ -1806,6 +1808,21 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS = DEF(GCC49_ARM_ASLDLINK_FLAGS)
DEFINE GCC5_AARCH64_ASLDLINK_FLAGS = DEF(GCC49_AARCH64_ASLDLINK_FLAGS)
DEFINE GCC5_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -fno-lto
+DEFINE GCC5_RISCV_ALL_CC_FLAGS = -g -fshort-wchar -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -c -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
+DEFINE GCC5_RISCV_ALL_DLINK_COMMON = -nostdlib -n -q --gc-sections -z common-page-size=0x40
+DEFINE GCC5_RISCV_ALL_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS = --defsym=PECOFF_HEADER_SIZE=0x220 --script=$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds
+DEFINE GCC5_RISCV_ALL_ASM_FLAGS = -c -x assembler -imacros $(DEST_DIR_DEBUG)/AutoGen.h
+DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
+
+DEFINE GCC5_RISCV64_ARCH = rv64imafdc
+DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable
+DEFINE GCC5_RISCV32_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64
+DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -melf64lriscv --oformat=elf64-littleriscv --no-relax
+DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
+DEFINE GCC5_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
+
####################################################################################
#
# GCC 4.8 - This configuration is used to compile under Linux to produce
@@ -2247,6 +2264,49 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
NOOPT_GCC5_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -O0
NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
+###################################################################################
+####################################################################################
+#
+# GCC RISC-V This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC RISC-V tool chain
+#
+####################################################################################
+
+#*_GCC5_*_*_FAMILY = GCC
+
+#*_GCC5_*_MAKE_PATH = DEF(GCC49_IA32_PREFIX)make
+#*_GCC5_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
+#*_GCC5_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
+#*_GCC5_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+#*_GCC5_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
+#*_GCC5_*_APP_FLAGS =
+#*_GCC5_*_ASL_FLAGS = DEF(IASL_FLAGS)
+#*_GCC5_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+
+##################
+# GCC5 RISCV64 definitions
+##################
+*_GCC5_RISCV64_OBJCOPY_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
+*_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
+*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
+*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
+*_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_ASLCC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_ASLPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_RC_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
+
+*_GCC5_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC5_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
+*_GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS)
+*_GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) -save-temps
+*_GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV64_DLINK_FLAGS)
+*_GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV64_DLINK2_FLAGS)
+*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+*_GCC5_RISCV64_OBJCOPY_FLAGS =
+
####################################################################################
#
# CLANG35 - This configuration is used to compile under Linux to produce
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
index e7566b3..640f7a1 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -4,6 +4,7 @@
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage (
IN UINT64 Adjust
);
+RETURN_STATUS
+PeCoffLoaderRelocateRiscVImage (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ );
+
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@@ -174,7 +183,8 @@ Returns:
ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
+ ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
//
// There are two types of ARM images. Pure ARM and ARM/Thumb.
@@ -802,6 +812,9 @@ Returns:
case EFI_IMAGE_MACHINE_ARMT:
Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
break;
+ case EFI_IMAGE_MACHINE_RISCV64:
+ Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
+ break;
default:
Status = RETURN_UNSUPPORTED;
break;
diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
index e367836..36797d9 100644
--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
@@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
--*/
@@ -61,6 +62,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
+//
+// RISC-V definition.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+
+UINT32 *RiscVHi20Fixup = NULL;
+
RETURN_STATUS
PeCoffLoaderRelocateIa32Image (
IN UINT16 *Reloc,
@@ -93,6 +105,89 @@ Returns:
return RETURN_UNSUPPORTED;
}
+/*++
+
+Routine Description:
+
+ Performs an RISC-V specific relocation fixup
+
+Arguments:
+
+ Reloc - Pointer to the relocation record
+
+ Fixup - Pointer to the address to fix up
+
+ FixupData - Pointer to a buffer to log the fixups
+
+ Adjust - The offset to adjust the fixup
+
+Returns:
+
+ Status code
+
+--*/
+RETURN_STATUS
+PeCoffLoaderRelocateRiscVImage (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 OrgValue;
+
+ OrgValue = *(UINT32 *) Fixup;
+ OrgValue = OrgValue;
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ RiscVHi20Fixup = (UINT32 *) Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ RiscVHi20Fixup = NULL;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ RiscVHi20Fixup = NULL;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruction and
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 908740d..fdbdd42 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -4,6 +4,7 @@ This file contains the internal functions required to generate a Firmware Volume
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2016 HP Development Company, L.P.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000
BOOLEAN mArm = FALSE;
+BOOLEAN mRiscV = FALSE;
STATIC UINT32 MaxFfsAlignment = 0;
BOOLEAN VtfFileFlag = FALSE;
@@ -2274,6 +2276,104 @@ Returns:
}
EFI_STATUS
+UpdateRiscvResetVectorIfNeeded (
+ MEMORY_FILE *FvImage,
+ FV_INFO *FvInfo
+ )
+/*++
+
+Routine Description:
+ This parses the FV looking for SEC and patches that address into the
+ beginning of the FV header.
+
+ For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
+
+Arguments:
+ FvImage Memory file for the FV memory image/
+ FvInfo Information read from INF file.
+
+Returns:
+
+ EFI_SUCCESS Function Completed successfully.
+ EFI_ABORTED Error encountered.
+ EFI_INVALID_PARAMETER A required parameter was NULL.
+ EFI_NOT_FOUND PEI Core file not found.
+
+--*/
+{
+ EFI_STATUS Status;
+ UINT16 MachineType;
+ EFI_FILE_SECTION_POINTER SecPe32;
+ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
+
+ UINT32 bSecCore;
+ UINT32 tmp;
+
+
+ //
+ // Verify input parameters
+ //
+ if (FvImage == NULL || FvInfo == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize FV library
+ //
+ InitializeFvLib (FvImage->FileImage, FvInfo->Size);
+
+ //
+ // Find the Sec Core
+ //
+ Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
+ if(EFI_ERROR(Status)) {
+ printf("skip because Secutiry Core not found\n");
+ return EFI_SUCCESS;
+ }
+
+ DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
+
+ Status = GetCoreMachineType(SecPe32, &MachineType);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC core.");
+ return EFI_ABORTED;
+ }
+
+ if (MachineType != EFI_IMAGE_MACHINE_RISCV64) {
+ Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
+ return EFI_ABORTED;
+ }
+
+ Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
+ return EFI_ABORTED;
+ }
+
+ VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long long) SecCoreEntryAddress);
+ VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo->BaseAddress);
+ bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
+ VerboseMsg("offset = 0x%llX", bSecCore);
+
+ if(bSecCore > 0x0fffff) {
+ Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of start of the FV");
+ return EFI_ABORTED;
+ }
+
+ tmp = bSecCore;
+ bSecCore = 0;
+ //J-type
+ bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
+ bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
+ bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
+ bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
+ bSecCore |= 0x6F; //JAL opcode
+
+ memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
GetPe32Info (
IN UINT8 *Pe32,
OUT UINT32 *EntryPoint,
@@ -2365,7 +2465,8 @@ Returns:
// Verify machine type is supported
//
if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
- (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
+ (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
+ (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;
}
@@ -2808,7 +2909,8 @@ Returns:
Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad file between the last file and the VTF file.");
goto Finish;
}
- if (!mArm) {
+
+ if (!mArm && !mRiscV) {
//
// Update reset vector (SALE_ENTRY for IPF)
// Now for IA32 and IA64 platform, the fv which has bsf file must have the
@@ -2843,6 +2945,22 @@ Returns:
FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
}
+ if (mRiscV) {
+ //
+ // Update RISCV reset vector.
+ //
+ Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
+ if (EFI_ERROR (Status)) {
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
+ goto Finish;
+ }
+ //
+ // Update Checksum for FvHeader
+ //
+ FvHeader->Checksum = 0;
+ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
+ }
+
//
// Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
//
@@ -3430,6 +3548,10 @@ Returns:
mArm = TRUE;
}
+ if (ImageContext.Machine == EFI_IMAGE_MACHINE_RISCV64) {
+ mRiscV = TRUE;
+ }
+
//
// Keep Image Context for PE image in FV
//
@@ -3583,7 +3705,7 @@ Returns:
ImageContext.DestinationAddress = NewPe32BaseAddress;
Status = PeCoffLoaderRelocateImage (&ImageContext);
if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s", FileName);
+ Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s Status=%d", FileName, Status);
free ((VOID *) MemoryImagePointer);
return Status;
}
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 46089ff..4095b7c 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -3,6 +3,7 @@ Elf32 Convert solution
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -141,8 +142,8 @@ InitializeElf32 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM))) {
- Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_ARM");
+ if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM) || (mEhdr->e_machine == EM_RISCV))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32 machine.");
return FALSE;
}
if (mEhdr->e_version != EV_CURRENT) {
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 3d6319c..2aa09fd 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -3,6 +3,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "ElfConvert.h"
#include "Elf64Convert.h"
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+
STATIC
VOID
ScanSections64 (
@@ -153,8 +160,8 @@ InitializeElf64 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64))) {
- Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or EM_AARCH64");
+ if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machine.");
return FALSE;
}
if (mEhdr->e_version != EV_CURRENT) {
@@ -481,6 +488,7 @@ ScanSections64 (
switch (mEhdr->e_machine) {
case EM_X86_64:
case EM_AARCH64:
+ case EM_RISCV64:
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
default:
@@ -690,6 +698,11 @@ ScanSections64 (
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
+ case EM_RISCV64:
+ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
+ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
+ break;
+
default:
VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
@@ -769,6 +782,11 @@ WriteSections64 (
Elf_Shdr *SecShdr;
UINT32 SecOffset;
BOOLEAN (*Filter)(Elf_Shdr *);
+ UINT32 Value;
+ UINT32 Value2;
+ UINT8 *Pass1Targ = NULL;
+ Elf_Shdr *Pass1Sym = NULL;
+ Elf64_Half Pass1SymSecIndex = 0;
Elf64_Addr GOTEntryRva;
//
@@ -893,13 +911,14 @@ WriteSections64 (
if (SymName == NULL) {
SymName = (const UINT8 *)"<unknown>";
}
+ if (mEhdr->e_machine != EM_RISCV64) {
+ Error (NULL, 0, 3000, "Invalid",
+ "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
+ "For example, absolute and undefined symbols are not supported.",
+ mInImageName, SymName, Sym->st_value);
- Error (NULL, 0, 3000, "Invalid",
- "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
- "For example, absolute and undefined symbols are not supported.",
- mInImageName, SymName, Sym->st_value);
-
- exit(EXIT_FAILURE);
+ exit(EXIT_FAILURE);
+ }
}
SymShdr = GetShdrByIndex(Sym->st_shndx);
@@ -1114,6 +1133,128 @@ WriteSections64 (
default:
Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_RISCV64) {
+ switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_RISCV_NONE:
+ break;
+ case R_RISCV_32:
+ *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+ break;
+ case R_RISCV_64:
+ *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ break;
+ case R_RISCV_HI20:
+ Pass1Targ = Targ;
+ Pass1Sym = SymShdr;
+ Pass1SymSecIndex = Sym->st_shndx;
+ break;
+ case R_RISCV_LO12_I:
+ if (Pass1Sym == SymShdr && Pass1Targ != NULL && Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
+ Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
+ *(UINT32 *)Targ = (RV_X (Value, 0, 12) << 20) | \
+ (RV_X (*(UINT32 *)Targ, 0, 20));
+ }
+ Pass1Sym = NULL;
+ Pass1Targ = NULL;
+ Pass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_LO12_S:
+ if (Pass1Sym == SymShdr && Pass1Targ != NULL && Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
+ Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UINT32 *)Targ, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
+
+ Value2 = *(UINT32 *)Targ & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Targ = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ Pass1Sym = NULL;
+ Pass1Targ = NULL;
+ Pass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_PCREL_HI20:
+ Pass1Targ = Targ;
+ Pass1Sym = SymShdr;
+ Pass1SymSecIndex = Sym->st_shndx;
+
+ Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
+ break;
+ case R_RISCV_PCREL_LO12_I:
+ if (Pass1Targ != NULL && Pass1Sym != NULL && Pass1SymSecIndex != 0) {
+ int i;
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
+ Value = Value - Pass1Sym->sh_addr + mCoffSectionsOffset[Pass1SymSecIndex];
+ if(-2048 > (INT32)Value) {
+ i = (-Value / 4096);
+ Value2 -= i;
+ Value += 4096 * i;
+ if(-2048 > (INT32)Value) {
+ Value2 -= 1;
+ Value += 4096;
+ }
+ }
+ else if( 2047 < (INT32)Value) {
+ i = (Value / 4096);
+ Value2 += i;
+ Value -= 4096 * i;
+ if(2047 < (INT32)Value) {
+ Value2 += 1;
+ Value -= 4096;
+ }
+ }
+
+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ *(UINT32 *)Pass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)Pass1Targ, 0, 12));
+ }
+ Pass1Sym = NULL;
+ Pass1Targ = NULL;
+ Pass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_ADD64:
+ case R_RISCV_SUB64:
+ case R_RISCV_ADD32:
+ case R_RISCV_SUB32:
+ case R_RISCV_BRANCH:
+ case R_RISCV_JAL:
+ case R_RISCV_GPREL_I:
+ case R_RISCV_GPREL_S:
+ case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
+ break;
+
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
}
@@ -1133,6 +1274,7 @@ WriteRelocations64 (
UINT32 Index;
EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
EFI_IMAGE_DATA_DIRECTORY *Dir;
+ UINT32 RiscVRelType;
for (Index = 0; Index < mEhdr->e_shnum; Index++) {
Elf_Shdr *RelShdr = GetShdrByIndex(Index);
@@ -1237,6 +1379,108 @@ WriteRelocations64 (
default:
Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_RISCV64) {
+ RiscVRelType = ELF_R_TYPE(Rel->r_info);
+ switch (RiscVRelType) {
+ case R_RISCV_NONE:
+ break;
+
+ case R_RISCV_32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_HIGHLOW);
+ break;
+
+ case R_RISCV_64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_DIR64);
+ break;
+
+ case R_RISCV_HI20:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_HI20);
+ break;
+
+ case R_RISCV_LO12_I:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_LOW12I);
+ break;
+
+ case R_RISCV_LO12_S:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_LOW12S);
+ break;
+
+ case R_RISCV_ADD64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_SUB64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_ADD32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_SUB32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_BRANCH:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_JAL:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_GPREL_I:
+ case R_RISCV_GPREL_S:
+ case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
+ case R_RISCV_PCREL_HI20:
+ case R_RISCV_PCREL_LO12_I:
+ break;
+
+ default:
+ printf ("Unsupported RISCV64 ELF relocation type 0x%x, offset: %lx\n", RiscVRelType, Rel->r_offset);
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
}
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index 15c9e33..1321f78 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -178,6 +179,8 @@ typedef struct {
#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
#define EM_AARCH64 183 /* ARM 64bit Architecture */
+#define EM_RISCV64 243 /* 64bit RISC-V Architecture */
+#define EM_RISCV 244 /* 32bit RISC-V Architecture */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
@@ -979,5 +982,64 @@ typedef struct {
#define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable. */
#define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relative offset to GOT entry with REX prefix, relaxable. */
+/*
+ * RISC-V relocation types
+ */
+
+/* Relocation types used by the dynamic linker */
+#define R_RISCV_NONE 0
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+#define R_RISCV_COPY 4
+#define R_RISCV_JUMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32 6
+#define R_RISCV_TLS_DTPMOD64 7
+#define R_RISCV_TLS_DTPREL32 8
+#define R_RISCV_TLS_DTPREL64 9
+#define R_RISCV_TLS_TPREL32 10
+#define R_RISCV_TLS_TPREL64 11
+/* Relocation types not used by the dynamic linker */
+#define R_RISCV_BRANCH 16
+#define R_RISCV_JAL 17
+#define R_RISCV_CALL 18
+#define R_RISCV_CALL_PLT 19
+#define R_RISCV_GOT_HI20 20
+#define R_RISCV_TLS_GOT_HI20 21
+#define R_RISCV_TLS_GD_HI20 22
+#define R_RISCV_PCREL_HI20 23
+#define R_RISCV_PCREL_LO12_I 24
+#define R_RISCV_PCREL_LO12_S 25
+#define R_RISCV_HI20 26
+#define R_RISCV_LO12_I 27
+#define R_RISCV_LO12_S 28
+#define R_RISCV_TPREL_HI20 29
+#define R_RISCV_TPREL_LO12_I 30
+#define R_RISCV_TPREL_LO12_S 31
+#define R_RISCV_TPREL_ADD 32
+#define R_RISCV_ADD8 33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8 37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41
+#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_ALIGN 43
+#define R_RISCV_RVC_BRANCH 44
+#define R_RISCV_RVC_JUMP 45
+#define R_RISCV_RVC_LUI 46
+#define R_RISCV_GPREL_I 47
+#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
#endif /* !_SYS_ELF_COMMON_H_ */
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
index 44037d1..2ed3008 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -6,6 +6,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -41,6 +42,7 @@
#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
//
// Support old names for backward compatible
@@ -50,6 +52,7 @@
#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
+#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
@@ -504,7 +507,10 @@ typedef struct {
#define EFI_IMAGE_REL_BASED_HIGHADJ 4
#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
#define EFI_IMAGE_REL_BASED_DIR64 10
diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
index 8ae1bd2..fc23e8c 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -52,7 +53,9 @@ TAB_ARCH_ARM = 'ARM'
TAB_ARCH_EBC = 'EBC'
TAB_ARCH_AARCH64 = 'AARCH64'
-ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_COMMON}
+TAB_ARCH_RISCV64 = 'RISCV64'
+
+ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
SUP_MODULE_BASE = 'BASE'
SUP_MODULE_SEC = 'SEC'
@@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE = {8:'=Q',
0:'=B',
16:""}
-TAB_COMPILER_MSFT = 'MSFT'
\ No newline at end of file
+TAB_COMPILER_MSFT = 'MSFT'
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (24 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 20:50 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
` (18 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds
causes PE32 relocation error.
This is the temporaty solution untill we find the root casue.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Scripts/GccBaseRiscV.lds | 66 ++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBaseRiscV.lds
new file mode 100644
index 0000000..7f9fae6
--- /dev/null
+++ b/BaseTools/Scripts/GccBaseRiscV.lds
@@ -0,0 +1,66 @@
+/** @file
+
+ Unified linker script for GCC based builds
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+SECTIONS {
+
+ /*
+ * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
+ * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
+ * between 32-bit and 64-bit builds). The actual start of the .text section
+ * will be rounded up based on its actual alignment.
+ */
+ . = PECOFF_HEADER_SIZE;
+
+ .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.text .text.* .stub .gnu.linkonce.t.*)
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.got .got.*)
+
+ /*
+ * The contents of AutoGen.c files are constant from the POV of the program,
+ * but most of its contents end up in .data or .bss by default since few of
+ * the variable definitions that get emitted are declared as CONST.
+ */
+ *:AutoGen.obj(.data.g*Guid)
+ }
+
+ /*
+ * The alignment of the .data section should be less than or equal to the
+ * alignment of the .text section. This ensures that the relative offset
+ * between these sections is the same in the ELF and the PE/COFF versions of
+ * this binary.
+ */
+ .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.bss .bss.*)
+ }
+
+ .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ KEEP (*(.eh_frame))
+ }
+
+ .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ *(.rela .rela.*)
+ }
+
+ /DISCARD/ : {
+ *(.note.GNU-stack)
+ *(.gnu_debuglink)
+ *(.interp)
+ *(.dynsym)
+ *(.dynstr)
+ *(.dynamic)
+ *(.hash)
+ *(.comment)
+ *(COMMON)
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (25 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 22:39 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
` (17 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++++
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++++
RiscVPkg/RiscVPkg.dec | 6 +
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 +++++++++++++++++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
| 13 +
8 files changed, 613 insertions(+)
create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include/ProcessorSpecificDataHob.h
new file mode 100644
index 0000000..6798a9d
--- /dev/null
+++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h
@@ -0,0 +1,95 @@
+/** @file
+ Definition of Processor Specific Data HOB.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
+#define _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
+
+#include <IndustryStandard/SmBios.h>
+
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
+
+#pragma pack(1)
+
+///
+/// RISC-V processor specific data HOB
+///
+typedef struct {
+ EFI_GUID ParentPrcessorGuid;
+ UINTN ParentProcessorUid;
+ EFI_GUID CoreGuid;
+ VOID *Context; // The additional information of this core which
+ // built in PEI phase and carried to DXE phase.
+ // The content is pocessor or platform specific.
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB;
+
+///
+/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE4_DATA_HOB;
+
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE7_DATA_HOB;
+
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache;
+} RISC_V_PROCESSOR_SMBIOS_DATA_HOB;
+
+#pragma pack()
+
+#endif
diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
new file mode 100644
index 0000000..36aa4ab
--- /dev/null
+++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
@@ -0,0 +1,58 @@
+/** @file
+ Industry Standard Definitions of RISC-V Processor Specific data defined in
+ below link for complaiant with SMBIOS Table Specification v3.3.0.
+ https://github.com/riscv/riscv-smbios
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+#define _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+
+#include <IndustryStandard/SmBios.h>
+
+#include <RiscV.h>
+
+#pragma pack(1)
+
+typedef enum{
+ RegisterUnsupported = 0x00,
+ RegisterLen32 = 0x01,
+ RegisterLen64 = 0x02,
+ RegisterLen128 = 0x03
+} RISC_V_REGISTER_LENGTH;
+
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
+
+///
+/// RISC-V processor specific data for SMBIOS type 44
+///
+typedef struct {
+ UINT16 Revision;
+ UINT8 Length;
+ RISCV_UINT128 HartId;
+ UINT8 BootHartId;
+ RISCV_UINT128 MachineVendorId;
+ RISCV_UINT128 MachineArchId;
+ RISCV_UINT128 MachineImplId;
+ UINT32 InstSetSupported;
+ UINT8 PrivilegeModeSupported;
+ RISCV_UINT128 MModeExcepDelegation;
+ RISCV_UINT128 MModeInterruptDelegation;
+ UINT8 HartXlen;
+ UINT8 MachineModeXlen;
+ UINT8 Reserved;
+ UINT8 SupervisorModeXlen;
+ UINT8 UserModeXlen;
+} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index a91392f..b316223 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -24,6 +24,12 @@
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
[PcdsFixedAtBuild]
+ # Processor Specific Data GUID HOB GUID
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
+
#
# 1000000000
# PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
new file mode 100644
index 0000000..032f559
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -0,0 +1,339 @@
+/** @file
+ RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RiscVSmbiosDxe.h"
+
+#define RISCV_SMBIOS_DEBUG_INFO 1
+
+EFI_SMBIOS_PROTOCOL *Smbios;
+
+/**
+ This function builds SMBIOS type 7 record according to
+ the given RISC_V_PROCESSOR_TYPE7_DATA_HOB.
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_DATA_HOB
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+static
+EFI_STATUS
+BuildSmbiosType7 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ IN RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+)
+{
+ EFI_STATUS Status;
+ SMBIOS_HANDLE Handle;
+
+ if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+ Type4DataHob->ProcessorUid != Type7DataHob->ProcessorUid) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Handle = SMBIOS_HANDLE_PI_RESERVED;
+ Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+ Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
+ Type7DataHob->EndingZero = 0;
+ Status = Smbios->Add (Smbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 7\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
+ DEBUG ((DEBUG_INFO, " ==============================\n"));
+ DEBUG ((DEBUG_INFO, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
+ DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
+ DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
+ DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
+ DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
+ DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
+ DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
+ DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
+ DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
+ DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
+#endif
+
+ *SmbiosHandle = Handle;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 4 record according to
+ the given RISC_V_PROCESSOR_TYPE4_DATA_HOB.
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+static
+EFI_STATUS
+BuildSmbiosType4 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData;
+ SMBIOS_HANDLE Cache;
+ SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 4.\n"));
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
+
+ Type4DataHob->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4DataHob->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4DataHob->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS Type7 data HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
+ //
+ do {
+ Type7HobData = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ Status = BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+ Type4DataHob->SmbiosType4Processor.L1CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+ Type4DataHob->SmbiosType4Processor.L2CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+ Type4DataHob->SmbiosType4Processor.L3CacheHandle = Cache;
+ } else {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Improper cache level of SMBIOS handle %d\n", Cache));
+ }
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+
+ //
+ // Build SMBIOS Type 4 record
+ //
+ Processor = SMBIOS_HANDLE_PI_RESERVED;
+ Type4DataHob->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+ Type4DataHob->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+ Type4DataHob->SmbiosType4Processor.Hdr.Handle = 0;
+ Type4DataHob->EndingZero = 0;
+ Status = Smbios->Add (Smbios, NULL, &Processor, &Type4DataHob->SmbiosType4Processor.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 4\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Socket StringID: %d\n", Type4DataHob->SmbiosType4Processor.Socket));
+ DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorType));
+ DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily));
+ DEBUG ((DEBUG_INFO, " Processor Manufacture StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture));
+ DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n", \
+ Type4DataHob->SmbiosType4Processor.ProcessorId.Signature, Type4DataHob->SmbiosType4Processor.ProcessorId.FeatureFlags));
+ DEBUG ((DEBUG_INFO, " Processor Version StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorVersion));
+ DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4DataHob->SmbiosType4Processor.Voltage));
+ DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n", Type4DataHob->SmbiosType4Processor.ExternalClock));
+ DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.MaxSpeed));
+ DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.CurrentSpeed));
+ DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4DataHob->SmbiosType4Processor.Status));
+ DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorUpgrade));
+ DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L1CacheHandle));
+ DEBUG ((DEBUG_INFO, " L2 Cache Handle: 0x%x\n",Type4DataHob->SmbiosType4Processor.L2CacheHandle));
+ DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L3CacheHandle));
+ DEBUG ((DEBUG_INFO, " Serial Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.SerialNumber));
+ DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n", Type4DataHob->SmbiosType4Processor.AssetTag));
+ DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.PartNumber));
+ DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount));
+ DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount));
+ DEBUG ((DEBUG_INFO, " Thread Count: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount));
+ DEBUG ((DEBUG_INFO, " Processor Characteristics: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics));
+ DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily2));
+ DEBUG ((DEBUG_INFO, " Core Count 2: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount2));
+ DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount2));
+ DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount2));
+#endif
+
+ *SmbiosHandle = Processor;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 44 record according..
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param Type4Handle SMBIOS handle of type 4
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+BuildSmbiosType44 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ IN SMBIOS_HANDLE Type4Handle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData;
+ SMBIOS_HANDLE RiscVType44;
+ SMBIOS_TABLE_TYPE44 *Type44Ptr;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 44 for...\n"));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
+#endif
+
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC_V_PROCESSOR_SPECIFIC_DATA_HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for multiple cores.
+ //
+ do {
+ ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4DataHob->PrcessorGuid) ||
+ ProcessorSpecificData->ParentProcessorUid != Type4DataHob->ProcessorUid) {
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ if (GuidHob == NULL) {
+ break;
+ }
+ continue;
+ }
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, "[ ================================\n"));
+ DEBUG ((DEBUG_INFO, "[ Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
+#endif
+
+ Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+ if (Type44Ptr == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+ Type44Ptr->Hdr.Handle = 0;
+ Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->RefHandle = Type4Handle;
+ Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4DataHob->SmbiosType4Processor.ProcessorFamily2 -
+ ProcessorFamilyRiscvRV32 + \
+ ProcessorSpecificBlockArchTypeRiscVRV32;
+ CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, "[ Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
+ DEBUG ((DEBUG_INFO, " HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
+ DEBUG ((DEBUG_INFO, " PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
+ DEBUG ((DEBUG_INFO, " MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
+ DEBUG ((DEBUG_INFO, " InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
+ DEBUG ((DEBUG_INFO, " MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
+#endif
+
+ //
+ // Add to SMBIOS table.
+ //
+ RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
+ Status = Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 44\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ return EFI_SUCCESS;
+}
+
+/**
+ Entry point of RISC-V SMBIOS builder.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSmbiosBuilderEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData;
+ SMBIOS_HANDLE Processor;
+
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a entry\n", __FUNCTION__));
+
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS Protocol fail\n"));
+ return Status;
+ }
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS information found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ Type4HobData = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ Status = EFI_NOT_FOUND;
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
+ //
+ do {
+ Status = BuildSmbiosType4 (Type4HobData, &Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 4 created.\n"));
+ ASSERT (FALSE);
+ }
+ Status = BuildSmbiosType44 (Type4HobData, Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 44 found.\n"));
+ ASSERT (FALSE);
+ }
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a exit\n", __FUNCTION__));
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
new file mode 100644
index 0000000..dfa1fc6
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -0,0 +1,32 @@
+/** @file
+ RISC-V SMBIOS Builder DXE module header file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _RISC_V_SMBIOS_DXE_H_
+#define _RISC_V_SMBIOS_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/Smbios.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificDataHob.h>
+
+#endif
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
new file mode 100644
index 0000000..59b814a
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
@@ -0,0 +1,58 @@
+## @file
+# RISC-V SMBIOS DXE module.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSmbiosDxe
+ MODULE_UNI_FILE = RiscVSmbiosDxe.uni
+ FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RiscVSmbiosBuilderEntry
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ CpuLib
+ DebugLib
+ DxeServicesTableLib
+ HobLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Sources]
+ RiscVSmbiosDxe.c
+ RiscVSmbiosDxe.h
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # Consumed
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
new file mode 100644
index 0000000..1bffe09
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
@@ -0,0 +1,12 @@
+// /** @file
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor SMBIOS Builder"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Processor SMBIOS Type 4, 7, 44 records."
+
--git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
new file mode 100644
index 0000000..4b37ca2
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V SMBIOS Builder Localized Strings and Content
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V SMBIOS Record Builder DXE Driver"
+
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (26 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-26 22:24 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
` (16 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add submodule opensbi under RiscVPkg. The current supported opensbi
version for RISC-V edk2 port is commit ID:ce228ee (tags/v0.4).
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.gitmodules | 16 ++++++++++------
RiscVPkg/opensbi | 1 +
2 files changed, 11 insertions(+), 6 deletions(-)
create mode 160000 RiscVPkg/opensbi
diff --git a/.gitmodules b/.gitmodules
index 508f0c1..6d3e28c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,10 @@
-[submodule "CryptoPkg/Library/OpensslLib/openssl"]
- path = CryptoPkg/Library/OpensslLib/openssl
- url = https://github.com/openssl/openssl
-[submodule "SoftFloat"]
- path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
- url = https://github.com/ucb-bar/berkeley-softfloat-3.git
+[submodule "CryptoPkg/Library/OpensslLib/openssl"]
+ path = CryptoPkg/Library/OpensslLib/openssl
+ url = https://github.com/openssl/openssl
+[submodule "SoftFloat"]
+ path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
+ url = https://github.com/ucb-bar/berkeley-softfloat-3.git
+[submodule "RiscVPkg/opensbi"]
+ path = RiscVPkg/opensbi
+ url = https://github.com/riscv/opensbi.git
+
diff --git a/RiscVPkg/opensbi b/RiscVPkg/opensbi
new file mode 160000
index 0000000..ce228ee
--- /dev/null
+++ b/RiscVPkg/opensbi
@@ -0,0 +1 @@
+Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (27 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 22:48 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
` (15 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add RiscVEdk2Readme.md
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVEdk2Readme.md | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 RiscVEdk2Readme.md
diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md
new file mode 100644
index 0000000..ec691fe
--- /dev/null
+++ b/RiscVEdk2Readme.md
@@ -0,0 +1,34 @@
+This branch is used to contribute RISC-V architecture to EDK2
+
+The branch owner:<br>
+Abner Chang < abner.chang@hpe.com > <br>
+Gilbert Chen < gilbert.chen@hpe.com >
+
+## RISC-V EDK2 Port Introduction
+RISC-V is an open ISA which was designed to support research and education of computer architecture, but now it becomes
+a standard open Instruction Set Architecture for industry implementations. The RISC-V edk2 project is to create a new processor binding in UEFI spec and have the RISC-V edk2 implementation. The goal is to have RISC-V edk2 port as the firmware reference
+for RISC-V platforms.
+
+This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V OpenSbi (https://github.com/riscv/opensbi) library integrated. RiscVPkg provides the generic and common modules of RISC-V prcessor. The first edk2 RISC-V platform is SiFive U500 FPGA whcih is maintained in U500Pkg under Platform/RiscV/SiFive in edk2-platform repository.
+
+## RISC-V EDK2 Package
+```
+RiscVPkg - RISC-V processor package. This package provides RISC-V processor related protocols/libraries accroding
+ to UEFI specification and edk2 implementations.
+```
+## Toolchain of RISC-V EDK2 port
+To build edk2 RISC-V platform requires GCC RISC-V toolchain, refer to https://github.com/riscv/riscv-gnu-toolchain for the details. The commit ID 64879b24 of riscv-gnu-toolchain repository is verified to build RISC-V edk2 platform and boot to EFI SHELL successfully. You have to clone the toolchain from above link and check out commit:64879b24 for building RISC-V edk2 port. The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase transition. We are still figuring out the root cause.
+
+## EDK2 Build Target
+"RISCV64" ARCH is the RISC-V architecture which currently supported and verified. The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in tools_def.txt.<br>
+Below is the edk2 build options for building RISC-V RV64 platform, <br>
+```
+build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5
+```
+For example, <br>
+```
+build -a RISCV64 -p Platform/SiFive/U500/U500.dsc -t GCC5
+```
+
+Make sure RISC-V toolchain is built succesfully and the toolchain binaries are generated in somewhere you specified when building toolchain. 'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries. <br>
+For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-' before you build RISC-V edk2 port.
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (28 preceding siblings ...)
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
@ 2019-09-23 0:31 ` Abner Chang
2019-09-30 22:50 ` [edk2-devel] " Leif Lindholm
[not found] ` <15C6EB9824DD2A88.29693@groups.io>
` (14 subsequent siblings)
44 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-09-23 0:31 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add maintainer and reviewer of RiscVPkg.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Maintainers.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index 919bacc..11449a5 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -408,6 +408,11 @@ F: PcAtChipsetPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
M: Ray Ni <ray.ni@intel.com>
+RiscVPkg: RISCV64 architecture modules
+F: RISCV64/
+M: Abner Chang <abner.chang@hpe.com>
+R: Gilbert Chen <gilbert.chen@hpe.com>
+
SecurityPkg
F: SecurityPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
--
2.7.4
^ permalink raw reply related [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg
[not found] ` <15C6EB9824DD2A88.29693@groups.io>
@ 2019-09-24 1:52 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:52 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Michael D Kinney, Liming Gao
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:31 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg:
> RISC-V RV64 binding in MdePkg
>
> Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Include/RiscV64/ProcessorBind.h | 173
> +++++++++++++++++++++++++++++++++
> MdePkg/MdePkg.dec | 5 +-
> 2 files changed, 177 insertions(+), 1 deletion(-) create mode 100644
> MdePkg/Include/RiscV64/ProcessorBind.h
>
> diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h
> b/MdePkg/Include/RiscV64/ProcessorBind.h
> new file mode 100644
> index 0000000..c3d4ef7
> --- /dev/null
> +++ b/MdePkg/Include/RiscV64/ProcessorBind.h
> @@ -0,0 +1,173 @@
> +/** @file
> + Processor or Compiler specific defines and types for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __PROCESSOR_BIND_H__
> +#define __PROCESSOR_BIND_H__
> +
> +///
> +/// Define the processor type so other code can make processor based
> +choices /// #define MDE_CPU_RISCV64
> +
> +//
> +// Make sure we are using the correct packing rules per EFI
> +specification // #if !defined(__GNUC__) #pragma pack() #endif
> +
> +///
> +/// 8-byte unsigned value
> +///
> +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); ///
> +/// 8-byte signed value ///
> +typedef long long INT64 __attribute__ ((aligned (8)));
> +///
> +/// 4-byte unsigned value
> +///
> +typedef unsigned int UINT32 __attribute__ ((aligned (4)));
> +///
> +/// 4-byte signed value
> +///
> +typedef int INT32 __attribute__ ((aligned (4)));
> +///
> +/// 2-byte unsigned value
> +///
> +typedef unsigned short UINT16 __attribute__ ((aligned (2)));
> +///
> +/// 2-byte Character. Unless otherwise specified all strings are
> +stored in the /// UTF-16 encoding format as defined by Unicode 2.1 and
> ISO/IEC 10646 standards.
> +///
> +typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
> +///
> +/// 2-byte signed value
> +///
> +typedef short INT16 __attribute__ ((aligned (2)));
> +///
> +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for
> +TRUE. Other /// values are undefined.
> +///
> +typedef unsigned char BOOLEAN;
> +///
> +/// 1-byte unsigned value
> +///
> +typedef unsigned char UINT8;
> +///
> +/// 1-byte Character
> +///
> +typedef char CHAR8;
> +///
> +/// 1-byte signed value
> +///
> +typedef signed char INT8;
> +///
> +/// Unsigned value of native width. (4 bytes on supported 32-bit
> +processor instructions, /// 8 bytes on supported 64-bit processor
> +instructions) /// typedef UINT64 UINTN __attribute__ ((aligned (8)));
> +/// /// Signed value of native width. (4 bytes on supported 32-bit
> +processor instructions, /// 8 bytes on supported 64-bit processor
> +instructions) ///
> +typedef INT64 INTN __attribute__ ((aligned (8)));
> +
> +//
> +// Processor specific defines
> +//
> +
> +///
> +/// A value of native width with the highest bit set.
> +///
> +#define MAX_BIT 0x8000000000000000ULL
> +///
> +/// A value of native width with the two highest bits set.
> +///
> +#define MAX_2_BITS 0xC000000000000000ULL
> +
> +///
> +/// Maximum legal RV64 address
> +///
> +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
> +
> +///
> +/// Maximum usable address at boot time (48 bits using 4 KB pages in
> +Supervisor mode) ///
> +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
> +
> +///
> +/// Maximum legal RISC-V INTN and UINTN values.
> +///
> +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
> +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
> +
> +///
> +/// The stack alignment required for RISC-V ///
> +#define CPU_STACK_ALIGNMENT 16
> +
> +///
> +/// Page allocation granularity for RISC-V ///
> +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
> +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
> +
> +//
> +// Modifier to ensure that all protocol member functions and EFI
> +intrinsics // use the correct C calling convention. All protocol member
> +functions and // EFI intrinsics are required to modify their member
> functions with EFIAPI.
> +//
> +#ifdef EFIAPI
> + ///
> + /// If EFIAPI is already defined, then we use that definition.
> + ///
> +#elif defined(__GNUC__)
> + ///
> + /// Define the standard calling convention regardless of optimization
> +level
> + /// The GCC support assumes a GCC compiler that supports the EFI ABI.
> +The EFI
> + /// ABI is much closer to the x64 Microsoft* ABI than standard x64
> +(x86-64)
> + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be
> +used for
> + /// x64. Warning the assembly code in the MDE x64 does not follow the
> +correct
> + /// ABI for the standard x64 (x86-64) GCC.
> + ///
> + #define EFIAPI
> +#else
> + ///
> + /// The default for a non Microsoft* or GCC compiler is to assume the
> +EFI ABI
> + /// is the standard.
> + ///
> + #define EFIAPI
> +#endif
> +
> +#if defined(__GNUC__)
> + ///
> + /// For GNU assembly code, .global or .globl can declare global symbols.
> + /// Define this macro to unify the usage.
> + ///
> + #define ASM_GLOBAL .globl
> +#endif
> +
> +/**
> + Return the pointer to the first instruction of a function given a function
> pointer.
> + On x64 CPU architectures, these two pointer values are the same,
> + so the implementation of this macro is very simple.
> +
> + @param FunctionPointer A pointer to a function.
> +
> + @return The pointer to the first instruction of a function given a function
> pointer.
> +
> +**/
> +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID
> +*)(UINTN)(FunctionPointer)
> +
> +#ifndef __USER_LABEL_PREFIX__
> +#define __USER_LABEL_PREFIX__
> +#endif
> +
> +#endif
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> 3fd7d16..1aaa97d 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -6,7 +6,7 @@
> #
> # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> -# (C)
> Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> +# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development
> +LP<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +39,9 @@
> [Includes.AARCH64]
> Include/AArch64
>
> +[Includes.RISCV64]
> + Include/RiscV64
> +
> [LibraryClasses]
> ## @libraryclass Provides most usb APIs to support the Hid requests
> defined in Usb Hid 1.1 spec
> # and the standard requests defined in Usb 1.1 spec.
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions.
[not found] ` <15C6EB994C26E5C4.2053@groups.io>
@ 2019-09-24 1:52 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:52 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29]
> MdePkg/Include: RISC-V definitions.
>
> Add RISC-V processor related definitions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++
> MdePkg/Include/Protocol/DebugSupport.h | 55
> +++++++++++++++++++++++++++++++
> MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++
> MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++
> MdePkg/Include/Uefi/UefiSpec.h | 5 +++
> 5 files changed, 89 insertions(+)
>
> diff --git a/MdePkg/Include/IndustryStandard/PeImage.h
> b/MdePkg/Include/IndustryStandard/PeImage.h
> index 720bb08..ca3fd0b 100644
> --- a/MdePkg/Include/IndustryStandard/PeImage.h
> +++ b/MdePkg/Include/IndustryStandard/PeImage.h
> @@ -9,6 +9,8 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> +Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define IMAGE_FILE_MACHINE_X64 0x8664
> #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
> #define IMAGE_FILE_MACHINE_ARM64 0xAA64
> +#define IMAGE_FILE_MACHINE_RISCV32 0x5032
> +#define IMAGE_FILE_MACHINE_RISCV64 0x5064
> +#define IMAGE_FILE_MACHINE_RISCV128 0x5128
>
> //
> // EXE file formats
> @@ -494,6 +499,13 @@ typedef struct {
> #define EFI_IMAGE_REL_BASED_DIR64 10
>
> ///
> +/// Relocation types of RISC-V processor.
> +///
> +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
> +
> +///
> /// Line number format.
> ///
> typedef struct {
> diff --git a/MdePkg/Include/Protocol/DebugSupport.h
> b/MdePkg/Include/Protocol/DebugSupport.h
> index 800e771..1a29cc0 100644
> --- a/MdePkg/Include/Protocol/DebugSupport.h
> +++ b/MdePkg/Include/Protocol/DebugSupport.h
> @@ -7,6 +7,7 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -603,6 +604,59 @@ typedef struct {
> UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64;
>
> +///
> +/// RISC-V processor exception types.
> +///
> +#define EXCEPT_RISCV_INST_MISALIGNED 0
> +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
> +#define EXCEPT_RISCV_ILLEGAL_INST 2
> +#define EXCEPT_RISCV_BREAKPOINT 3
> +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
> +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
> +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
> +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
> +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
> +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
> +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
> +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
> +
> +#define EXCEPT_RISCV_SOFTWARE_INT 0x0
> +#define EXCEPT_RISCV_TIMER_INT 0x1
> +
> +typedef struct {
> + UINT64 X0;
> + UINT64 X1;
> + UINT64 X2;
> + UINT64 X3;
> + UINT64 X4;
> + UINT64 X5;
> + UINT64 X6;
> + UINT64 X7;
> + UINT64 X8;
> + UINT64 X9;
> + UINT64 X10;
> + UINT64 X11;
> + UINT64 X12;
> + UINT64 X13;
> + UINT64 X14;
> + UINT64 X15;
> + UINT64 X16;
> + UINT64 X17;
> + UINT64 X18;
> + UINT64 X19;
> + UINT64 X20;
> + UINT64 X21;
> + UINT64 X22;
> + UINT64 X23;
> + UINT64 X24;
> + UINT64 X25;
> + UINT64 X26;
> + UINT64 X27;
> + UINT64 X28;
> + UINT64 X29;
> + UINT64 X30;
> + UINT64 X31;
> +} EFI_SYSTEM_CONTEXT_RISCV64;
>
> ///
> /// Universal EFI_SYSTEM_CONTEXT definition.
> @@ -614,6 +668,7 @@ typedef union {
> EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
> EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
> EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
> + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
> } EFI_SYSTEM_CONTEXT;
>
> //
> diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h
> b/MdePkg/Include/Protocol/PxeBaseCode.h
> index b02d270..8a9e4a1 100644
> --- a/MdePkg/Include/Protocol/PxeBaseCode.h
> +++ b/MdePkg/Include/Protocol/PxeBaseCode.h
> @@ -3,6 +3,8 @@
> devices for network access and network booting.
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> +All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @par Revision Reference:
> @@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A
> #elif defined (MDE_CPU_AARCH64)
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
> +#elif defined (MDE_CPU_RISCV64)
> +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
> #endif
>
>
> diff --git a/MdePkg/Include/Uefi/UefiBaseType.h
> b/MdePkg/Include/Uefi/UefiBaseType.h
> index a62f13d..d979412 100644
> --- a/MdePkg/Include/Uefi/UefiBaseType.h
> +++ b/MdePkg/Include/Uefi/UefiBaseType.h
> @@ -3,6 +3,7 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> +All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -240,6 +241,12 @@ typedef union {
> ///
> #define EFI_IMAGE_MACHINE_AARCH64 0xAA64
>
> +///
> +/// PE32+ Machine type for RISC-V 32/64/128 ///
> +#define EFI_IMAGE_MACHINE_RISCV32 0x5032
> +#define EFI_IMAGE_MACHINE_RISCV64 0x5064
> +#define EFI_IMAGE_MACHINE_RISCV128 0x5128
>
> #if defined (MDE_CPU_IA32)
>
> @@ -268,6 +275,12 @@ typedef union {
>
> #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
>
> +#elif defined (MDE_CPU_RISCV64)
> +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
> + ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
> +
> +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
> +
> #elif defined (MDE_CPU_EBC)
>
> ///
> diff --git a/MdePkg/Include/Uefi/UefiSpec.h
> b/MdePkg/Include/Uefi/UefiSpec.h index 44a0a6a..e2d4539 100644
> --- a/MdePkg/Include/Uefi/UefiSpec.h
> +++ b/MdePkg/Include/Uefi/UefiSpec.h
> @@ -6,6 +6,8 @@
> by this include file.
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> +All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -2178,6 +2180,7 @@ typedef struct {
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64
> L"\\EFI\\BOOT\\BOOTX64.EFI"
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
> L"\\EFI\\BOOT\\BOOTARM.EFI"
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
> L"\\EFI\\BOOT\\BOOTAA64.EFI"
> +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
> L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
>
> #if defined (MDE_CPU_IA32)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME
> EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
> @@ -2188,6 +2191,8 @@ typedef struct {
> #define EFI_REMOVABLE_MEDIA_FILE_NAME
> EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
> #elif defined (MDE_CPU_AARCH64)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME
> EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
> +#elif defined (MDE_CPU_RISCV64)
> + #define EFI_REMOVABLE_MEDIA_FILE_NAME
> EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
> #else
> #error Unknown Processor Type
> #endif
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
[not found] ` <15C6EB9950232DB5.29693@groups.io>
@ 2019-09-24 1:53 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:53 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC Maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29]
> MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
>
> Add RISC-V RV64 BaseLib functions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Include/Library/BaseLib.h | 26 ++
> MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
> MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++
> MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +++
> MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++
> MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++
> MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++
> MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35
> +++ .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++
> MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++
> .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++
> MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++
> MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++
> .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++
> MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264
> +++++++++++++++++++++
> 15 files changed, 670 insertions(+), 1 deletion(-) create mode 100644
> MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> create mode 100644
> MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> create mode 100644
> MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
>
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 2a75bc0..b8c8512 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -4,6 +4,8 @@
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> +Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -124,6 +126,30 @@ typedef struct {
>
> #endif // defined (MDE_CPU_AARCH64)
>
> +#if defined (MDE_CPU_RISCV64)
> +///
> +/// The RISC-V architecture context buffer used by SetJump() and
> LongJump().
> +///
> +typedef struct {
> + UINT64 RA;
> + UINT64 S0;
> + UINT64 S1;
> + UINT64 S2;
> + UINT64 S3;
> + UINT64 S4;
> + UINT64 S5;
> + UINT64 S6;
> + UINT64 S7;
> + UINT64 S8;
> + UINT64 S9;
> + UINT64 S10;
> + UINT64 S11;
> + UINT64 SP;
> +} BASE_LIBRARY_JUMP_BUFFER;
> +
> +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
> +
> +#endif // defined (MDE_CPU_RISCV64)
>
> //
> // String Services
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 3586beb..28d5795 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -4,6 +4,7 @@
> # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> #
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@
> LIBRARY_CLASS = BaseLib
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> @@ -381,6 +382,21 @@
> AArch64/CpuBreakpoint.asm | MSFT
> AArch64/SpeculationBarrier.asm | MSFT
>
> +[Sources.RISCV64]
> + Math64.c
> + RiscV64/Unaligned.c
> + RiscV64/InternalSwitchStack.c
> + RiscV64/CpuBreakpoint.c
> + RiscV64/GetInterruptState.c
> + RiscV64/DisableInterrupts.c
> + RiscV64/EnableInterrupts.c
> + RiscV64/CpuPause.c
> + RiscV64/RiscVSetJumpLongJump.S | GCC
> + RiscV64/RiscVCpuBreakpoint.S | GCC
> + RiscV64/RiscVCpuPause.S | GCC
> + RiscV64/RiscVInterrupt.S | GCC
> + RiscV64/FlushCache.S | GCC
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> new file mode 100644
> index 0000000..d82b1d5
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> @@ -0,0 +1,27 @@
> +/** @file
> + CPU breakpoint for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVCpuBreakpoint (VOID);
> +
> +/**
> + Generates a breakpoint on the CPU.
> +
> + Generates a breakpoint on the CPU. The breakpoint must be implemented
> + such that code can resume normal execution after the breakpoint.
> +
> +**/
> +VOID
> +EFIAPI
> +CpuBreakpoint (
> + VOID
> + )
> +{
> + RiscVCpuBreakpoint ();
> +}
> diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> new file mode 100644
> index 0000000..8eb6b65
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> @@ -0,0 +1,29 @@
> +/** @file
> + CPU pause for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVCpuPause (VOID);
> +
> +
> +/**
> + Requests CPU to pause for a short period of time.
> +
> + Requests CPU to pause for a short period of time. Typically used in
> + MP systems to prevent memory starvation while waiting for a spin lock.
> +
> +**/
> +VOID
> +EFIAPI
> +CpuPause (
> + VOID
> + )
> +{
> + RiscVCpuPause ();
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> new file mode 100644
> index 0000000..7ee5eb1
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> @@ -0,0 +1,24 @@
> +/** @file
> + CPU disable interrupt function for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> +"BaseLibInternals.h"
> +
> +extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
> +
> +/**
> + Disables CPU interrupts.
> +
> +**/
> +VOID
> +EFIAPI
> +DisableInterrupts (
> + VOID
> + )
> +{
> + RiscVDisableSupervisorModeInterrupts (); }
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> new file mode 100644
> index 0000000..9aa0d9a
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> @@ -0,0 +1,25 @@
> +/** @file
> + CPU enable interrupt function for RISC-V
> +
> + Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
> +
> +/**
> + Enables CPU interrupts.
> +
> +**/
> +VOID
> +EFIAPI
> +EnableInterrupts (
> + VOID
> + )
> +{
> + RiscVEnableSupervisorModeInterrupt (); }
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> new file mode 100644
> index 0000000..0ef0213
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> @@ -0,0 +1,21 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// RISC-V cache operation.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +
> +.align 3
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
> +
> +ASM_PFX(RiscVInvalidateInstCacheAsm):
> + fence.i
> + ret
> +
> +ASM_PFX(RiscVInvalidateDataCacheAsm):
> + fence
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> new file mode 100644
> index 0000000..8f764fb
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> @@ -0,0 +1,35 @@
> +/** @file
> + CPU get interrupt state function for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
> +
> +/**
> + Retrieves the current CPU interrupt state.
> +
> + Returns TRUE is interrupts are currently enabled. Otherwise returns
> + FALSE.
> +
> + @retval TRUE CPU interrupts are enabled.
> + @retval FALSE CPU interrupts are disabled.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +GetInterruptState (
> + VOID
> + )
> +{
> + unsigned long RetValue;
> +
> + RetValue = RiscVGetSupervisorModeInterrupts ();
> + return RetValue? TRUE: FALSE;
> +}
> +
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> new file mode 100644
> index 0000000..1082d4e
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> @@ -0,0 +1,55 @@
> +/** @file
> + Switch stack function for RISC-V
> +
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> + rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +/**
> + Transfers control to a function starting with a new stack.
> +
> + Transfers control to the function specified by EntryPoint using the
> + new stack specified by NewStack and passing in the parameters
> + specified by Context1 and Context2. Context1 and Context2 are
> + optional and may be NULL. The function EntryPoint must never return.
> + Marker will be ignored on IA-32, x64, and EBC.
> + IPF CPUs expect one additional parameter of type VOID * that
> + specifies the new backing store pointer.
> +
> + If EntryPoint is NULL, then ASSERT().
> + If NewStack is NULL, then ASSERT().
> +
> + @param EntryPoint A pointer to function to call with the new stack.
> + @param Context1 A pointer to the context to pass into the EntryPoint
> + function.
> + @param Context2 A pointer to the context to pass into the EntryPoint
> + function.
> + @param NewStack A pointer to the new stack to use for the EntryPoint
> + function.
> + @param Marker VA_LIST marker for the variable argument list.
> +
> +**/
> +VOID
> +EFIAPI
> +InternalSwitchStack (
> + IN SWITCH_STACK_ENTRY_POINT EntryPoint,
> + IN VOID *Context1, OPTIONAL
> + IN VOID *Context2, OPTIONAL
> + IN VOID *NewStack,
> + IN VA_LIST Marker
> + )
> +{
> + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
> +
> + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x
> Context2:%x NewStack%x\n", \
> + EntryPoint, Context1, Context2, NewStack));
> + JumpBuffer.RA = (UINTN)EntryPoint;
> + JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
> + JumpBuffer.S0 = (UINT64)(UINTN)Context1;
> + JumpBuffer.S1 = (UINT64)(UINTN)Context2;
> + LongJump (&JumpBuffer, (UINTN)-1);
> + ASSERT(FALSE);
> +}
> diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> new file mode 100644
> index 0000000..a62b882
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> @@ -0,0 +1,32 @@
> +/** @file
> + Long jump implementation of RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +
> +/**
> + Restores the CPU context that was saved with SetJump().
> +
> + Restores the CPU context from the buffer specified by JumpBuffer.
> + This function never returns to the caller.
> + Instead is resumes execution based on the state of JumpBuffer.
> +
> + @param JumpBuffer A pointer to CPU context buffer.
> + @param Value The value to return when the SetJump() context is
> restored.
> +
> +**/
> +VOID
> +EFIAPI
> +InternalLongJump (
> + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
> + IN UINTN Value
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> new file mode 100644
> index 0000000..1a45e2a
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> @@ -0,0 +1,14 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// CpuBreakpoint for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +
> +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
> +ASM_PFX(RiscVCpuBreakpoint):
> + ebreak
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> new file mode 100644
> index 0000000..ceba0c0
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> @@ -0,0 +1,14 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// CpuPause for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +
> +ASM_GLOBAL ASM_PFX(RiscVCpuPause)
> +ASM_PFX(RiscVCpuPause):
> + nop
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> new file mode 100644
> index 0000000..8fdb544
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> @@ -0,0 +1,32 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// RISC-V Supervisor Mode interrupt enable/disable // // Copyright (c)
> +2016 - 2019, Hewlett Packard Enterprise Development LP. All rights
> +reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +
> +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
> +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
> +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
> +
> +# define MSTATUS_SIE 0x00000002
> +# define CSR_SSTATUS 0x100
> +
> +ASM_PFX(RiscVDisableSupervisorModeInterrupts):
> + li a1, MSTATUS_SIE
> + csrc CSR_SSTATUS, a1
> + ret
> +
> +ASM_PFX(RiscVEnableSupervisorModeInterrupt):
> + li a1, MSTATUS_SIE
> + csrs CSR_SSTATUS, a1
> + ret
> +
> +ASM_PFX(RiscVGetSupervisorModeInterrupts):
> + csrr a0, CSR_SSTATUS
> + andi a0, a0, MSTATUS_SIE
> + ret
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> new file mode 100644
> index 0000000..e72dd7f
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> @@ -0,0 +1,55 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// Set/Long jump for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +# define REG_S sd
> +# define REG_L ld
> +# define SZREG 8
> +.align 3
> + .globl SetJump
> +
> +SetJump:
> + REG_S ra, 0*SZREG(a0)
> + REG_S s0, 1*SZREG(a0)
> + REG_S s1, 2*SZREG(a0)
> + REG_S s2, 3*SZREG(a0)
> + REG_S s3, 4*SZREG(a0)
> + REG_S s4, 5*SZREG(a0)
> + REG_S s5, 6*SZREG(a0)
> + REG_S s6, 7*SZREG(a0)
> + REG_S s7, 8*SZREG(a0)
> + REG_S s8, 9*SZREG(a0)
> + REG_S s9, 10*SZREG(a0)
> + REG_S s10,11*SZREG(a0)
> + REG_S s11,12*SZREG(a0)
> + REG_S sp, 13*SZREG(a0)
> + li a0, 0
> + ret
> +
> + .globl InternalLongJump
> +InternalLongJump:
> + REG_L ra, 0*SZREG(a0)
> + REG_L s0, 1*SZREG(a0)
> + REG_L s1, 2*SZREG(a0)
> + REG_L s2, 3*SZREG(a0)
> + REG_L s3, 4*SZREG(a0)
> + REG_L s4, 5*SZREG(a0)
> + REG_L s5, 6*SZREG(a0)
> + REG_L s6, 7*SZREG(a0)
> + REG_L s7, 8*SZREG(a0)
> + REG_L s8, 9*SZREG(a0)
> + REG_L s9, 10*SZREG(a0)
> + REG_L s10,11*SZREG(a0)
> + REG_L s11,12*SZREG(a0)
> + REG_L sp, 13*SZREG(a0)
> +
> + add a0, s0, 0
> + add a1, s1, 0
> + add a2, s2, 0
> + add a3, s3, 0
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> new file mode 100644
> index 0000000..012d913
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> @@ -0,0 +1,264 @@
> +/** @file
> + RISC-V specific functionality for (un)aligned memory read/write.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "BaseLibInternals.h"
> +
> +/**
> + Reads a 16-bit value from memory that may be unaligned.
> +
> + This function returns the 16-bit value pointed to by Buffer. The
> + function guarantees that the read operation does not produce an
> alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 16-bit value that may be unaligned.
> +
> + @return The 16-bit value read from Buffer.
> +
> +**/
> +UINT16
> +EFIAPI
> +ReadUnaligned16 (
> + IN CONST UINT16 *Buffer
> + )
> +{
> + UINT16 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = sizeof (UINT16) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 16-bit value to memory that may be unaligned.
> +
> + This function writes the 16-bit value specified by Value to Buffer.
> + Value is returned. The function guarantees that the write operation
> + does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 16-bit value that may be unaligned.
> + @param Value 16-bit value to write to Buffer.
> +
> + @return The 16-bit value to write to Buffer.
> +
> +**/
> +UINT16
> +EFIAPI
> +WriteUnaligned16 (
> + OUT UINT16 *Buffer,
> + IN UINT16 Value
> + )
> +{
> + INT8 Count;
> + UINT16 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT16) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 24-bit value from memory that may be unaligned.
> +
> + This function returns the 24-bit value pointed to by Buffer. The
> + function guarantees that the read operation does not produce an
> alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 24-bit value that may be unaligned.
> +
> + @return The 24-bit value read from Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +ReadUnaligned24 (
> + IN CONST UINT32 *Buffer
> + )
> +{
> + UINT32 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 2, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 24-bit value to memory that may be unaligned.
> +
> + This function writes the 24-bit value specified by Value to Buffer.
> + Value is returned. The function guarantees that the write operation
> + does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 24-bit value that may be unaligned.
> + @param Value 24-bit value to write to Buffer.
> +
> + @return The 24-bit value to write to Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +WriteUnaligned24 (
> + OUT UINT32 *Buffer,
> + IN UINT32 Value
> + )
> +{
> + INT8 Count;
> + UINT32 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < 3 ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit value from memory that may be unaligned.
> +
> + This function returns the 32-bit value pointed to by Buffer. The
> + function guarantees that the read operation does not produce an
> alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 32-bit value that may be unaligned.
> +
> + @return The 32-bit value read from Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +ReadUnaligned32 (
> + IN CONST UINT32 *Buffer
> + )
> +{
> + UINT32 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = sizeof (UINT32) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 32-bit value to memory that may be unaligned.
> +
> + This function writes the 32-bit value specified by Value to Buffer.
> + Value is returned. The function guarantees that the write operation
> + does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 32-bit value that may be unaligned.
> + @param Value The 32-bit value to write to Buffer.
> +
> + @return The 32-bit value to write to Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +WriteUnaligned32 (
> + OUT UINT32 *Buffer,
> + IN UINT32 Value
> + )
> +{
> + INT8 Count;
> + UINT32 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT32) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit value from memory that may be unaligned.
> +
> + This function returns the 64-bit value pointed to by Buffer. The
> + function guarantees that the read operation does not produce an
> alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 64-bit value that may be unaligned.
> +
> + @return The 64-bit value read from Buffer.
> +
> +**/
> +UINT64
> +EFIAPI
> +ReadUnaligned64 (
> + IN CONST UINT64 *Buffer
> + )
> +{
> + UINT64 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = sizeof (UINT64) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 64-bit value to memory that may be unaligned.
> +
> + This function writes the 64-bit value specified by Value to Buffer.
> + Value is returned. The function guarantees that the write operation
> + does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 64-bit value that may be unaligned.
> + @param Value The 64-bit value to write to Buffer.
> +
> + @return The 64-bit value to write to Buffer.
> +
> +**/
> +UINT64
> +EFIAPI
> +WriteUnaligned64 (
> + OUT UINT64 *Buffer,
> + IN UINT64 Value
> + )
> +{
> + INT8 Count;
> + UINT64 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT64) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
[not found] ` <15C6EB9A049FF8A4.24160@groups.io>
@ 2019-09-24 1:54 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:54 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC Maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>
> RISC-V MMIO library instance. RISC-V only supports memory map I/O.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601
> +++++++++++++++++++++
> 2 files changed, 607 insertions(+), 2 deletions(-) create mode 100644
> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> index 457cce9..fbb568e 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> @@ -2,13 +2,14 @@
> # Instance of I/O Library using compiler intrinsics.
> #
> # I/O Library that uses compiler intrinsics to perform IN and OUT instructions
> -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO
> requests.
> +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated into
> MMIO requests.
> # MMIO requests are forwarded directly to memory. For EBC, I/O port
> requests # ASSERT().
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> #
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@
>
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> @@ -55,6 +56,9 @@
> [Sources.AARCH64]
> IoLibArm.c
>
> +[Sources.RISCV64]
> + IoLibRiscV.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> new file mode 100644
> index 0000000..789928b
> --- /dev/null
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> @@ -0,0 +1,601 @@
> +/** @file
> + Common I/O Library routines for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made
> + available under the terms and conditions of the BSD License which
> + accompanies this distribution. The full text of the license may be
> + found at
> + INVALID URI REMOVED
> 3A__opensource.org_lic
> + enses_bsd-
> 2Dlicense.php&d=DwIBAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4V
> +
> gi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=iiSSnOQeIcsWwWSNpZOq8Z8FU
> hf-ZXBIKZ
> + -k2RKjtSw&s=JXcajsH1FkirFiWOe0VJ0qh1HCibFZd6W9j87D8J98k&e=
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> +**/
> +
> +#include "BaseIoLibIntrinsicInternal.h"
> +
> +/**
> + Reads an 8-bit MMIO register.
> +
> + Reads the 8-bit MMIO register specified by Address. The 8-bit read
> + value is returned. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioRead8 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT8*)Address;
> +}
> +
> +/**
> + Writes an 8-bit MMIO register.
> +
> + Writes the 8-bit MMIO register specified by Address with the value
> + specified by Value and returns Value. This function must guarantee
> + that all MMIO read and write operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + )
> +{
> + *(volatile UINT8 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 16-bit MMIO register.
> +
> + Reads the 16-bit MMIO register specified by Address. The 16-bit read
> + value is returned. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioRead16 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT16 *)Address;
> +}
> +
> +/**
> + Writes a 16-bit MMIO register.
> +
> + Writes the 16-bit MMIO register specified by Address with the value
> + specified by Value and returns Value. This function must guarantee
> + that all MMIO read and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + *(volatile UINT16 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit MMIO register.
> +
> + Reads the 32-bit MMIO register specified by Address. The 32-bit read
> + value is returned. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioRead32 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT32 *)Address;
> +}
> +
> +/**
> + Writes a 32-bit MMIO register.
> +
> + Writes the 32-bit MMIO register specified by Address with the value
> + specified by Value and returns Value. This function must guarantee
> + that all MMIO read and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The valu return *(volatile UINT8*)Address;
> + to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + *(volatile UINT32 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit MMIO register.
> +
> + Reads the 64-bit MMIO register specified by Address. The 64-bit read
> + value is returned. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioRead64 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT64 *)Address;
> +}
> +
> +/**
> + Writes a 64-bit MMIO register.
> +
> + Writes the 64-bit MMIO register specified by Address with the value
> + specified by Value and returns Value. This function must guarantee
> + that all MMIO read and write operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + *(volatile UINT64 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads an 8-bit I/O port.
> +
> + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +IoRead8 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes an 8-bit I/O port.
> +
> + Writes the 8-bit I/O port specified by Port with the value specified
> + by Value and returns Value. This function must guarantee that all I/O
> + read and write operations are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +
> +UINT8
> +EFIAPI
> +IoWrite8 (
> + IN UINTN Port,
> + IN UINT8 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 16-bit I/O port.
> +
> + Reads the 16-bit I/O port specified by Port. The 16-bit read value is
> returned.
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoRead16 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 16-bit I/O port.
> +
> + Writes the 16-bit I/O port specified by Port with the value specified
> + by Value and returns Value. This function must guarantee that all I/O
> + read and write operations are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoWrite16 (
> + IN UINTN Port,
> + IN UINT16 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 32-bit I/O port.
> +
> + Reads the 32-bit I/O port specified by Port. The 32-bit read value is
> returned.
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoRead32 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 32-bit I/O port.
> +
> + Writes the 32-bit I/O port specified by Port with the value specified
> + by Value and returns Value. This function must guarantee that all I/O
> + read and write operations are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoWrite32 (
> + IN UINTN Port,
> + IN UINT32 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 64-bit I/O port.
> +
> + Reads the 64-bit I/O port specified by Port. The 64-bit read value is
> returned.
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoRead64 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 64-bit I/O port.
> +
> + Writes the 64-bit I/O port specified by Port with the value specified
> + by Value and returns Value. This function must guarantee that all I/O
> + read and write operations are serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written to the I/O port.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoWrite64 (
> + IN UINTN Port,
> + IN UINT64 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads an 8-bit I/O port fifo into a block of memory.
> +
> + Reads the 8-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is stored in the
> + provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into an 8-bit I/O port fifo.
> +
> + Writes the 8-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is retrieved
> + from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations
> + are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 16-bit I/O port fifo into a block of memory.
> +
> + Reads the 16-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is stored in the
> + provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 16-bit I/O port fifo.
> +
> + Writes the 16-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is retrieved
> + from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations
> + are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 32-bit I/O port fifo into a block of memory.
> +
> + Reads the 32-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is stored in the
> + provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations
> + are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 32-bit I/O port fifo.
> +
> + Writes the 32-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is retrieved
> + from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations
> + are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + ASSERT (FALSE);
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo
[not found] ` <15C6EB9B3E887BEB.29693@groups.io>
@ 2019-09-24 1:55 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:55 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Zhichao Gao, Ray Ni
CC maintainers
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29]
> MdeModulePkg/Logo
>
> Add RISCV64 Arch.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdeModulePkg/Logo/Logo.inf | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
> index 0182025..243748c 100644
> --- a/MdeModulePkg/Logo/Logo.inf
> +++ b/MdeModulePkg/Logo/Logo.inf
> @@ -19,7 +19,7 @@
> #
> # The following information is for reference only and not required by the
> build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Binaries]
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
[not found] ` <15C6EB9A40C408A0.24160@groups.io>
@ 2019-09-24 1:56 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:56 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
>
> Support RISC-V image relocation.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> +++++++++++++++++++++
> 5 files changed, 152 insertions(+), 1 deletion(-) create mode 100644
> MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> index 07bb62f..97e0ff4 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> @@ -1,6 +1,6 @@
> /** @file
> Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
> - only supports relocating IA32, x64, IPF, and EBC images.
> + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
>
> Caution: This file requires additional review when modified.
> This library will have external input - PE/COFF image.
> @@ -17,6 +17,7 @@
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development
> + LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> index 395c140..b190494 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> @@ -3,6 +3,7 @@
> # The IPF version library supports loading IPF and EBC PE/COFF image.
> # The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
> # The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> +# The RISC-V version library support loading RISC-V images.
> #
> # Caution: This module requires additional review when modified.
> # This library will have external input - PE/COFF image.
> @@ -11,6 +12,7 @@
> #
> # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@
> [Sources.ARM]
> Arm/PeCoffLoaderEx.c
>
> +[Sources.RISCV64]
> + RiscV/PeCoffLoaderEx.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> index b0ea702..8616ca3 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> @@ -4,6 +4,7 @@
> // The IPF version library supports loading IPF and EBC PE/COFF image.
> // The IA32 version library support loading IA32, X64 and EBC PE/COFF
> images.
> // The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> +// The RISC-V version library support loading RISC-V32 and RISC-V64
> PE/COFF images.
> //
> // Caution: This module requires additional review when modified.
> // This library will have external input - PE/COFF image.
> @@ -12,6 +13,7 @@
> //
> // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> //
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git
> a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> index b74277f..9c33703 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> @@ -2,6 +2,7 @@
> Declaration of internal functions in PE/COFF Lib.
>
> Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> + rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> new file mode 100644
> index 0000000..8eb37f9
> --- /dev/null
> +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> @@ -0,0 +1,142 @@
> +/** @file
> + PE/Coff loader for RISC-V PE image
> +
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> +"BasePeCoffLibInternals.h"
> +#include <Library/BaseLib.h>
> +
> +//
> +// RISC-V definition.
> +//
> +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> #define
> +RISCV_CONST_HIGH_PART(VALUE) \
> + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> +
> +/**
> + Performs an RISC-V specific relocation fixup and is a no-op on
> + other instruction sets.
> + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
> + types. We have to know the lower 12-bit fixup first then we can deal
> + carry over on high 20-bit fixup. So we log the high 20-bit in
> + FixupData.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeCoffLoaderRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + UINT32 Value;
> + UINT32 Value2;
> + UINT32 *RiscVHi20Fixup;
> +
> + switch ((*Reloc) >> 12) {
> + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> +
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
> + (RV_X (*(UINT32 *)Fixup, 0, 20));
> + }
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32
> *)Fixup, 25, 7) << 5));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> + Value &= RISCV_IMM_REACH - 1;
> + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |
> (RV_X(Value, 5, 7) << 25)));
> + }
> + break;
> +
> + default:
> + return RETURN_UNSUPPORTED;
> +
> + }
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Returns TRUE if the machine type of PE/COFF image is supported.
> +Supported
> + does not mean the image can be executed it means the PE/COFF loader
> +supports
> + loading and relocating of the image type. It's up to the caller to
> +support
> + the entry point.
> +
> + @param Machine Machine type from the PE Header.
> +
> + @return TRUE if this PE/COFF loader can load the image
> +
> +**/
> +BOOLEAN
> +PeCoffLoaderImageFormatSupported (
> + IN UINT16 Machine
> + )
> +{
> + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine ==
> IMAGE_FILE_MACHINE_RISCV64)) {
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Performs an Itanium-based specific re-relocation fixup and is a no-op
> +on other
> + instruction sets. This is used to re-relocated the image into the EFI
> +virtual
> + space for runtime calls.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeHotRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + return RETURN_UNSUPPORTED;
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg
[not found] ` <15C6EB9B872A5B83.24160@groups.io>
@ 2019-09-24 1:57 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:57 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Siyuan Fu, Jiaxin Wu
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg
>
> Add RISCV64 Arch.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> NetworkPkg/Network.dsc.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
> index c7f4328..b484f9b 100644
> --- a/NetworkPkg/Network.dsc.inc
> +++ b/NetworkPkg/Network.dsc.inc
> @@ -34,7 +34,7 @@
> !include NetworkPkg/NetworkComponents.dsc.inc
>
> !else
> -[Components.IA32, Components.X64, Components.ARM,
> Components.AARCH64]
> +[Components.IA32, Components.X64, Components.ARM,
> Components.AARCH64,
> +Components.RISCV64]
> !include NetworkPkg/NetworkComponents.dsc.inc
>
> !endif
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
[not found] ` <15C6EB99CBC780B5.2053@groups.io>
@ 2019-09-24 1:57 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:57 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29]
> MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
> implementation.
>
> Implement RISC-V cache maintenance functions in
> BaseCacheMaintenanceLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseCacheMaintenanceLib.inf | 4 +
> .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250
> +++++++++++++++++++++
> 2 files changed, 254 insertions(+)
> create mode 100644
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
>
> diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> index ec7feec..d9bfa04 100644
> ---
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> +++
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> @@ -6,6 +6,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@
> [Sources.AARCH64]
> ArmCache.c
>
> +[Sources.RISCV64]
> + RiscVCache.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> new file mode 100644
> index 0000000..d8e4665
> --- /dev/null
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -0,0 +1,250 @@
> +/** @file
> + RISC-V specific functionality for cache.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + RISC-V invalidate instruction cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateInstCacheAsm (
> + VOID
> + );
> +
> +/**
> + RISC-V invalidate data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateDataCacheAsm (
> + VOID
> + );
> +
> +/**
> + Invalidates the entire instruction cache in cache coherency domain of
> +the
> + calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateInstructionCache (
> + VOID
> + )
> +{
> + RiscVInvalidateInstCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of instruction cache lines in the cache coherency
> +domain
> + of the calling CPU.
> +
> + Invalidates the instruction cache lines specified by Address and
> + Length. If Address is not aligned on a cache line boundary, then
> + entire instruction cache line containing Address is invalidated. If
> + Address + Length is not aligned on a cache line boundary, then the
> + entire instruction cache line containing Address + Length -1 is
> + invalidated. This function may choose to invalidate the entire
> + instruction cache if that is more efficient than invalidating the
> + specified range. If Length is 0, then no instruction cache lines are
> invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the instruction cache lines to
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> +
> + @param Length The number of bytes to invalidate from the instruction
> cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateInstructionCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back and invalidates the entire data cache in cache coherency
> +domain
> + of the calling CPU.
> +
> + Writes back and invalidates the entire data cache in cache coherency
> + domain of the calling CPU. This function guarantees that all dirty
> + cache lines are written back to system memory, and also invalidates
> + all the data cache lines in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackInvalidateDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> +__FUNCTION__)); }
> +
> +/**
> + Writes back and invalidates a range of data cache lines in the cache
> + coherency domain of the calling CPU.
> +
> + Writes back and invalidates the data cache lines specified by Address
> + and Length. If Address is not aligned on a cache line boundary, then
> + entire data cache line containing Address is written back and
> + invalidated. If Address + Length is not aligned on a cache line
> + boundary, then the entire data cache line containing Address + Length
> + -1 is written back and invalidated. This function may choose to write
> + back and invalidate the entire data cache if that is more efficient
> + than writing back and invalidating the specified range. If Length is
> + 0, then no data cache lines are written back and invalidated. Address is
> returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back
> and
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> + @param Length The number of bytes to write back and invalidate from
> the
> + data cache.
> +
> + @return Address of cache invalidation.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackInvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back the entire data cache in cache coherency domain of the
> +calling
> + CPU.
> +
> + Writes back the entire data cache in cache coherency domain of the
> + calling CPU. This function guarantees that all dirty cache lines are
> + written back to system memory. This function may also invalidate all
> + the data cache lines in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__)); }
> +
> +/**
> + Writes back a range of data cache lines in the cache coherency domain
> +of the
> + calling CPU.
> +
> + Writes back the data cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is written back. If Address + Length is
> + not aligned on a cache line boundary, then the entire data cache line
> + containing Address + Length -1 is written back. This function may
> + choose to write back the entire data cache if that is more efficient than
> writing back the specified range.
> + If Length is 0, then no data cache lines are written back. This
> + function may also invalidate all the data cache lines in the
> + specified range of the cache coherency domain of the calling CPU. Address
> is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing
> + mode, then Address is a virtual address.
> + @param Length The number of bytes to write back from the data cache.
> +
> + @return Address of cache written in main memory.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Invalidates the entire data cache in cache coherency domain of the
> +calling
> + CPU.
> +
> + Invalidates the entire data cache in cache coherency domain of the
> + calling CPU. This function must be used with care because dirty cache
> + lines are not written back to system memory. It is typically used for
> + cache diagnostics. If the CPU does not support invalidation of the
> + entire data cache, then a write back and invalidate operation should be
> performed on the entire data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateDataCache (
> + VOID
> + )
> +{
> + RiscVInvalidateDataCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of data cache lines in the cache coherency domain
> +of the
> + calling CPU.
> +
> + Invalidates the data cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is invalidated. If Address + Length is
> + not aligned on a cache line boundary, then the entire data cache line
> + containing Address + Length -1 is invalidated. This function must
> + never invalidate any cache lines outside the specified range. If
> + Length is 0, then no data cache lines are invalidated. Address is
> + returned. This function must be used with care because dirty cache
> + lines are not written back to system memory. It is typically used for
> + cache diagnostics. If the CPU does not support invalidation of a data
> + cache range, then a write back and invalidate operation should be
> performed on the data cache range.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to invalidate. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing mode,
> + then Address is a virtual address.
> + @param Length The number of bytes to invalidate from the data cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
[not found] ` <15C6EB9A9BD83853.2053@groups.io>
@ 2019-09-24 1:58 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:58 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29]
> MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
>
> Implement RISC-V CPU related functions in BaseCpuLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++-
> MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++--
> MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++
> 3 files changed, 27 insertions(+), 3 deletions(-) create mode 100644
> MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
>
> diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> index a7cb381..a95d8a0 100644
> --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> @@ -7,6 +7,7 @@
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> #
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -24,7 +25,7 @@
>
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources.IA32]
> @@ -59,6 +60,9 @@
> AArch64/CpuFlushTlb.asm | MSFT
> AArch64/CpuSleep.asm | MSFT
>
> +[Sources.RISCV64]
> + RiscV/Cpu.S
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> index fc95cda..85d56ce 100644
> --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> @@ -1,12 +1,13 @@
> // /** @file
> // Instance of CPU Library for various architecture.
> //
> -// CPU Library implemented using ASM functions for IA-32 and X64,
> +// CPU Library implemented using ASM functions for IA-32, X64 and
> +RISCV64,
> // PAL CALLs for IPF, and empty functions for EBC.
> //
> // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR> //
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> //
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -15,5 +16,5 @@
>
> #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU
> Library for various architectures"
>
> -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library
> implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and
> empty functions for EBC."
> +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library
> implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for
> IPF, and empty functions for EBC."
>
> diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> new file mode 100644
> index 0000000..703b1e8
> --- /dev/null
> +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> @@ -0,0 +1,19 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// CpuSleep for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +.data
> +.align 3
> +.section .text
> +
> +.global ASM_PFX(_CpuSleep)
> +
> +ASM_PFX(_CpuSleep):
> + wfi
> + ret
> +
> +
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
[not found] ` <15C6EB9AEB7BB057.24160@groups.io>
@ 2019-09-24 1:58 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:58 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29]
> MdePkg/BaseSynchronizationLib: RISC-V cache related code.
>
> Support RISC-V cache related functions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseSynchronizationLib.inf | 6 +
> .../RiscV64/Synchronization.c | 183 +++++++++++++++++++++
> .../RiscV64/SynchronizationAsm.S | 78 +++++++++
> 3 files changed, 267 insertions(+)
> create mode 100644
> MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> create mode 100644
> MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
>
> diff --git
> a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> index 446bc19..c16ef9d 100755
> --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> @@ -3,6 +3,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,11 @@
> AArch64/Synchronization.S | GCC
> AArch64/Synchronization.asm | MSFT
>
> +[Sources.RISCV64]
> + Synchronization.c
> + RiscV64/Synchronization.c | GCC
> + RiscV64/SynchronizationAsm.S
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git
> a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> new file mode 100644
> index 0000000..e210b74
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> @@ -0,0 +1,183 @@
> +/** @file
> + Implementation of synchronization functions on RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include <Library/DebugLib.h>
> +
> +UINT32
> +SyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT32 CompareValue,
> + IN UINT32 ExchangeValue
> +);
> +
> +UINT64
> +SyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> +);
> +
> +UINT32
> +SyncSyncIncrement32 (
> + IN volatile UINT32 *Value
> + );
> +
> +UINT32
> +SyncSyncDecrement32 (
> + IN volatile UINT32 *Value
> + );
> +
> +/**
> + Performs an atomic compare exchange operation on a 16-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 16-bit unsigned
> + integer specified by Value. If Value is equal to CompareValue, then
> + Value is set to ExchangeValue and CompareValue is returned. If Value
> + is not equal to CompareValue, then Value is returned. The compare
> + exchange operation must be performed using MP safe mechanisms.
> +
> + @param Value A pointer to the 16-bit value for the
> + compare exchange operation.
> + @param CompareValue 16-bit value used in compare operation.
> + @param ExchangeValue 16-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT16
> +EFIAPI
> +InternalSyncCompareExchange16 (
> + IN volatile UINT16 *Value,
> + IN UINT16 CompareValue,
> + IN UINT16 ExchangeValue
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO
> +operation\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs an atomic compare exchange operation on a 32-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 32-bit unsigned
> + integer specified by Value. If Value is equal to CompareValue, then
> + Value is set to ExchangeValue and CompareValue is returned. If Value
> + is not equal to CompareValue, then Value is returned. The compare
> + exchange operation must be performed using MP safe mechanisms.
> +
> + @param Value A pointer to the 32-bit value for the
> + compare exchange operation.
> + @param CompareValue 32-bit value used in compare operation.
> + @param ExchangeValue 32-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT32 CompareValue,
> + IN UINT32 ExchangeValue
> + )
> +{
> +
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural
> address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncCompareExchange32(Value, CompareValue, ExchangeValue); }
> +
> +/**
> + Performs an atomic compare exchange operation on a 64-bit unsigned
> integer.
> +
> + Performs an atomic compare exchange operation on the 64-bit unsigned
> + integer specified by Value. If Value is equal to CompareValue, then
> + Value is set to ExchangeValue and CompareValue is returned. If Value is
> not equal to CompareValue, then Value is returned.
> + The compare exchange operation must be performed using MP safe
> mechanisms.
> +
> + @param Value A pointer to the 64-bit value for the compare exchange
> + operation.
> + @param CompareValue 64-bit value used in compare operation.
> + @param ExchangeValue 64-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT64
> +EFIAPI
> +InternalSyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT64)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural
> address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncCompareExchange64 (Value, CompareValue, ExchangeValue); }
> +
> +/**
> + Performs an atomic increment of an 32-bit unsigned integer.
> +
> + Performs an atomic increment of the 32-bit unsigned integer specified
> + by Value and returns the incremented value. The increment operation
> + must be performed using MP safe mechanisms. The state of the return
> + value is not guaranteed to be MP safe.
> +
> + @param Value A pointer to the 32-bit value to increment.
> +
> + @return The incremented value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncIncrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural
> address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncSyncIncrement32 (Value);
> +}
> +
> +/**
> + Performs an atomic decrement of an 32-bit unsigned integer.
> +
> + Performs an atomic decrement of the 32-bit unsigned integer specified
> + by Value and returns the decrement value. The decrement operation
> + must be performed using MP safe mechanisms. The state of the return
> + value is not guaranteed to be MP safe.
> +
> + @param Value A pointer to the 32-bit value to decrement.
> +
> + @return The decrement value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncDecrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural
> address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncSyncDecrement32 (Value);
> +}
> diff --git
> a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> new file mode 100644
> index 0000000..943e274
> --- /dev/null
> +++
> b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> @@ -0,0 +1,78 @@
> +//---------------------------------------------------------------------
> +---------
> +//
> +// RISC-V synchronization functions.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> +BSD-2-Clause-Patent //
> +//---------------------------------------------------------------------
> +---------
> +#include <Base.h>
> +
> +.data
> +
> +.text
> +.align 3
> +
> +.global ASM_PFX(SyncCompareExchange32)
> +.global ASM_PFX(SyncCompareExchange64)
> +.global ASM_PFX(SyncSyncIncrement32)
> +.global ASM_PFX(SyncSyncDecrement32)
> +
> +//
> +// ompare and xchange a 32-bit value.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (SyncCompareExchange32):
> + lr.w a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.w a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit:
> + mv a0, a3
> + ret
> +
> +.global ASM_PFX(SyncCompareExchange64)
> +
> +//
> +// Compare and xchange a 64-bit value.
> +//
> +// @param a0 : Pointer to 64-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (SyncCompareExchange64):
> + lr.d a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.d a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit2:
> + mv a0, a3
> + ret
> +
> +//
> +// Performs an atomic increment of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (SyncSyncIncrement32):
> + li a1, 1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> +
> +//
> +// Performs an atomic decrement of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (SyncSyncDecrement32):
> + li a1, -1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
[not found] ` <15C6EB99608359A3.24160@groups.io>
@ 2019-09-24 1:59 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 1:59 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Michael D Kinney
CC maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29]
> MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
> implementation.
>
> Implement RISC-V cache maintenance functions in
> BaseCacheMaintenanceLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseCacheMaintenanceLib.inf | 4 +
> .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250
> +++++++++++++++++++++
> 2 files changed, 254 insertions(+)
> create mode 100644
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
>
> diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> index ec7feec..d9bfa04 100644
> ---
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> +++
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in
> f
> @@ -6,6 +6,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@
> [Sources.AARCH64]
> ArmCache.c
>
> +[Sources.RISCV64]
> + RiscVCache.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> new file mode 100644
> index 0000000..d8e4665
> --- /dev/null
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -0,0 +1,250 @@
> +/** @file
> + RISC-V specific functionality for cache.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + RISC-V invalidate instruction cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateInstCacheAsm (
> + VOID
> + );
> +
> +/**
> + RISC-V invalidate data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateDataCacheAsm (
> + VOID
> + );
> +
> +/**
> + Invalidates the entire instruction cache in cache coherency domain of
> +the
> + calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateInstructionCache (
> + VOID
> + )
> +{
> + RiscVInvalidateInstCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of instruction cache lines in the cache coherency
> +domain
> + of the calling CPU.
> +
> + Invalidates the instruction cache lines specified by Address and
> + Length. If Address is not aligned on a cache line boundary, then
> + entire instruction cache line containing Address is invalidated. If
> + Address + Length is not aligned on a cache line boundary, then the
> + entire instruction cache line containing Address + Length -1 is
> + invalidated. This function may choose to invalidate the entire
> + instruction cache if that is more efficient than invalidating the
> + specified range. If Length is 0, then no instruction cache lines are
> invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the instruction cache lines to
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> +
> + @param Length The number of bytes to invalidate from the instruction
> cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateInstructionCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back and invalidates the entire data cache in cache coherency
> +domain
> + of the calling CPU.
> +
> + Writes back and invalidates the entire data cache in cache coherency
> + domain of the calling CPU. This function guarantees that all dirty
> + cache lines are written back to system memory, and also invalidates
> + all the data cache lines in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackInvalidateDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> +__FUNCTION__)); }
> +
> +/**
> + Writes back and invalidates a range of data cache lines in the cache
> + coherency domain of the calling CPU.
> +
> + Writes back and invalidates the data cache lines specified by Address
> + and Length. If Address is not aligned on a cache line boundary, then
> + entire data cache line containing Address is written back and
> + invalidated. If Address + Length is not aligned on a cache line
> + boundary, then the entire data cache line containing Address + Length
> + -1 is written back and invalidated. This function may choose to write
> + back and invalidate the entire data cache if that is more efficient
> + than writing back and invalidating the specified range. If Length is
> + 0, then no data cache lines are written back and invalidated. Address is
> returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back
> and
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> + @param Length The number of bytes to write back and invalidate from
> the
> + data cache.
> +
> + @return Address of cache invalidation.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackInvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back the entire data cache in cache coherency domain of the
> +calling
> + CPU.
> +
> + Writes back the entire data cache in cache coherency domain of the
> + calling CPU. This function guarantees that all dirty cache lines are
> + written back to system memory. This function may also invalidate all
> + the data cache lines in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__)); }
> +
> +/**
> + Writes back a range of data cache lines in the cache coherency domain
> +of the
> + calling CPU.
> +
> + Writes back the data cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is written back. If Address + Length is
> + not aligned on a cache line boundary, then the entire data cache line
> + containing Address + Length -1 is written back. This function may
> + choose to write back the entire data cache if that is more efficient than
> writing back the specified range.
> + If Length is 0, then no data cache lines are written back. This
> + function may also invalidate all the data cache lines in the
> + specified range of the cache coherency domain of the calling CPU. Address
> is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing
> + mode, then Address is a virtual address.
> + @param Length The number of bytes to write back from the data cache.
> +
> + @return Address of cache written in main memory.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Invalidates the entire data cache in cache coherency domain of the
> +calling
> + CPU.
> +
> + Invalidates the entire data cache in cache coherency domain of the
> + calling CPU. This function must be used with care because dirty cache
> + lines are not written back to system memory. It is typically used for
> + cache diagnostics. If the CPU does not support invalidation of the
> + entire data cache, then a write back and invalidate operation should be
> performed on the entire data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateDataCache (
> + VOID
> + )
> +{
> + RiscVInvalidateDataCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of data cache lines in the cache coherency domain
> +of the
> + calling CPU.
> +
> + Invalidates the data cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is invalidated. If Address + Length is
> + not aligned on a cache line boundary, then the entire data cache line
> + containing Address + Length -1 is invalidated. This function must
> + never invalidate any cache lines outside the specified range. If
> + Length is 0, then no data cache lines are invalidated. Address is
> + returned. This function must be used with care because dirty cache
> + lines are not written back to system memory. It is typically used for
> + cache diagnostics. If the CPU does not support invalidation of a data
> + cache range, then a write back and invalidate operation should be
> performed on the data cache range.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to invalidate. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing mode,
> + then Address is a virtual address.
> + @param Length The number of bytes to invalidate from the data cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> + return Address;
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
[not found] ` <15C6EB9D6C0EC3B0.29693@groups.io>
@ 2019-09-24 2:00 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 2:00 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Bi, Dandan
CC maintainer
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29]
> MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
>
> Implementation of RISC-V platform level DxeIPL
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++-
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71
> ++++++++++++++++++++++
> RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 +++++++++++++
> 3 files changed, 124 insertions(+), 1 deletion(-) create mode 100644
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index 98bc17f..5532323 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -7,6 +7,7 @@
> #
> # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> #
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ # #
> The following information is for reference only and not required by the build
> tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> AARCH64 RISCV64
> #
>
> [Sources]
> @@ -49,6 +50,9 @@
> [Sources.ARM, Sources.AARCH64]
> Arm/DxeLoadFunc.c
>
> +[Sources.RISCV64]
> + RiscV64/DxeLoadFunc.c
> +
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> @@ -56,6 +60,9 @@
> [Packages.ARM, Packages.AARCH64]
> ArmPkg/ArmPkg.dec
>
> +[Packages.RISCV64]
> + RiscVPkg/RiscVPkg.dec
> +
> [LibraryClasses]
> PcdLib
> MemoryAllocationLib
> @@ -75,6 +82,10 @@
> [LibraryClasses.ARM, LibraryClasses.AARCH64]
> ArmMmuLib
>
> +[LibraryClasses.RISCV64]
> + RiscVPlatformDxeIplLib
> + RiscVOpensbiLib
> +
> [Ppis]
> gEfiDxeIplPpiGuid ## PRODUCES
> gEfiPeiDecompressPpiGuid ## PRODUCES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> new file mode 100644
> index 0000000..d3c7f9d
> --- /dev/null
> +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> @@ -0,0 +1,71 @@
> +/** @file
> + RISC-V specific functionality for DxeLoad.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "DxeIpl.h"
> +#include "Library/RiscVPlatformDxeIpl.h"
> +
> +typedef
> +VOID*
> +(EFIAPI *DXEENTRYPOINT) (
> + IN VOID *HobStart
> + );
> +
> +/**
> + Transfers control to DxeCore.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +VOID
> +HandOffToDxeCore (
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + )
> +{
> + VOID *BaseOfStack;
> + VOID *TopOfStack;
> + EFI_STATUS Status;
> + //
> + //
> + // Allocate 128KB for the Stack
> + //
> + BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
> + ASSERT (BaseOfStack != NULL);
> +
> + //
> + // Compute the top of the stack we were allocated. Pre-allocate a
> + UINTN // for safety.
> + //
> + TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES
> + (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); TopOfStack =
> + ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
> +
> + //
> + // End of PEI phase signal
> + //
> + Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Update the contents of BSP stack HOB to reflect the real stack info
> passed to DxeCore.
> + //
> + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack,
> + STACK_SIZE);
> +
> + DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at
> + %x\n", BaseOfStack, TopOfStack));
> +
> + //
> + // Transfer the control to the entry point of DxeCore.
> + //
> + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack,
> +DxeCoreEntryPoint, HobList); }
> +
> diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> new file mode 100644
> index 0000000..4763397
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> @@ -0,0 +1,41 @@
> +/** @file
> + Header file of RISC-V platform DXE IPL
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All
> + rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _RISC_V_PLATFORM_DXEIPL_H_
> +#define _RISC_V_PLATFORM_DXEIPL_H_
> +
> +typedef struct {
> + VOID *TopOfStack;
> + VOID *BaseOfStack;
> + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;
> + EFI_PEI_HOB_POINTERS HobList;
> +} OPENSBI_SWITCH_MODE_CONTEXT;
> +
> +/**
> + RISC-V platform DXE IPL to DXE core handoff process.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param BaseOfStack Base address of stack
> + @param TopOfStack Top address of stack
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +
> +VOID
> +RiscVPlatformHandOffToDxeCore (
> + IN VOID *BaseOfStack,
> + IN VOID *TopOfStack,
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + );
> +#endif
> +
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
[not found] ` <15C6EB98AD6CCCEB.24160@groups.io>
@ 2019-09-24 2:01 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 2:01 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Hao A Wu
CC reviewers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29]
> MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
>
> Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9
> +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git
> a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> index 9da4507..84f3688 100644
> ---
> a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +++
> b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> @@ -5,6 +5,7 @@
> # the capsule runtime services are ready.
> #
> # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> +rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -21,20 +22,20
> @@ # # The following information is for reference only and not required by
> the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> CapsuleService.c
> CapsuleService.h
>
> -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
> +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64,
> +Sources.RISCV64]
> SaveLongModeContext.c
>
> -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
> +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64,
> +Sources.RISCV64]
> CapsuleCache.c
>
> -[Sources.Ia32, Sources.X64, Sources.EBC]
> +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
> CapsuleReset.c
>
> [Sources.ARM, Sources.AARCH64]
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
[not found] ` <15C6EB9F04387439.29693@groups.io>
@ 2019-09-24 2:02 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-09-24 2:02 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Liming Gao, Bob Feng
Add maintainers
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29]
> BaseTools/Scripts
>
> Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds causes
> PE32 relocation error.
> This is the temporaty solution untill we find the root casue.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> BaseTools/Scripts/GccBaseRiscV.lds | 66
> ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
>
> diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> b/BaseTools/Scripts/GccBaseRiscV.lds
> new file mode 100644
> index 0000000..7f9fae6
> --- /dev/null
> +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> @@ -0,0 +1,66 @@
> +/** @file
> +
> + Unified linker script for GCC based builds
> +
> + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> + Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +SECTIONS {
> +
> + /*
> + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> sequence of
> + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
> + * between 32-bit and 64-bit builds). The actual start of the .text section
> + * will be rounded up based on its actual alignment.
> + */
> + . = PECOFF_HEADER_SIZE;
> +
> + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.text .text.* .stub .gnu.linkonce.t.*)
> + *(.rodata .rodata.* .gnu.linkonce.r.*)
> + *(.got .got.*)
> +
> + /*
> + * The contents of AutoGen.c files are constant from the POV of the
> program,
> + * but most of its contents end up in .data or .bss by default since few of
> + * the variable definitions that get emitted are declared as CONST.
> + */
> + *:AutoGen.obj(.data.g*Guid)
> + }
> +
> + /*
> + * The alignment of the .data section should be less than or equal to the
> + * alignment of the .text section. This ensures that the relative offset
> + * between these sections is the same in the ELF and the PE/COFF versions
> of
> + * this binary.
> + */
> + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.data .data.* .gnu.linkonce.d.*)
> + *(.bss .bss.*)
> + }
> +
> + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + KEEP (*(.eh_frame))
> + }
> +
> + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + *(.rela .rela.*)
> + }
> +
> + /DISCARD/ : {
> + *(.note.GNU-stack)
> + *(.gnu_debuglink)
> + *(.interp)
> + *(.dynsym)
> + *(.dynstr)
> + *(.dynamic)
> + *(.hash)
> + *(.comment)
> + *(COMMON)
> + }
> +}
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
@ 2019-09-26 20:50 ` Leif Lindholm
2019-10-15 6:31 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 20:50 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:51AM +0800, Abner Chang wrote:
> Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds
> causes PE32 relocation error.
> This is the temporaty solution untill we find the root casue.
I presume you mean that having a separate version for RISCV is
temporary? I am OK with this for now. However, the diff is not what I
would expect. Can you verify that the difference is only what you
actually need?
For example:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> BaseTools/Scripts/GccBaseRiscV.lds | 66 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
>
> diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBaseRiscV.lds
> new file mode 100644
> index 0000000..7f9fae6
> --- /dev/null
> +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> @@ -0,0 +1,66 @@
> +/** @file
> +
> + Unified linker script for GCC based builds
> +
> + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +SECTIONS {
> +
> + /*
> + * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
> + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
> + * between 32-bit and 64-bit builds). The actual start of the .text section
> + * will be rounded up based on its actual alignment.
> + */
> + . = PECOFF_HEADER_SIZE;
> +
> + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.text .text.* .stub .gnu.linkonce.t.*)
> + *(.rodata .rodata.* .gnu.linkonce.r.*)
> + *(.got .got.*)
> +
> + /*
> + * The contents of AutoGen.c files are constant from the POV of the program,
> + * but most of its contents end up in .data or .bss by default since few of
> + * the variable definitions that get emitted are declared as CONST.
> + */
The above comment block looks completely different - in GccBase.lds:
/*
* The contents of AutoGen.c files are mostly constant from the POV of the
* program, but most of it ends up in .data or .bss by default since few of
* the variable definitions that get emitted are declared as CONST.
* Unfortunately, we cannot pull it into the .text section entirely, since
* patchable PCDs are also emitted here, but we can at least move all of the
* emitted GUIDs here.
*/
> + *:AutoGen.obj(.data.g*Guid)
> + }
> +
> + /*
> + * The alignment of the .data section should be less than or equal to the
> + * alignment of the .text section. This ensures that the relative offset
> + * between these sections is the same in the ELF and the PE/COFF versions of
> + * this binary.
> + */
> + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.data .data.* .gnu.linkonce.d.*)
> + *(.bss .bss.*)
> + }
> +
> + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + KEEP (*(.eh_frame))
> + }
> +
> + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
The above line is, I believe, the only necessary change for your workaround?
> + *(.rela .rela.*)
> + }
> +
The original one as the following:
.hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
KEEP (*(.hii))
}
I do not think including this could be the cause of any issues.
Also, GccBase.lds includes here:
/*
* Retain the GNU build id but in a non-allocatable section so GenFw
* does not copy it into the PE/COFF image.
*/
.build-id (INFO) : { *(.note.gnu.build-id) }
> + /DISCARD/ : {
> + *(.note.GNU-stack)
> + *(.gnu_debuglink)
> + *(.interp)
> + *(.dynsym)
> + *(.dynstr)
> + *(.dynamic)
> + *(.hash)
In GccBase.lds:
*(.hash .gnu.hash)
/
Leif
> + *(.comment)
> + *(COMMON)
> + }
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
@ 2019-09-26 22:09 ` Leif Lindholm
2019-10-15 6:18 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:09 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:50AM +0800, Abner Chang wrote:
> BaseTools changes for building EDK2 RISC-V platform.
> The changes made to build_rule.template is to avoid build errors
> cause by GCC711RISCV tool chain.
Thank you, this is much cleaner.
There are however some issues in this patch that prevent building on
any platform. Please ensure to give a local build test before
submitting a 3.
First of all, this still does not contain the addition to
BaseTools/Source/Python/Common/buildoptions.py that I mentioned in
https://edk2.groups.io/g/devel/message/47036 - meaning that attempting
to build anything for RISCV64 gives an error.
Other minor issues reviewed inline:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> BaseTools/Conf/build_rule.template | 62 ++---
> BaseTools/Conf/tools_def.template | 64 ++++-
> BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
> BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++++++++++++++-
> BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> BaseTools/Source/Python/Common/DataType.py | 7 +-
> 10 files changed, 659 insertions(+), 45 deletions(-)
>
> diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
> index db06d3a..fab3926 100755
> --- a/BaseTools/Conf/build_rule.template
> +++ b/BaseTools/Conf/build_rule.template
> @@ -1,6 +1,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> +# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
>
> @@ -145,14 +146,6 @@
> <Command.GCC, Command.RVCT>
> "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src}
>
> -[C-Header-File]
> - <InputFile>
> - *.h, *.H
> -
> - <OutputFile>
> -
> - <Command>
> -
Header files are good, please don't delete them.
> [Assembly-Code-File.COMMON.COMMON]
> <InputFile.MSFT, InputFile.INTEL, InputFile.RVCT>
> ?.asm, ?.Asm, ?.ASM
> @@ -266,10 +259,10 @@
> <Command.GCC>
> $(RM) ${dst}
> "$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST)
> -
> +
Please address these line ending issues..
> <Command.RVCT>
> "$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST)
> -
> +
> <Command.RVCTCYGWIN>
> # $(OBJECT_FILES_LIST) has wrong paths for cygwin
> "$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES)
> @@ -304,8 +297,8 @@
>
> <Command.XCODE>
> "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> -
> -
> +
> +
> [Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64, Static-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM]
> <InputFile>
> *.lib
> @@ -321,6 +314,21 @@
> "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
>
>
> +[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32]
> + <InputFile>
> + *.lib
> +
> + <ExtraDependency>
> + $(MAKE_FILE)
> +
> + <OutputFile>
> + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> +
> + <Command.GCC>
> + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
This line looks to me like the only thing that is actually changed
here, and I am not convinced it is necessary.
"$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS) $(DLINK2_FLAGS)
On the ARM/AARCH64 side, we use gcc as the DLINK, and pass the
required flags through to the linker with -Wl. Please have a look and
try to rework at that end rather than fundamentally revamping the
basic build rules differently for RISCV than other architectures.
Basically, please discard all changes to this file, apply the below
diff, and rework the flags to resolve the builds. (Basically, add a
bunch of -Wl,)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index b96b394dc441..b6d5c25ba5b5 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2286,11 +2286,10 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
##################
# GCC5 RISCV64 definitions
##################
-*_GCC5_RISCV64_OBJCOPY_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
*_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
-*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
-*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
-*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
+*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ar
+*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
*_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
*_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
*_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> + "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> +
> +
> [Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION]
> <InputFile>
> *.lib
> @@ -346,8 +354,8 @@
>
> <Command.XCODE>
> "$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> -
> -
> +
> +
> [Dynamic-Library-File]
> <InputFile>
> ?.dll
> @@ -360,7 +368,7 @@
> $(CP) ${dst} $(DEBUG_DIR)
> $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> - -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> + -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> <Command.GCC>
> $(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
> $(OBJCOPY) --strip-unneeded -R .eh_frame ${src}
> @@ -375,7 +383,7 @@
> $(CP) ${dst} $(DEBUG_DIR)
> $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> -
> +
> <Command.XCODE>
> # tool to convert Mach-O to PE/COFF
> "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).pecoff
> @@ -414,13 +422,13 @@
> <Command.MSFT, Command.INTEL>
> Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
> "$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
>
> <Command.GCC>
> Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
> "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
>
> [C-Code-File.AcpiTable]
> @@ -462,14 +470,14 @@
> "$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(CC_FLAGS) $(ASLCC_FLAGS) $(INC) ${src}
> "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(GENFW_FLAGS)
> -
> - <Command.XCODE>
> +
> + <Command.XCODE>
> "$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASLCC_FLAGS) $(INC) ${src}
> "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff
> "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff $(GENFW_FLAGS)
> -
> -
> +
> +
> [Masm16-Code-File]
> <InputFile>
> ?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16
> @@ -492,14 +500,14 @@
> Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
> "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) $(LIBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group
> -
> +
> <Command.XCODE>
> "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
> Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
> "$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${dst}
> -
> +
>
> [Nasm-to-Binary-Code-File]
> <InputFile>
> @@ -635,8 +643,8 @@
> <Command.GCC>
> "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
> "$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
> -
> +
> <Command.XCODE, Command.RVCT>
> GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
> -
> -
> +
> +
> diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
> index 8f0e6cb..54c3dc5 100755
> --- a/BaseTools/Conf/tools_def.template
> +++ b/BaseTools/Conf/tools_def.template
> @@ -3,7 +3,7 @@
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
> # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
> -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> +# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -231,11 +231,12 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
> # Intel(r) ACPI Compiler from
> # https://acpica.org/downloads
> # GCC5 -Linux,Windows- Requires:
> -# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
> +# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
> # Optional:
> # Required to build platforms or ACPI tables:
> # Intel(r) ACPI Compiler from
> # https://acpica.org/downloads
> +#
> # CLANG35 -Linux,Windows- Requires:
> # Clang v3.5 or later, and GNU binutils targeting aarch64-linux-gnu or arm-linux-gnueabi
> # Optional:
> @@ -1735,6 +1736,7 @@ DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386
> DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
> DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
> DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
> +DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv - B riscv64 --rename-section .data=.hii
The above line requires two changes in order to work. The first one is
the two spaces between the - and the B. The second is that "riscv64"
is not accepted by the toolchain. "riscv" works.
>
> DEFINE GCC48_ALL_CC_FLAGS = -g -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
> DEFINE GCC48_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-n,-q,--gc-sections -z common-page-size=0x20
> @@ -1806,6 +1808,21 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS = DEF(GCC49_ARM_ASLDLINK_FLAGS)
> DEFINE GCC5_AARCH64_ASLDLINK_FLAGS = DEF(GCC49_AARCH64_ASLDLINK_FLAGS)
> DEFINE GCC5_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -fno-lto
>
> +DEFINE GCC5_RISCV_ALL_CC_FLAGS = -g -fshort-wchar -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -c -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
> +DEFINE GCC5_RISCV_ALL_DLINK_COMMON = -nostdlib -n -q --gc-sections -z common-page-size=0x40
> +DEFINE GCC5_RISCV_ALL_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
> +DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS = --defsym=PECOFF_HEADER_SIZE=0x220 --script=$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds
> +DEFINE GCC5_RISCV_ALL_ASM_FLAGS = -c -x assembler -imacros $(DEST_DIR_DEBUG)/AutoGen.h
> +DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
> +
> +DEFINE GCC5_RISCV64_ARCH = rv64imafdc
> +DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable
> +DEFINE GCC5_RISCV32_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
> +DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64
> +DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -melf64lriscv --oformat=elf64-littleriscv --no-relax
> +DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
> +DEFINE GCC5_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
> +
> ####################################################################################
> #
> # GCC 4.8 - This configuration is used to compile under Linux to produce
> @@ -2247,6 +2264,49 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
> NOOPT_GCC5_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -O0
> NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
>
> +###################################################################################
> +####################################################################################
> +#
> +# GCC RISC-V This configuration is used to compile under Linux to produce
> +# PE/COFF binaries using GCC RISC-V tool chain
> +#
> +####################################################################################
> +
> +#*_GCC5_*_*_FAMILY = GCC
> +
> +#*_GCC5_*_MAKE_PATH = DEF(GCC49_IA32_PREFIX)make
> +#*_GCC5_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
> +#*_GCC5_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
> +#*_GCC5_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> +#*_GCC5_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
> +#*_GCC5_*_APP_FLAGS =
> +#*_GCC5_*_ASL_FLAGS = DEF(IASL_FLAGS)
> +#*_GCC5_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
> +
> +##################
> +# GCC5 RISCV64 definitions
> +##################
> +*_GCC5_RISCV64_OBJCOPY_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
> +*_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
> +*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> +*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> +*_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_ASLCC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_ASLPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_RC_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
> +
> +*_GCC5_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> +*_GCC5_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
> +*_GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS)
> +*_GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) -save-temps
> +*_GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV64_DLINK_FLAGS)
> +*_GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV64_DLINK2_FLAGS)
> +*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
> +*_GCC5_RISCV64_OBJCOPY_FLAGS =
> +
> ####################################################################################
> #
> # CLANG35 - This configuration is used to compile under Linux to produce
> diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
> index e7566b3..640f7a1 100644
> --- a/BaseTools/Source/C/Common/BasePeCoff.c
> +++ b/BaseTools/Source/C/Common/BasePeCoff.c
> @@ -4,6 +4,7 @@
>
> Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage (
> IN UINT64 Adjust
> );
>
> +RETURN_STATUS
> +PeCoffLoaderRelocateRiscVImage (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + );
> +
> STATIC
> RETURN_STATUS
> PeCoffLoaderGetPeHeader (
> @@ -174,7 +183,8 @@ Returns:
> ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
> ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
> ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
> - ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
> + ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
> + ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
> if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
> //
> // There are two types of ARM images. Pure ARM and ARM/Thumb.
> @@ -802,6 +812,9 @@ Returns:
> case EFI_IMAGE_MACHINE_ARMT:
> Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
> break;
> + case EFI_IMAGE_MACHINE_RISCV64:
> + Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
> + break;
> default:
> Status = RETURN_UNSUPPORTED;
> break;
> diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> index e367836..36797d9 100644
> --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> @@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups
>
> Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> --*/
> @@ -61,6 +62,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define IMM64_SIGN_INST_WORD_POS_X 27
> #define IMM64_SIGN_VAL_POS_X 63
>
> +//
> +// RISC-V definition.
> +//
> +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> +#define RISCV_IMM_BITS 12
> +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> +#define RISCV_CONST_HIGH_PART(VALUE) \
> + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> +
> +UINT32 *RiscVHi20Fixup = NULL;
> +
> RETURN_STATUS
> PeCoffLoaderRelocateIa32Image (
> IN UINT16 *Reloc,
> @@ -93,6 +105,89 @@ Returns:
> return RETURN_UNSUPPORTED;
> }
>
> +/*++
> +
> +Routine Description:
> +
> + Performs an RISC-V specific relocation fixup
> +
> +Arguments:
> +
> + Reloc - Pointer to the relocation record
> +
> + Fixup - Pointer to the address to fix up
> +
> + FixupData - Pointer to a buffer to log the fixups
> +
> + Adjust - The offset to adjust the fixup
> +
> +Returns:
> +
> + Status code
> +
> +--*/
> +RETURN_STATUS
> +PeCoffLoaderRelocateRiscVImage (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + UINT32 Value;
> + UINT32 Value2;
> + UINT32 OrgValue;
> +
> + OrgValue = *(UINT32 *) Fixup;
> + OrgValue = OrgValue;
> + switch ((*Reloc) >> 12) {
> + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> + RiscVHi20Fixup = (UINT32 *) Fixup;
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> + if (RiscVHi20Fixup != NULL) {
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
> + (RV_X (*(UINT32 *)Fixup, 0, 20));
> + }
> + RiscVHi20Fixup = NULL;
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> + if (RiscVHi20Fixup != NULL) {
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> + Value &= RISCV_IMM_REACH - 1;
> + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
> + }
> + RiscVHi20Fixup = NULL;
> + break;
> +
> + default:
> + return EFI_UNSUPPORTED;
> +
> + }
> + return RETURN_SUCCESS;
> +}
>
> /**
> Pass in a pointer to an ARM MOVT or MOVW immediate instruction and
> diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> index 908740d..fdbdd42 100644
> --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> @@ -4,6 +4,7 @@ This file contains the internal functions required to generate a Firmware Volume
> Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> Portions Copyright (c) 2016 HP Development Company, L.P.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000
>
> BOOLEAN mArm = FALSE;
> +BOOLEAN mRiscV = FALSE;
> STATIC UINT32 MaxFfsAlignment = 0;
> BOOLEAN VtfFileFlag = FALSE;
>
> @@ -2274,6 +2276,104 @@ Returns:
> }
>
> EFI_STATUS
> +UpdateRiscvResetVectorIfNeeded (
> + MEMORY_FILE *FvImage,
> + FV_INFO *FvInfo
> + )
> +/*++
> +
> +Routine Description:
> + This parses the FV looking for SEC and patches that address into the
> + beginning of the FV header.
> +
> + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> +
> +Arguments:
> + FvImage Memory file for the FV memory image/
> + FvInfo Information read from INF file.
> +
> +Returns:
> +
> + EFI_SUCCESS Function Completed successfully.
> + EFI_ABORTED Error encountered.
> + EFI_INVALID_PARAMETER A required parameter was NULL.
> + EFI_NOT_FOUND PEI Core file not found.
> +
> +--*/
> +{
> + EFI_STATUS Status;
> + UINT16 MachineType;
> + EFI_FILE_SECTION_POINTER SecPe32;
> + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> +
> + UINT32 bSecCore;
> + UINT32 tmp;
> +
> +
> + //
> + // Verify input parameters
> + //
> + if (FvImage == NULL || FvInfo == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + //
> + // Initialize FV library
> + //
> + InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> +
> + //
> + // Find the Sec Core
> + //
> + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> + if(EFI_ERROR(Status)) {
> + printf("skip because Secutiry Core not found\n");
> + return EFI_SUCCESS;
> + }
> +
> + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> +
> + Status = GetCoreMachineType(SecPe32, &MachineType);
> + if(EFI_ERROR(Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC core.");
> + return EFI_ABORTED;
> + }
> +
> + if (MachineType != EFI_IMAGE_MACHINE_RISCV64) {
> + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
> + return EFI_ABORTED;
> + }
> +
> + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
> + if(EFI_ERROR(Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
> + return EFI_ABORTED;
> + }
> +
> + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long long) SecCoreEntryAddress);
> + VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo->BaseAddress);
> + bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
> + VerboseMsg("offset = 0x%llX", bSecCore);
> +
> + if(bSecCore > 0x0fffff) {
> + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of start of the FV");
> + return EFI_ABORTED;
> + }
> +
> + tmp = bSecCore;
> + bSecCore = 0;
> + //J-type
> + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> + bSecCore |= 0x6F; //JAL opcode
> +
> + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> GetPe32Info (
> IN UINT8 *Pe32,
> OUT UINT32 *EntryPoint,
> @@ -2365,7 +2465,8 @@ Returns:
> // Verify machine type is supported
> //
> if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
> - (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
> + (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
> + (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
> return EFI_UNSUPPORTED;
> }
> @@ -2808,7 +2909,8 @@ Returns:
> Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad file between the last file and the VTF file.");
> goto Finish;
> }
> - if (!mArm) {
> +
> + if (!mArm && !mRiscV) {
> //
> // Update reset vector (SALE_ENTRY for IPF)
> // Now for IA32 and IA64 platform, the fv which has bsf file must have the
> @@ -2843,6 +2945,22 @@ Returns:
> FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> }
>
> + if (mRiscV) {
> + //
> + // Update RISCV reset vector.
> + //
> + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
> + if (EFI_ERROR (Status)) {
> + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
> + goto Finish;
> + }
> + //
> + // Update Checksum for FvHeader
> + //
> + FvHeader->Checksum = 0;
> + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> + }
> +
> //
> // Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
> //
> @@ -3430,6 +3548,10 @@ Returns:
> mArm = TRUE;
> }
>
> + if (ImageContext.Machine == EFI_IMAGE_MACHINE_RISCV64) {
> + mRiscV = TRUE;
> + }
> +
> //
> // Keep Image Context for PE image in FV
> //
> @@ -3583,7 +3705,7 @@ Returns:
> ImageContext.DestinationAddress = NewPe32BaseAddress;
> Status = PeCoffLoaderRelocateImage (&ImageContext);
> if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s", FileName);
> + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s Status=%d", FileName, Status);
> free ((VOID *) MemoryImagePointer);
> return Status;
> }
> diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
> index 46089ff..4095b7c 100644
> --- a/BaseTools/Source/C/GenFw/Elf32Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
> @@ -3,6 +3,7 @@ Elf32 Convert solution
>
> Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -141,8 +142,8 @@ InitializeElf32 (
> Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
> return FALSE;
> }
> - if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM))) {
> - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_ARM");
> + if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM) || (mEhdr->e_machine == EM_RISCV))) {
> + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32 machine.");
> return FALSE;
> }
> if (mEhdr->e_version != EV_CURRENT) {
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
> index 3d6319c..2aa09fd 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -3,6 +3,7 @@ Elf64 convert solution
>
> Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include "ElfConvert.h"
> #include "Elf64Convert.h"
>
> +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> +#define RISCV_IMM_BITS 12
> +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> +#define RISCV_CONST_HIGH_PART(VALUE) \
> + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> +
> STATIC
> VOID
> ScanSections64 (
> @@ -153,8 +160,8 @@ InitializeElf64 (
> Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
> return FALSE;
> }
> - if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64))) {
> - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or EM_AARCH64");
> + if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
> + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machine.");
> return FALSE;
> }
> if (mEhdr->e_version != EV_CURRENT) {
> @@ -481,6 +488,7 @@ ScanSections64 (
> switch (mEhdr->e_machine) {
> case EM_X86_64:
> case EM_AARCH64:
> + case EM_RISCV64:
> mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
> break;
> default:
> @@ -690,6 +698,11 @@ ScanSections64 (
> NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
> NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> break;
> + case EM_RISCV64:
> + NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
> + NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> + break;
> +
> default:
> VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
> NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
> @@ -769,6 +782,11 @@ WriteSections64 (
> Elf_Shdr *SecShdr;
> UINT32 SecOffset;
> BOOLEAN (*Filter)(Elf_Shdr *);
> + UINT32 Value;
> + UINT32 Value2;
> + UINT8 *Pass1Targ = NULL;
> + Elf_Shdr *Pass1Sym = NULL;
> + Elf64_Half Pass1SymSecIndex = 0;
> Elf64_Addr GOTEntryRva;
>
> //
> @@ -893,13 +911,14 @@ WriteSections64 (
> if (SymName == NULL) {
> SymName = (const UINT8 *)"<unknown>";
> }
> + if (mEhdr->e_machine != EM_RISCV64) {
This needs a comment explaining why this does not apply to RISCV.
> + Error (NULL, 0, 3000, "Invalid",
> + "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
> + "For example, absolute and undefined symbols are not supported.",
> + mInImageName, SymName, Sym->st_value);
>
> - Error (NULL, 0, 3000, "Invalid",
> - "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
> - "For example, absolute and undefined symbols are not supported.",
> - mInImageName, SymName, Sym->st_value);
> -
> - exit(EXIT_FAILURE);
> + exit(EXIT_FAILURE);
> + }
> }
> SymShdr = GetShdrByIndex(Sym->st_shndx);
>
> @@ -1114,6 +1133,128 @@ WriteSections64 (
> default:
> Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
> }
> + } else if (mEhdr->e_machine == EM_RISCV64) {
Yeah, this code block is just *waaaay* too big.
Please break it out into its own helper function.
> + switch (ELF_R_TYPE(Rel->r_info)) {
> + case R_RISCV_NONE:
> + break;
> + case R_RISCV_32:
> + *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
> + break;
> + case R_RISCV_64:
> + *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> + break;
> + case R_RISCV_HI20:
> + Pass1Targ = Targ;
> + Pass1Sym = SymShdr;
> + Pass1SymSecIndex = Sym->st_shndx;
> + break;
> + case R_RISCV_LO12_I:
> + if (Pass1Sym == SymShdr && Pass1Targ != NULL && Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
> + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
> + *(UINT32 *)Targ = (RV_X (Value, 0, 12) << 20) | \
> + (RV_X (*(UINT32 *)Targ, 0, 20));
> + }
> + Pass1Sym = NULL;
> + Pass1Targ = NULL;
> + Pass1SymSecIndex = 0;
> + break;
> +
> + case R_RISCV_LO12_S:
> + if (Pass1Sym == SymShdr && Pass1Targ != NULL && Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
> + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UINT32 *)Targ, 25, 7) << 5));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
> +
> + Value2 = *(UINT32 *)Targ & 0x01fff07f;
> + Value &= RISCV_IMM_REACH - 1;
> + *(UINT32 *)Targ = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
> + }
> + Pass1Sym = NULL;
> + Pass1Targ = NULL;
> + Pass1SymSecIndex = 0;
> + break;
> +
> + case R_RISCV_PCREL_HI20:
> + Pass1Targ = Targ;
> + Pass1Sym = SymShdr;
> + Pass1SymSecIndex = Sym->st_shndx;
> +
> + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
> + break;
> + case R_RISCV_PCREL_LO12_I:
> + if (Pass1Targ != NULL && Pass1Sym != NULL && Pass1SymSecIndex != 0) {
> + int i;
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
> + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> + if(Value & (RISCV_IMM_REACH/2)) {
> + Value |= ~(RISCV_IMM_REACH-1);
> + }
> + Value = Value - Pass1Sym->sh_addr + mCoffSectionsOffset[Pass1SymSecIndex];
> + if(-2048 > (INT32)Value) {
> + i = (-Value / 4096);
> + Value2 -= i;
> + Value += 4096 * i;
> + if(-2048 > (INT32)Value) {
> + Value2 -= 1;
> + Value += 4096;
> + }
> + }
> + else if( 2047 < (INT32)Value) {
> + i = (Value / 4096);
> + Value2 += i;
> + Value -= 4096 * i;
> + if(2047 < (INT32)Value) {
> + Value2 += 1;
> + Value -= 4096;
> + }
> + }
> +
> + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> + *(UINT32 *)Pass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)Pass1Targ, 0, 12));
> + }
> + Pass1Sym = NULL;
> + Pass1Targ = NULL;
> + Pass1SymSecIndex = 0;
> + break;
> +
> + case R_RISCV_ADD64:
> + case R_RISCV_SUB64:
> + case R_RISCV_ADD32:
> + case R_RISCV_SUB32:
> + case R_RISCV_BRANCH:
> + case R_RISCV_JAL:
> + case R_RISCV_GPREL_I:
> + case R_RISCV_GPREL_S:
> + case R_RISCV_CALL:
> + case R_RISCV_RVC_BRANCH:
> + case R_RISCV_RVC_JUMP:
> + case R_RISCV_RELAX:
> + case R_RISCV_SUB6:
> + case R_RISCV_SET6:
> + case R_RISCV_SET8:
> + case R_RISCV_SET16:
> + case R_RISCV_SET32:
> + break;
> +
> + default:
> + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
> + }
> } else {
> Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
> }
> @@ -1133,6 +1274,7 @@ WriteRelocations64 (
> UINT32 Index;
> EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
> EFI_IMAGE_DATA_DIRECTORY *Dir;
> + UINT32 RiscVRelType;
>
> for (Index = 0; Index < mEhdr->e_shnum; Index++) {
> Elf_Shdr *RelShdr = GetShdrByIndex(Index);
> @@ -1237,6 +1379,108 @@ WriteRelocations64 (
> default:
> Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
> }
> + } else if (mEhdr->e_machine == EM_RISCV64) {
> + RiscVRelType = ELF_R_TYPE(Rel->r_info);
> + switch (RiscVRelType) {
> + case R_RISCV_NONE:
> + break;
> +
> + case R_RISCV_32:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_HIGHLOW);
> + break;
> +
> + case R_RISCV_64:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_DIR64);
> + break;
> +
> + case R_RISCV_HI20:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_RISCV_HI20);
> + break;
> +
> + case R_RISCV_LO12_I:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_RISCV_LOW12I);
> + break;
> +
> + case R_RISCV_LO12_S:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_RISCV_LOW12S);
> + break;
> +
> + case R_RISCV_ADD64:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_SUB64:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_ADD32:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_SUB32:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_BRANCH:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_JAL:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_GPREL_I:
> + case R_RISCV_GPREL_S:
> + case R_RISCV_CALL:
> + case R_RISCV_RVC_BRANCH:
> + case R_RISCV_RVC_JUMP:
> + case R_RISCV_RELAX:
> + case R_RISCV_SUB6:
> + case R_RISCV_SET6:
> + case R_RISCV_SET8:
> + case R_RISCV_SET16:
> + case R_RISCV_SET32:
> + case R_RISCV_PCREL_HI20:
> + case R_RISCV_PCREL_LO12_I:
> + break;
> +
> + default:
> + printf ("Unsupported RISCV64 ELF relocation type 0x%x, offset: %lx\n", RiscVRelType, Rel->r_offset);
printf is not a supported output function in this file. Please use Error.
> + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
> + }
> } else {
> Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
> }
> diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
> index 15c9e33..1321f78 100644
> --- a/BaseTools/Source/C/GenFw/elf_common.h
> +++ b/BaseTools/Source/C/GenFw/elf_common.h
> @@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD
>
> Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
> @@ -178,6 +179,8 @@ typedef struct {
> #define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
> #define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
> #define EM_AARCH64 183 /* ARM 64bit Architecture */
> +#define EM_RISCV64 243 /* 64bit RISC-V Architecture */
> +#define EM_RISCV 244 /* 32bit RISC-V Architecture */
>
> /* Non-standard or deprecated. */
> #define EM_486 6 /* Intel i486. */
> @@ -979,5 +982,64 @@ typedef struct {
> #define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable. */
> #define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relative offset to GOT entry with REX prefix, relaxable. */
>
> +/*
> + * RISC-V relocation types
> + */
> +
> +/* Relocation types used by the dynamic linker */
> +#define R_RISCV_NONE 0
> +#define R_RISCV_32 1
> +#define R_RISCV_64 2
> +#define R_RISCV_RELATIVE 3
> +#define R_RISCV_COPY 4
> +#define R_RISCV_JUMP_SLOT 5
> +#define R_RISCV_TLS_DTPMOD32 6
> +#define R_RISCV_TLS_DTPMOD64 7
> +#define R_RISCV_TLS_DTPREL32 8
> +#define R_RISCV_TLS_DTPREL64 9
> +#define R_RISCV_TLS_TPREL32 10
> +#define R_RISCV_TLS_TPREL64 11
>
> +/* Relocation types not used by the dynamic linker */
> +#define R_RISCV_BRANCH 16
> +#define R_RISCV_JAL 17
> +#define R_RISCV_CALL 18
> +#define R_RISCV_CALL_PLT 19
> +#define R_RISCV_GOT_HI20 20
> +#define R_RISCV_TLS_GOT_HI20 21
> +#define R_RISCV_TLS_GD_HI20 22
> +#define R_RISCV_PCREL_HI20 23
> +#define R_RISCV_PCREL_LO12_I 24
> +#define R_RISCV_PCREL_LO12_S 25
> +#define R_RISCV_HI20 26
> +#define R_RISCV_LO12_I 27
> +#define R_RISCV_LO12_S 28
> +#define R_RISCV_TPREL_HI20 29
> +#define R_RISCV_TPREL_LO12_I 30
> +#define R_RISCV_TPREL_LO12_S 31
> +#define R_RISCV_TPREL_ADD 32
> +#define R_RISCV_ADD8 33
> +#define R_RISCV_ADD16 34
> +#define R_RISCV_ADD32 35
> +#define R_RISCV_ADD64 36
> +#define R_RISCV_SUB8 37
> +#define R_RISCV_SUB16 38
> +#define R_RISCV_SUB32 39
> +#define R_RISCV_SUB64 40
> +#define R_RISCV_GNU_VTINHERIT 41
> +#define R_RISCV_GNU_VTENTRY 42
> +#define R_RISCV_ALIGN 43
> +#define R_RISCV_RVC_BRANCH 44
> +#define R_RISCV_RVC_JUMP 45
> +#define R_RISCV_RVC_LUI 46
> +#define R_RISCV_GPREL_I 47
> +#define R_RISCV_GPREL_S 48
> +#define R_RISCV_TPREL_I 49
> +#define R_RISCV_TPREL_S 50
> +#define R_RISCV_RELAX 51
> +#define R_RISCV_SUB6 52
> +#define R_RISCV_SET6 53
> +#define R_RISCV_SET8 54
> +#define R_RISCV_SET16 55
> +#define R_RISCV_SET32 56
> #endif /* !_SYS_ELF_COMMON_H_ */
> diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> index 44037d1..2ed3008 100644
> --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> @@ -6,6 +6,7 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -41,6 +42,7 @@
> #define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
> #define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
> #define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
> +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
>
> //
> // Support old names for backward compatible
> @@ -50,6 +52,7 @@
> #define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
> #define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
> #define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
> +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
>
> #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
> #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
> @@ -504,7 +507,10 @@ typedef struct {
> #define EFI_IMAGE_REL_BASED_HIGHADJ 4
> #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
> #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
> +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
> #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
> #define EFI_IMAGE_REL_BASED_IA64_IMM64 9
> #define EFI_IMAGE_REL_BASED_DIR64 10
>
> diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
> index 8ae1bd2..fc23e8c 100644
> --- a/BaseTools/Source/Python/Common/DataType.py
> +++ b/BaseTools/Source/Python/Common/DataType.py
> @@ -3,6 +3,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> ##
> @@ -52,7 +53,9 @@ TAB_ARCH_ARM = 'ARM'
> TAB_ARCH_EBC = 'EBC'
> TAB_ARCH_AARCH64 = 'AARCH64'
>
> -ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_COMMON}
> +TAB_ARCH_RISCV64 = 'RISCV64'
> +
> +ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
>
> SUP_MODULE_BASE = 'BASE'
> SUP_MODULE_SEC = 'SEC'
> @@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE = {8:'=Q',
> 0:'=B',
> 16:""}
>
> -TAB_COMPILER_MSFT = 'MSFT'
> \ No newline at end of file
> +TAB_COMPILER_MSFT = 'MSFT'
Please either fix in a separate patch or leave out altogether.
/
Leif
> --
> 2.7.4
>
>
>
>
^ permalink raw reply related [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
` (43 preceding siblings ...)
[not found] ` <15C6EB9F04387439.29693@groups.io>
@ 2019-09-26 22:22 ` Leif Lindholm
2019-10-15 6:39 ` Abner Chang
44 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:22 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:25AM +0800, Abner Chang wrote:
> This branch "RISC-V-V2" is used to contribute RISC-V architecture on EDK2.
> Compare to the old branch "RISC-V", this branch "RISC-V-V2" is created based on
> the most recent edk2/master @37eef910. This is easier for reviewers to have
> clear ideas of edk2 code changes for RISC-V EDK2 implementation.
> Because of the code changes made on old branch "RISC-V" is stale and not
> compliant with the latest RISC-V spec, this new branch has the fresh changes
> for RISC-V EDK2 implementation.
>
> The main changes of these series of patches are,
> - Add RiscVPkg which conform with RISC-V Privilege Spec v1.10.
> - Incorporate and leverage RISC-V OpenSBI to provide EDK2 port OpenSBI library.
> - Provide RISC-V platform implementation specific drivers to EDK2 RISC-V platform
> package.
> - Provide generic RISC-V SMBIOS DXE drive to create SMBIOS type 4, 7 and 44 records,
> in which the SMBIOS type 44 record is introduced in SMBIOS spec 3.3.0.
>
> Abner Chang (29):
> RiscVPkg: RISC-V processor package.
> RiscVPkg/Include: Add header files of RISC-V CPU package
> RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
PatchCheck.py warns about long line in commit message.
> MdePkg: RISC-V RV64 binding in MdePkg
> MdePkg/Include: RISC-V definitions.
> MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
> MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
> MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
> implementation.
PatchCheck.py warns about long line in commit message.
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
> MdePkg/BaseSynchronizationLib: RISC-V cache related code.
> MdeModulePkg/Logo
> NetworkPkg
> RiscVPkg/Library: RISC-V CPU library
> RiscVPkg/Library: Add RISC-V exception library
> RiscVPkg/Library: Add RISC-V timer library
> RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
> RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
> MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
> RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service
> Table Pointer library
PatchCheck.py warns about long line in commit message.
> RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary
> Memory library
PatchCheck.py warns about long line in commit message.
/
Leif
> RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
> BaseTools: BaseTools changes for RISC-V platform.
> BaseTools/Scripts
> RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
> platforms.
> edk2-staging/RISC-V-V2: Add submodule
> edk2-staging/RISC-V-V2: Add ReadMe
> edk2-staging: Update Maintainers.txt
>
> .gitmodules | 16 +-
> BaseTools/Conf/build_rule.template | 62 ++-
> BaseTools/Conf/tools_def.template | 64 ++-
> BaseTools/Scripts/GccBaseRiscV.lds | 66 +++
> BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++
> BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++-
> BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++-
> BaseTools/Source/C/GenFw/elf_common.h | 62 +++
> .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> BaseTools/Source/Python/Common/DataType.py | 7 +-
> Maintainers.txt | 5 +
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +-
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 +++
> MdeModulePkg/Logo/Logo.inf | 2 +-
> .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +-
> MdePkg/Include/IndustryStandard/PeImage.h | 12 +
> MdePkg/Include/Library/BaseLib.h | 26 +
> MdePkg/Include/Protocol/DebugSupport.h | 55 ++
> MdePkg/Include/Protocol/PxeBaseCode.h | 4 +
> MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++
> MdePkg/Include/Uefi/UefiBaseType.h | 13 +
> MdePkg/Include/Uefi/UefiSpec.h | 5 +
> .../BaseCacheMaintenanceLib.inf | 4 +
> .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-
> MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
> MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +
> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
> MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
> MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +
> MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +
> MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 +
> MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 +
> MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +
> MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++
> .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++
> MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 ++
> .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +
> MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +
> MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 ++
> .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++
> MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++
> MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++
> .../BaseSynchronizationLib.inf | 6 +
> .../RiscV64/Synchronization.c | 183 +++++++
> .../RiscV64/SynchronizationAsm.S | 78 +++
> MdePkg/MdePkg.dec | 5 +-
> NetworkPkg/Network.dsc.inc | 2 +-
> RiscVEdk2Readme.md | 34 ++
> RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++
> RiscVPkg/Include/Library/RiscVCpuLib.h | 68 +++
> RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++
> .../Library/RiscVPlatformTempMemoryInitLib.h | 17 +
> RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++
> RiscVPkg/Include/RiscV.h | 72 +++
> RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++
> RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++
> RiscVPkg/Include/sbi/sbi.h | 96 ++++
> RiscVPkg/Include/sbi/sbi_bits.h | 17 +
> RiscVPkg/Include/sbi/sbi_types.h | 18 +
> .../PeiServicesTablePointerLibOpenSbi.inf | 38 ++
> .../PeiServicesTablePointerLibOpenSbi.uni | 23 +
> .../PeiServicesTablePointerOpenSbi.c | 121 +++++
> RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 ++++
> RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++
> .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 ++
> .../RiscVDxeIplHandoffLib.inf | 32 ++
> .../RiscVDxeIplHandoffOpenSbiLib.c | 102 ++++
> .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 ++
> .../RiscVExceptionLib/CpuExceptionHandler.S | 88 +++
> .../CpuExceptionHandlerDxeLib.inf | 42 ++
> .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++
> .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 +
> .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++
> .../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++
> .../Riscv64/TempMemInit.S | 26 +
> .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++
> RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++
> RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +
> RiscVPkg/RiscVPkg.dec | 42 ++
> RiscVPkg/RiscVPkg.uni | 13 +
> RiscVPkg/RiscVPkgExtra.uni | 13 +
> RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 +++++++++++
> RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++
> RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++
> RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
> RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 ++++++++++++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
> .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
> RiscVPkg/opensbi | 1 +
> 100 files changed, 6085 insertions(+), 66 deletions(-)
> create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
> create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> create mode 100644 RiscVEdk2Readme.md
> create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
> create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
> create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
> create mode 100644 RiscVPkg/Include/RiscV.h
> create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
> create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
> create mode 100644 RiscVPkg/Include/sbi/sbi.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
> create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
> create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
> create mode 100644 RiscVPkg/RiscVPkg.dec
> create mode 100644 RiscVPkg/RiscVPkg.uni
> create mode 100644 RiscVPkg/RiscVPkgExtra.uni
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> create mode 160000 RiscVPkg/opensbi
>
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
@ 2019-09-26 22:24 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:24 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:53AM +0800, Abner Chang wrote:
> Add submodule opensbi under RiscVPkg. The current supported opensbi
> version for RISC-V edk2 port is commit ID:ce228ee (tags/v0.4).
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .gitmodules | 16 ++++++++++------
> RiscVPkg/opensbi | 1 +
> 2 files changed, 11 insertions(+), 6 deletions(-)
> create mode 160000 RiscVPkg/opensbi
>
> diff --git a/.gitmodules b/.gitmodules
> index 508f0c1..6d3e28c 100644
> --- a/.gitmodules
> +++ b/.gitmodules
> @@ -1,6 +1,10 @@
> -[submodule "CryptoPkg/Library/OpensslLib/openssl"]
> - path = CryptoPkg/Library/OpensslLib/openssl
> - url = https://github.com/openssl/openssl
> -[submodule "SoftFloat"]
> - path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> - url = https://github.com/ucb-bar/berkeley-softfloat-3.git
> +[submodule "CryptoPkg/Library/OpensslLib/openssl"]
> + path = CryptoPkg/Library/OpensslLib/openssl
> + url = https://github.com/openssl/openssl
> +[submodule "SoftFloat"]
> + path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> + url = https://github.com/ucb-bar/berkeley-softfloat-3.git
Can you investigate why the pre-existing modules are deleted and
re-added as part of this patch?
Other than that, this is all good.
/
Leif
> +[submodule "RiscVPkg/opensbi"]
> + path = RiscVPkg/opensbi
> + url = https://github.com/riscv/opensbi.git
> +
> diff --git a/RiscVPkg/opensbi b/RiscVPkg/opensbi
> new file mode 160000
> index 0000000..ce228ee
> --- /dev/null
> +++ b/RiscVPkg/opensbi
> @@ -0,0 +1 @@
> +Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
@ 2019-09-26 22:26 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:26 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:26AM +0800, Abner Chang wrote:
> - Add RiscVPkg package which provides RISC-V processor related
> drivers and libraries.
> - Support RISC-V OpenSBI and RISC-V platforms
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/RiscVPkg.dec | 27 +++++++++++++++++++++++++++
> RiscVPkg/RiscVPkg.uni | 13 +++++++++++++
> RiscVPkg/RiscVPkgExtra.uni | 13 +++++++++++++
> 3 files changed, 53 insertions(+)
> create mode 100644 RiscVPkg/RiscVPkg.dec
> create mode 100644 RiscVPkg/RiscVPkg.uni
> create mode 100644 RiscVPkg/RiscVPkgExtra.uni
>
> diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
> new file mode 100644
> index 0000000..74314e8
> --- /dev/null
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -0,0 +1,27 @@
> +## @file RiscVPkg.dec
> +# This Package provides UEFI RISC-V modules and libraries.
> +#
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001b
> + PACKAGE_NAME = RiscVPkg
> + PACKAGE_UNI_FILE = RiscVPkg.uni
> + PACKAGE_GUID = 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1
> + PACKAGE_VERSION = 1.0
> +
> +[Includes]
> + Include
> + opensbi # OpebSBI header file reference ("include/sbi/...")
> + opensbi/include # Header file reference from opensbi files, ("sbi/...")
> + opensbi/lib/utils/libfdt
This line should no longer be needed, right?
If you delete it,
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +
> +[Guids]
> + gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
> +
> +[UserExtensions.TianoCore."ExtraFiles"]
> + RiscVPkgExtra.uni
> diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni
> new file mode 100644
> index 0000000..5ec7a99
> --- /dev/null
> +++ b/RiscVPkg/RiscVPkg.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +// RISC-V Package Localized Strings and Content.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V modules and libraries"
> +
> +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V modules and libraries."
> +
> diff --git a/RiscVPkg/RiscVPkgExtra.uni b/RiscVPkg/RiscVPkgExtra.uni
> new file mode 100644
> index 0000000..b50a6b4
> --- /dev/null
> +++ b/RiscVPkg/RiscVPkgExtra.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +// RISC-V Package Localized Strings and Content.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +#string STR_PROPERTIES_PACKAGE_NAME
> +#language en-US
> +"RiscV package"
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
@ 2019-09-26 22:29 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:29 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:27AM +0800, Abner Chang wrote:
> RISC-V package library definitions.
>
> IndustryStandard/RiscV.h
> -Add RiscV.h which conform with RISC-V Privilege Spec v1.10.
>
> RiscV.h
> -Definition of EDK2 RISC-V implementation.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++++++++++++++++++++++++++++
> RiscVPkg/Include/RiscV.h | 72 +++++++++++++++++++++
> 2 files changed, 174 insertions(+)
> create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
> create mode 100644 RiscVPkg/Include/RiscV.h
>
> diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h
> new file mode 100644
> index 0000000..d4d5002
> --- /dev/null
> +++ b/RiscVPkg/Include/IndustryStandard/RiscV.h
> @@ -0,0 +1,102 @@
> +/** @file
> + RISC-V package definitions.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _RISCV_INDUSTRY_STANDARD_H_
> +#define _RISCV_INDUSTRY_STANDARD_H_
Please delete leading _ in above two lines.
> +
> +#if defined (MDE_CPU_RISCV64)
> +#define RISC_V_XLEN_BITS 64
> +#else
> +#endif
> +
> +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
> +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
> +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
> +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
> +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
> +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
> +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
> +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
> +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
> +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
> +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
> +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
> +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
> +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
> +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
> +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
> +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
> +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
> +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
> +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
> +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
> +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
> +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
> +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
> +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
> +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
> +
> +//
> +// RISC-V CSR definitions.
> +//
> +//
> +// Machine information
> +//
> +#define RISCV_CSR_MACHINE_MVENDORID 0xF11
> +#define RISCV_CSR_MACHINE_MARCHID 0xF12
> +#define RISCV_CSR_MACHINE_MIMPID 0xF13
> +#define RISCV_CSR_MACHINE_HARRID 0xF14
> +//
> +// Machine Trap Setup.
> +//
> +#define RISCV_CSR_MACHINE_MSTATUS 0x300
> +#define RISCV_CSR_MACHINE_MISA 0x301
> +#define RISCV_CSR_MACHINE_MEDELEG 0x302
> +#define RISCV_CSR_MACHINE_MIDELEG 0x303
> +#define RISCV_CSR_MACHINE_MIE 0x304
> +#define RISCV_CSR_MACHINE_MTVEC 0x305
> +
> +#define RISCV_TIMER_COMPARE_BITS 32
> +//
> +// Machine Timer and Counter.
> +//
> +//#define RISCV_CSR_MACHINE_MTIME 0x701
> +//#define RISCV_CSR_MACHINE_MTIMEH 0x741
> +//
> +// Machine Trap Handling.
> +//
> +#define RISCV_CSR_MACHINE_MSCRATCH 0x340
> +#define RISCV_CSR_MACHINE_MEPC 0x341
> +#define RISCV_CSR_MACHINE_MCAUSE 0x342
> + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
> + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
> +#define RISCV_CSR_MACHINE_MBADADDR 0x343
> +#define RISCV_CSR_MACHINE_MIP 0x344
> +
> +//
> +// Machine Protection and Translation.
> +//
> +#define RISCV_CSR_MACHINE_MBASE 0x380
> +#define RISCV_CSR_MACHINE_MBOUND 0x381
> +#define RISCV_CSR_MACHINE_MIBASE 0x382
> +#define RISCV_CSR_MACHINE_MIBOUND 0x383
> +#define RISCV_CSR_MACHINE_MDBASE 0x384
> +#define RISCV_CSR_MACHINE_MDBOUND 0x385
> +//
> +// Machine Read-Write Shadow of Hypervisor Read-Only Registers
> +//
> +#define RISCV_CSR_HTIMEW 0xB01
> +#define RISCV_CSR_HTIMEHW 0xB81
> +//
> +// Machine Host-Target Interface (Non-Standard Berkeley Extension)
> +//
> +#define RISCV_CSR_MTOHOST 0x780
> +#define RISCV_CSR_MFROMHOST 0x781
> +
> +#endif
> diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h
> new file mode 100644
> index 0000000..1c3ab55
> --- /dev/null
> +++ b/RiscVPkg/Include/RiscV.h
> @@ -0,0 +1,72 @@
> +/** @file
> + RISC-V package definitions.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _RISCV_H_
> +#define _RISCV_H_
Please delete leading _ in above two lines.
With that change in both these files:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +
> +#include <IndustryStandard/RiscV.h>
> +
> +//
> +// Structure for 128-bit value
> +//
> +typedef struct {
> + UINT64 Value64_L;
> + UINT64 Value64_H;
> +} RISCV_UINT128;
> +
> +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
> +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
> +
> +///
> +/// Exception handlers in context.
> +///
> +typedef struct _EXCEPTION_HANDLER_CONTEXT {
> + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
> + EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
> + EFI_PHYSICAL_ADDRESS IllegalInstHander;
> + EFI_PHYSICAL_ADDRESS BreakpointHander;
> + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
> + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
> + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
> + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
> + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
> + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
> + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
> + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
> +} EXCEPTION_HANDLER_CONTEXT;
> +
> +///
> +/// Exception handlers in context.
> +///
> +typedef struct _INTERRUPT_HANDLER_CONTEXT {
> + EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
> + EFI_PHYSICAL_ADDRESS TimerIntHandler;
> +} INTERRUPT_HANDLER_CONTEXT;
> +
> +///
> +/// Interrupt handlers in context.
> +///
> +typedef struct _TRAP_HANDLER_CONTEXT {
> + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
> + INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
> +} TRAP_HANDLER_CONTEXT;
> +
> +///
> +/// Machine mode context used for saveing hart-local context.
> +///
> +typedef struct _RISCV_MACHINE_MODE_CONTEXT {
> + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
> + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler.
> + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
> + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
> + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler.
> + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode.
> +} RISCV_MACHINE_MODE_CONTEXT;
> +
> +#endif
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
@ 2019-09-26 22:41 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:41 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:28AM +0800, Abner Chang wrote:
> Add EDK2 RISC-V OpenSBI header files and opensbi-HOWTO.txt for users to build RISC-V platform with RISC-V OpenSBI library.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++++++++++++
> RiscVPkg/Include/sbi/sbi.h | 96 +++++++++++++++++++++++++++++++
> RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++
> RiscVPkg/Include/sbi/sbi_types.h | 18 ++++++
> 4 files changed, 169 insertions(+)
> create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
> create mode 100644 RiscVPkg/Include/sbi/sbi.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
>
> diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> new file mode 100644
> index 0000000..498faf4
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> @@ -0,0 +1,38 @@
> +/** @file
> + RISC-V OpesbSBI Platform Firmware context definition
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef _SBI_FIRMWARE_CONTEXT_H_
> +#define _SBI_FIRMWARE_CONTEXT_H_
Please drop leading _.
> +
> +#include <RiscV.h>
> +
> +#define RISC_V_MAX_HART_SUPPORTED 16
> +
> +//
> +// keep the structure member in 64-bit alignment.
> +//
> +#pragma pack(push)
> +#pragma pack(8)
I don't think this has any effect.
> +
> +typedef struct {
> + UINT64 IsaExtensionSupported; // The ISA extension this core supported.
> + RISCV_UINT128 MachineVendorId; // Machine vendor ID
> + RISCV_UINT128 MachineArchId; // Machine Architecture ID
> + RISCV_UINT128 MachineImplId; // Machine Implementation ID
> +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
UINT64 has 64-bit alignment requirement.
RISCV_UINT128 consists of two UINT64, giving it 64-bit alignment
requirement. I don't see how specifying alignment changes anything.
> +
> +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
> +
> +typedef struct {
> + VOID *PeiServiceTable; // PEI Service table
> + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
> +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
> +
> +#pragma pack(pop)
> +#endif
> +
> diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
> new file mode 100644
> index 0000000..89d5016
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi.h
> @@ -0,0 +1,96 @@
> +/** @file
> + SBI inline function calls.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _SBI_H_
> +#define _SBI_H_
Please drop leading _.
> +
> +#include <sbi/sbi_types.h> // Reference to header file wrapper
> +#include <include/sbi/riscv_asm.h> // Reference to header file in opensbi
> +
> +#define SBI_SET_TIMER 0
> +#define SBI_CONSOLE_PUTCHAR 1
> +#define SBI_CONSOLE_GETCHAR 2
> +#define SBI_CLEAR_IPI 3
> +#define SBI_SEND_IPI 4
> +#define SBI_REMOTE_FENCE_I 5
> +#define SBI_REMOTE_SFENCE_VMA 6
> +#define SBI_REMOTE_SFENCE_VMA_ASID 7
> +#define SBI_SHUTDOWN 8
> +
> +#define SBI_CALL(which, arg0, arg1, arg2) ({ \
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> + asm volatile ("ecall" \
> + : "+r" (a0) \
> + : "r" (a1), "r" (a2), "r" (a7) \
> + : "memory"); \
> + a0; \
> +})
> +
> +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
> +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
> +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
> +
> +static inline void sbi_console_putchar(int ch)
Static inline functions are not permitted in header files.
Please convert these wrapper functions to macros.
> +{
> + SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
> +}
> +
> +static inline int sbi_console_getchar(void)
> +{
> + return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
> +}
> +
> +static inline void sbi_set_timer(uint64_t stime_value)
> +{
> +#if __riscv_xlen == 32
> + SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
> +#else
> + SBI_CALL_1(SBI_SET_TIMER, stime_value);
> +#endif
> +}
> +
> +static inline void sbi_shutdown(void)
> +{
> + SBI_CALL_0(SBI_SHUTDOWN);
> +}
> +
> +static inline void sbi_clear_ipi(void)
> +{
> + SBI_CALL_0(SBI_CLEAR_IPI);
> +}
> +
> +static inline void sbi_send_ipi(const unsigned long *hart_mask)
> +{
> + SBI_CALL_1(SBI_SEND_IPI, hart_mask);
> +}
> +
> +static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> +{
> + SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
> +}
> +
> +static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
> +}
> +
> +static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid)
> +{
> + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
> +}
> +
> +#endif
> diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h
> new file mode 100644
> index 0000000..1e6bda3
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi_bits.h
> @@ -0,0 +1,17 @@
> +/** @file
> + RISC-V OpesbSBI header file reference.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef _EDK2_SBI_BITS_H_
> +#define _EDK2_SBI_BITS_H_
Please drop leading _.
> +
> +#undef MAX
> +#undef MIN
> +
> +#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi
> +
> +#endif
> diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h
> new file mode 100644
> index 0000000..d7ff227
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi_types.h
> @@ -0,0 +1,18 @@
> +/** @file
> + RISC-V OpesbSBI header file reference.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef _EDK2_SBI_TYPES_H_
> +#define _EDK2_SBI_TYPES_H_
Please drop leading _.
/
Leif
> +
> +#undef TRUE
> +#undef FALSE
> +#undef NULL
> +
> +#include "opensbi/include/sbi/sbi_types.h" // Reference to header file in opensbi
> +
> +#endif
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
@ 2019-09-26 22:44 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:44 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:29AM +0800, Abner Chang wrote:
> Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++++++++++
> MdePkg/MdePkg.dec | 5 +-
> 2 files changed, 177 insertions(+), 1 deletion(-)
> create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
>
> diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h
> new file mode 100644
> index 0000000..c3d4ef7
> --- /dev/null
> +++ b/MdePkg/Include/RiscV64/ProcessorBind.h
> @@ -0,0 +1,173 @@
> +/** @file
> + Processor or Compiler specific defines and types for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __PROCESSOR_BIND_H__
> +#define __PROCESSOR_BIND_H__
> +
> +///
> +/// Define the processor type so other code can make processor based choices
> +///
> +#define MDE_CPU_RISCV64
> +
> +//
> +// Make sure we are using the correct packing rules per EFI specification
> +//
> +#if !defined(__GNUC__)
> +#pragma pack()
> +#endif
> +
> +///
> +/// 8-byte unsigned value
> +///
> +typedef unsigned long long UINT64 __attribute__ ((aligned (8)));
> +///
> +/// 8-byte signed value
> +///
> +typedef long long INT64 __attribute__ ((aligned (8)));
> +///
> +/// 4-byte unsigned value
> +///
> +typedef unsigned int UINT32 __attribute__ ((aligned (4)));
> +///
> +/// 4-byte signed value
> +///
> +typedef int INT32 __attribute__ ((aligned (4)));
> +///
> +/// 2-byte unsigned value
> +///
> +typedef unsigned short UINT16 __attribute__ ((aligned (2)));
> +///
> +/// 2-byte Character. Unless otherwise specified all strings are stored in the
> +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
> +///
> +typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
> +///
> +/// 2-byte signed value
> +///
> +typedef short INT16 __attribute__ ((aligned (2)));
> +///
> +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
> +/// values are undefined.
> +///
> +typedef unsigned char BOOLEAN;
> +///
> +/// 1-byte unsigned value
> +///
> +typedef unsigned char UINT8;
> +///
> +/// 1-byte Character
> +///
> +typedef char CHAR8;
> +///
> +/// 1-byte signed value
> +///
> +typedef signed char INT8;
> +///
> +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
> +/// 8 bytes on supported 64-bit processor instructions)
> +///
> +typedef UINT64 UINTN __attribute__ ((aligned (8)));
> +///
> +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
> +/// 8 bytes on supported 64-bit processor instructions)
> +///
> +typedef INT64 INTN __attribute__ ((aligned (8)));
> +
> +//
> +// Processor specific defines
> +//
> +
> +///
> +/// A value of native width with the highest bit set.
> +///
> +#define MAX_BIT 0x8000000000000000ULL
> +///
> +/// A value of native width with the two highest bits set.
> +///
> +#define MAX_2_BITS 0xC000000000000000ULL
> +
> +///
> +/// Maximum legal RV64 address
> +///
> +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
> +
> +///
> +/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)
> +///
> +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
> +
> +///
> +/// Maximum legal RISC-V INTN and UINTN values.
> +///
> +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
> +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
> +
> +///
> +/// The stack alignment required for RISC-V
> +///
> +#define CPU_STACK_ALIGNMENT 16
> +
> +///
> +/// Page allocation granularity for RISC-V
> +///
> +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
> +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
> +
> +//
> +// Modifier to ensure that all protocol member functions and EFI intrinsics
> +// use the correct C calling convention. All protocol member functions and
> +// EFI intrinsics are required to modify their member functions with EFIAPI.
> +//
> +#ifdef EFIAPI
> + ///
> + /// If EFIAPI is already defined, then we use that definition.
> + ///
> +#elif defined(__GNUC__)
> + ///
> + /// Define the standard calling convention regardless of optimization level
> + /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
> + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
> + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
> + /// x64. Warning the assembly code in the MDE x64 does not follow the correct
> + /// ABI for the standard x64 (x86-64) GCC.
> + ///
> + #define EFIAPI
> +#else
> + ///
> + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
> + /// is the standard.
> + ///
> + #define EFIAPI
> +#endif
> +
> +#if defined(__GNUC__)
> + ///
> + /// For GNU assembly code, .global or .globl can declare global symbols.
> + /// Define this macro to unify the usage.
> + ///
> + #define ASM_GLOBAL .globl
> +#endif
> +
> +/**
> + Return the pointer to the first instruction of a function given a function pointer.
> + On x64 CPU architectures, these two pointer values are the same,
> + so the implementation of this macro is very simple.
> +
> + @param FunctionPointer A pointer to a function.
> +
> + @return The pointer to the first instruction of a function given a function pointer.
> +
> +**/
> +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
> +
> +#ifndef __USER_LABEL_PREFIX__
> +#define __USER_LABEL_PREFIX__
> +#endif
> +
> +#endif
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index 3fd7d16..1aaa97d 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -6,7 +6,7 @@
> #
> # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> +# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -39,6 +39,9 @@
> [Includes.AARCH64]
> Include/AArch64
>
> +[Includes.RISCV64]
> + Include/RiscV64
> +
> [LibraryClasses]
> ## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
> # and the standard requests defined in Usb 1.1 spec.
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
@ 2019-09-26 22:45 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:45 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:30AM +0800, Abner Chang wrote:
> Add RISC-V processor related definitions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++
> MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++++++++++
> MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++
> MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++
> MdePkg/Include/Uefi/UefiSpec.h | 5 +++
> 5 files changed, 89 insertions(+)
>
> diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
> index 720bb08..ca3fd0b 100644
> --- a/MdePkg/Include/IndustryStandard/PeImage.h
> +++ b/MdePkg/Include/IndustryStandard/PeImage.h
> @@ -9,6 +9,8 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define IMAGE_FILE_MACHINE_X64 0x8664
> #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
> #define IMAGE_FILE_MACHINE_ARM64 0xAA64
> +#define IMAGE_FILE_MACHINE_RISCV32 0x5032
> +#define IMAGE_FILE_MACHINE_RISCV64 0x5064
> +#define IMAGE_FILE_MACHINE_RISCV128 0x5128
>
> //
> // EXE file formats
> @@ -494,6 +499,13 @@ typedef struct {
> #define EFI_IMAGE_REL_BASED_DIR64 10
>
> ///
> +/// Relocation types of RISC-V processor.
> +///
> +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
> +
> +///
> /// Line number format.
> ///
> typedef struct {
> diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
> index 800e771..1a29cc0 100644
> --- a/MdePkg/Include/Protocol/DebugSupport.h
> +++ b/MdePkg/Include/Protocol/DebugSupport.h
> @@ -7,6 +7,7 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -603,6 +604,59 @@ typedef struct {
> UINT64 FAR; // Fault Address Register
> } EFI_SYSTEM_CONTEXT_AARCH64;
>
> +///
> +/// RISC-V processor exception types.
> +///
> +#define EXCEPT_RISCV_INST_MISALIGNED 0
> +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
> +#define EXCEPT_RISCV_ILLEGAL_INST 2
> +#define EXCEPT_RISCV_BREAKPOINT 3
> +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
> +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
> +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
> +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
> +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
> +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
> +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
> +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
> +
> +#define EXCEPT_RISCV_SOFTWARE_INT 0x0
> +#define EXCEPT_RISCV_TIMER_INT 0x1
> +
> +typedef struct {
> + UINT64 X0;
> + UINT64 X1;
> + UINT64 X2;
> + UINT64 X3;
> + UINT64 X4;
> + UINT64 X5;
> + UINT64 X6;
> + UINT64 X7;
> + UINT64 X8;
> + UINT64 X9;
> + UINT64 X10;
> + UINT64 X11;
> + UINT64 X12;
> + UINT64 X13;
> + UINT64 X14;
> + UINT64 X15;
> + UINT64 X16;
> + UINT64 X17;
> + UINT64 X18;
> + UINT64 X19;
> + UINT64 X20;
> + UINT64 X21;
> + UINT64 X22;
> + UINT64 X23;
> + UINT64 X24;
> + UINT64 X25;
> + UINT64 X26;
> + UINT64 X27;
> + UINT64 X28;
> + UINT64 X29;
> + UINT64 X30;
> + UINT64 X31;
> +} EFI_SYSTEM_CONTEXT_RISCV64;
>
> ///
> /// Universal EFI_SYSTEM_CONTEXT definition.
> @@ -614,6 +668,7 @@ typedef union {
> EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
> EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
> EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
> + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
> } EFI_SYSTEM_CONTEXT;
>
> //
> diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
> index b02d270..8a9e4a1 100644
> --- a/MdePkg/Include/Protocol/PxeBaseCode.h
> +++ b/MdePkg/Include/Protocol/PxeBaseCode.h
> @@ -3,6 +3,8 @@
> devices for network access and network booting.
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @par Revision Reference:
> @@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A
> #elif defined (MDE_CPU_AARCH64)
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
> +#elif defined (MDE_CPU_RISCV64)
> +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
> #endif
>
>
> diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
> index a62f13d..d979412 100644
> --- a/MdePkg/Include/Uefi/UefiBaseType.h
> +++ b/MdePkg/Include/Uefi/UefiBaseType.h
> @@ -3,6 +3,7 @@
>
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
> +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -240,6 +241,12 @@ typedef union {
> ///
> #define EFI_IMAGE_MACHINE_AARCH64 0xAA64
>
> +///
> +/// PE32+ Machine type for RISC-V 32/64/128
> +///
> +#define EFI_IMAGE_MACHINE_RISCV32 0x5032
> +#define EFI_IMAGE_MACHINE_RISCV64 0x5064
> +#define EFI_IMAGE_MACHINE_RISCV128 0x5128
>
> #if defined (MDE_CPU_IA32)
>
> @@ -268,6 +275,12 @@ typedef union {
>
> #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
>
> +#elif defined (MDE_CPU_RISCV64)
> +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
> + ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
> +
> +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
> +
> #elif defined (MDE_CPU_EBC)
>
> ///
> diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
> index 44a0a6a..e2d4539 100644
> --- a/MdePkg/Include/Uefi/UefiSpec.h
> +++ b/MdePkg/Include/Uefi/UefiSpec.h
> @@ -6,6 +6,8 @@
> by this include file.
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -2178,6 +2180,7 @@ typedef struct {
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
> #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
> +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
>
> #if defined (MDE_CPU_IA32)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
> @@ -2188,6 +2191,8 @@ typedef struct {
> #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
> #elif defined (MDE_CPU_AARCH64)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
> +#elif defined (MDE_CPU_RISCV64)
> + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
> #else
> #error Unknown Processor Type
> #endif
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
@ 2019-09-26 22:46 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:46 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:31AM +0800, Abner Chang wrote:
> Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> index 9da4507..84f3688 100644
> --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> @@ -5,6 +5,7 @@
> # the capsule runtime services are ready.
> #
> # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> ##
> @@ -21,20 +22,20 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> CapsuleService.c
> CapsuleService.h
>
> -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
> +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
> SaveLongModeContext.c
>
> -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
> +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
> CapsuleCache.c
>
> -[Sources.Ia32, Sources.X64, Sources.EBC]
> +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
> CapsuleReset.c
>
> [Sources.ARM, Sources.AARCH64]
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
@ 2019-09-26 22:56 ` Leif Lindholm
2019-10-14 16:47 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 22:56 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:32AM +0800, Abner Chang wrote:
> Add RISC-V RV64 BaseLib functions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Include/Library/BaseLib.h | 26 ++
> MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
> MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++
> MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +++
> MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++
> MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++
> MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++
> MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 +++
> .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++
> MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++
> .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++
> MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++
> MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++
> .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++
> MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++++++++++++++
> 15 files changed, 670 insertions(+), 1 deletion(-)
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
>
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index 2a75bc0..b8c8512 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -4,6 +4,8 @@
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -124,6 +126,30 @@ typedef struct {
>
> #endif // defined (MDE_CPU_AARCH64)
>
> +#if defined (MDE_CPU_RISCV64)
> +///
> +/// The RISC-V architecture context buffer used by SetJump() and LongJump().
> +///
> +typedef struct {
> + UINT64 RA;
> + UINT64 S0;
> + UINT64 S1;
> + UINT64 S2;
> + UINT64 S3;
> + UINT64 S4;
> + UINT64 S5;
> + UINT64 S6;
> + UINT64 S7;
> + UINT64 S8;
> + UINT64 S9;
> + UINT64 S10;
> + UINT64 S11;
> + UINT64 SP;
> +} BASE_LIBRARY_JUMP_BUFFER;
> +
> +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
> +
> +#endif // defined (MDE_CPU_RISCV64)
>
> //
> // String Services
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> index 3586beb..28d5795 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -4,6 +4,7 @@
> # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -20,7 +21,7 @@
> LIBRARY_CLASS = BaseLib
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> @@ -381,6 +382,21 @@
> AArch64/CpuBreakpoint.asm | MSFT
> AArch64/SpeculationBarrier.asm | MSFT
>
> +[Sources.RISCV64]
> + Math64.c
> + RiscV64/Unaligned.c
> + RiscV64/InternalSwitchStack.c
> + RiscV64/CpuBreakpoint.c
> + RiscV64/GetInterruptState.c
> + RiscV64/DisableInterrupts.c
> + RiscV64/EnableInterrupts.c
> + RiscV64/CpuPause.c
> + RiscV64/RiscVSetJumpLongJump.S | GCC
> + RiscV64/RiscVCpuBreakpoint.S | GCC
> + RiscV64/RiscVCpuPause.S | GCC
> + RiscV64/RiscVInterrupt.S | GCC
> + RiscV64/FlushCache.S | GCC
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> new file mode 100644
> index 0000000..d82b1d5
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> @@ -0,0 +1,27 @@
> +/** @file
> + CPU breakpoint for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVCpuBreakpoint (VOID);
> +
> +/**
> + Generates a breakpoint on the CPU.
> +
> + Generates a breakpoint on the CPU. The breakpoint must be implemented such
> + that code can resume normal execution after the breakpoint.
> +
> +**/
> +VOID
> +EFIAPI
> +CpuBreakpoint (
> + VOID
> + )
> +{
> + RiscVCpuBreakpoint ();
> +}
> diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> new file mode 100644
> index 0000000..8eb6b65
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> @@ -0,0 +1,29 @@
> +/** @file
> + CPU pause for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVCpuPause (VOID);
> +
> +
> +/**
> + Requests CPU to pause for a short period of time.
> +
> + Requests CPU to pause for a short period of time. Typically used in MP
> + systems to prevent memory starvation while waiting for a spin lock.
> +
> +**/
> +VOID
> +EFIAPI
> +CpuPause (
> + VOID
> + )
> +{
> + RiscVCpuPause ();
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> new file mode 100644
> index 0000000..7ee5eb1
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> @@ -0,0 +1,24 @@
> +/** @file
> + CPU disable interrupt function for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
> +
> +/**
> + Disables CPU interrupts.
> +
> +**/
> +VOID
> +EFIAPI
> +DisableInterrupts (
> + VOID
> + )
> +{
> + RiscVDisableSupervisorModeInterrupts ();
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> new file mode 100644
> index 0000000..9aa0d9a
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> @@ -0,0 +1,25 @@
> +/** @file
> + CPU enable interrupt function for RISC-V
> +
> + Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
> +
> +/**
> + Enables CPU interrupts.
> +
> +**/
> +VOID
> +EFIAPI
> +EnableInterrupts (
> + VOID
> + )
> +{
> + RiscVEnableSupervisorModeInterrupt ();
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> new file mode 100644
> index 0000000..0ef0213
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> @@ -0,0 +1,21 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V cache operation.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +
> +.align 3
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
> +
> +ASM_PFX(RiscVInvalidateInstCacheAsm):
> + fence.i
> + ret
> +
> +ASM_PFX(RiscVInvalidateDataCacheAsm):
> + fence
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> new file mode 100644
> index 0000000..8f764fb
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> @@ -0,0 +1,35 @@
> +/** @file
> + CPU get interrupt state function for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
> +
> +/**
> + Retrieves the current CPU interrupt state.
> +
> + Returns TRUE is interrupts are currently enabled. Otherwise
> + returns FALSE.
> +
> + @retval TRUE CPU interrupts are enabled.
> + @retval FALSE CPU interrupts are disabled.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +GetInterruptState (
> + VOID
> + )
> +{
> + unsigned long RetValue;
> +
> + RetValue = RiscVGetSupervisorModeInterrupts ();
> + return RetValue? TRUE: FALSE;
> +}
> +
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> new file mode 100644
> index 0000000..1082d4e
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> @@ -0,0 +1,55 @@
> +/** @file
> + Switch stack function for RISC-V
> +
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +/**
> + Transfers control to a function starting with a new stack.
> +
> + Transfers control to the function specified by EntryPoint using the
> + new stack specified by NewStack and passing in the parameters specified
> + by Context1 and Context2. Context1 and Context2 are optional and may
> + be NULL. The function EntryPoint must never return.
> + Marker will be ignored on IA-32, x64, and EBC.
> + IPF CPUs expect one additional parameter of type VOID * that specifies
> + the new backing store pointer.
> +
> + If EntryPoint is NULL, then ASSERT().
> + If NewStack is NULL, then ASSERT().
> +
> + @param EntryPoint A pointer to function to call with the new stack.
> + @param Context1 A pointer to the context to pass into the EntryPoint
> + function.
> + @param Context2 A pointer to the context to pass into the EntryPoint
> + function.
> + @param NewStack A pointer to the new stack to use for the EntryPoint
> + function.
> + @param Marker VA_LIST marker for the variable argument list.
> +
> +**/
> +VOID
> +EFIAPI
> +InternalSwitchStack (
> + IN SWITCH_STACK_ENTRY_POINT EntryPoint,
> + IN VOID *Context1, OPTIONAL
> + IN VOID *Context2, OPTIONAL
> + IN VOID *NewStack,
> + IN VA_LIST Marker
> + )
> +{
> + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
> +
> + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
> + EntryPoint, Context1, Context2, NewStack));
> + JumpBuffer.RA = (UINTN)EntryPoint;
> + JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
> + JumpBuffer.S0 = (UINT64)(UINTN)Context1;
> + JumpBuffer.S1 = (UINT64)(UINTN)Context2;
> + LongJump (&JumpBuffer, (UINTN)-1);
> + ASSERT(FALSE);
> +}
> diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> new file mode 100644
> index 0000000..a62b882
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> @@ -0,0 +1,32 @@
> +/** @file
> + Long jump implementation of RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +
> +/**
> + Restores the CPU context that was saved with SetJump().
> +
> + Restores the CPU context from the buffer specified by JumpBuffer.
> + This function never returns to the caller.
> + Instead is resumes execution based on the state of JumpBuffer.
> +
> + @param JumpBuffer A pointer to CPU context buffer.
> + @param Value The value to return when the SetJump() context is restored.
> +
> +**/
> +VOID
> +EFIAPI
> +InternalLongJump (
> + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
> + IN UINTN Value
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> new file mode 100644
> index 0000000..1a45e2a
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> @@ -0,0 +1,14 @@
> +//------------------------------------------------------------------------------
> +//
> +// CpuBreakpoint for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +
> +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
> +ASM_PFX(RiscVCpuBreakpoint):
> + ebreak
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> new file mode 100644
> index 0000000..ceba0c0
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> @@ -0,0 +1,14 @@
> +//------------------------------------------------------------------------------
> +//
> +// CpuPause for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +
> +ASM_GLOBAL ASM_PFX(RiscVCpuPause)
> +ASM_PFX(RiscVCpuPause):
> + nop
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> new file mode 100644
> index 0000000..8fdb544
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> @@ -0,0 +1,32 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V Supervisor Mode interrupt enable/disable
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +
> +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
> +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
> +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
> +
> +# define MSTATUS_SIE 0x00000002
> +# define CSR_SSTATUS 0x100
> +
> +ASM_PFX(RiscVDisableSupervisorModeInterrupts):
> + li a1, MSTATUS_SIE
> + csrc CSR_SSTATUS, a1
> + ret
> +
> +ASM_PFX(RiscVEnableSupervisorModeInterrupt):
> + li a1, MSTATUS_SIE
> + csrs CSR_SSTATUS, a1
> + ret
> +
> +ASM_PFX(RiscVGetSupervisorModeInterrupts):
> + csrr a0, CSR_SSTATUS
> + andi a0, a0, MSTATUS_SIE
> + ret
> +
> diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> new file mode 100644
> index 0000000..e72dd7f
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> @@ -0,0 +1,55 @@
> +//------------------------------------------------------------------------------
> +//
> +// Set/Long jump for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +# define REG_S sd
> +# define REG_L ld
> +# define SZREG 8
> +.align 3
> + .globl SetJump
> +
> +SetJump:
> + REG_S ra, 0*SZREG(a0)
> + REG_S s0, 1*SZREG(a0)
> + REG_S s1, 2*SZREG(a0)
> + REG_S s2, 3*SZREG(a0)
> + REG_S s3, 4*SZREG(a0)
> + REG_S s4, 5*SZREG(a0)
> + REG_S s5, 6*SZREG(a0)
> + REG_S s6, 7*SZREG(a0)
> + REG_S s7, 8*SZREG(a0)
> + REG_S s8, 9*SZREG(a0)
> + REG_S s9, 10*SZREG(a0)
> + REG_S s10,11*SZREG(a0)
> + REG_S s11,12*SZREG(a0)
> + REG_S sp, 13*SZREG(a0)
Please adjust indentation of all of the asm code so that there is
space after ',' and on both sides of '*'.
> + li a0, 0
> + ret
> +
> + .globl InternalLongJump
> +InternalLongJump:
> + REG_L ra, 0*SZREG(a0)
> + REG_L s0, 1*SZREG(a0)
> + REG_L s1, 2*SZREG(a0)
> + REG_L s2, 3*SZREG(a0)
> + REG_L s3, 4*SZREG(a0)
> + REG_L s4, 5*SZREG(a0)
> + REG_L s5, 6*SZREG(a0)
> + REG_L s6, 7*SZREG(a0)
> + REG_L s7, 8*SZREG(a0)
> + REG_L s8, 9*SZREG(a0)
> + REG_L s9, 10*SZREG(a0)
> + REG_L s10,11*SZREG(a0)
> + REG_L s11,12*SZREG(a0)
> + REG_L sp, 13*SZREG(a0)
> +
> + add a0, s0, 0
> + add a1, s1, 0
> + add a2, s2, 0
> + add a3, s3, 0
> + ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> new file mode 100644
> index 0000000..012d913
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
We do need to fix BaseLib/Unaligned.c (as well as the associated
definitions in header file), but having a separate implementation for
RISCV does not make sense.
/
Leif
> @@ -0,0 +1,264 @@
> +/** @file
> + RISC-V specific functionality for (un)aligned memory read/write.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BaseLibInternals.h"
> +
> +/**
> + Reads a 16-bit value from memory that may be unaligned.
> +
> + This function returns the 16-bit value pointed to by Buffer. The function
> + guarantees that the read operation does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 16-bit value that may be unaligned.
> +
> + @return The 16-bit value read from Buffer.
> +
> +**/
> +UINT16
> +EFIAPI
> +ReadUnaligned16 (
> + IN CONST UINT16 *Buffer
> + )
> +{
> + UINT16 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = sizeof (UINT16) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 16-bit value to memory that may be unaligned.
> +
> + This function writes the 16-bit value specified by Value to Buffer. Value is
> + returned. The function guarantees that the write operation does not produce
> + an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 16-bit value that may be unaligned.
> + @param Value 16-bit value to write to Buffer.
> +
> + @return The 16-bit value to write to Buffer.
> +
> +**/
> +UINT16
> +EFIAPI
> +WriteUnaligned16 (
> + OUT UINT16 *Buffer,
> + IN UINT16 Value
> + )
> +{
> + INT8 Count;
> + UINT16 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT16) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 24-bit value from memory that may be unaligned.
> +
> + This function returns the 24-bit value pointed to by Buffer. The function
> + guarantees that the read operation does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 24-bit value that may be unaligned.
> +
> + @return The 24-bit value read from Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +ReadUnaligned24 (
> + IN CONST UINT32 *Buffer
> + )
> +{
> + UINT32 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 2, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 24-bit value to memory that may be unaligned.
> +
> + This function writes the 24-bit value specified by Value to Buffer. Value is
> + returned. The function guarantees that the write operation does not produce
> + an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 24-bit value that may be unaligned.
> + @param Value 24-bit value to write to Buffer.
> +
> + @return The 24-bit value to write to Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +WriteUnaligned24 (
> + OUT UINT32 *Buffer,
> + IN UINT32 Value
> + )
> +{
> + INT8 Count;
> + UINT32 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < 3 ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit value from memory that may be unaligned.
> +
> + This function returns the 32-bit value pointed to by Buffer. The function
> + guarantees that the read operation does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 32-bit value that may be unaligned.
> +
> + @return The 32-bit value read from Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +ReadUnaligned32 (
> + IN CONST UINT32 *Buffer
> + )
> +{
> + UINT32 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> +
> + for (Count = sizeof (UINT32) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 32-bit value to memory that may be unaligned.
> +
> + This function writes the 32-bit value specified by Value to Buffer. Value is
> + returned. The function guarantees that the write operation does not produce
> + an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 32-bit value that may be unaligned.
> + @param Value The 32-bit value to write to Buffer.
> +
> + @return The 32-bit value to write to Buffer.
> +
> +**/
> +UINT32
> +EFIAPI
> +WriteUnaligned32 (
> + OUT UINT32 *Buffer,
> + IN UINT32 Value
> + )
> +{
> + INT8 Count;
> + UINT32 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT32) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit value from memory that may be unaligned.
> +
> + This function returns the 64-bit value pointed to by Buffer. The function
> + guarantees that the read operation does not produce an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 64-bit value that may be unaligned.
> +
> + @return The 64-bit value read from Buffer.
> +
> +**/
> +UINT64
> +EFIAPI
> +ReadUnaligned64 (
> + IN CONST UINT64 *Buffer
> + )
> +{
> + UINT64 Value;
> + INT8 Count;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = sizeof (UINT64) - 1, Value = 0; Count >= 0 ; Count --) {
> + Value = Value << 8;
> + Value |= *((UINT8*)Buffer + Count);
> + }
> + return Value;
> +}
> +
> +/**
> + Writes a 64-bit value to memory that may be unaligned.
> +
> + This function writes the 64-bit value specified by Value to Buffer. Value is
> + returned. The function guarantees that the write operation does not produce
> + an alignment fault.
> +
> + If the Buffer is NULL, then ASSERT().
> +
> + @param Buffer A pointer to a 64-bit value that may be unaligned.
> + @param Value The 64-bit value to write to Buffer.
> +
> + @return The 64-bit value to write to Buffer.
> +
> +**/
> +UINT64
> +EFIAPI
> +WriteUnaligned64 (
> + OUT UINT64 *Buffer,
> + IN UINT64 Value
> + )
> +{
> + INT8 Count;
> + UINT64 ValueTemp;
> +
> + ASSERT (Buffer != NULL);
> + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT64) ; Count ++) {
> + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> + ValueTemp = ValueTemp >> 8;
> + }
> + return Value;
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
2019-09-23 0:31 ` Abner Chang
@ 2019-09-26 23:30 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 23:30 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:34AM +0800, Abner Chang wrote:
> Implement RISC-V cache maintenance functions in
> BaseCacheMaintenanceLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
I can't comment on their correctness, but the code looks fine.
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../BaseCacheMaintenanceLib.inf | 4 +
> .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++
> 2 files changed, 254 insertions(+)
> create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> index ec7feec..d9bfa04 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> @@ -6,6 +6,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -41,6 +42,9 @@
> [Sources.AARCH64]
> ArmCache.c
>
> +[Sources.RISCV64]
> + RiscVCache.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> new file mode 100644
> index 0000000..d8e4665
> --- /dev/null
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -0,0 +1,250 @@
> +/** @file
> + RISC-V specific functionality for cache.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + RISC-V invalidate instruction cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateInstCacheAsm (
> + VOID
> + );
> +
> +/**
> + RISC-V invalidate data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateDataCacheAsm (
> + VOID
> + );
> +
> +/**
> + Invalidates the entire instruction cache in cache coherency domain of the
> + calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateInstructionCache (
> + VOID
> + )
> +{
> + RiscVInvalidateInstCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of instruction cache lines in the cache coherency domain
> + of the calling CPU.
> +
> + Invalidates the instruction cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire instruction
> + cache line containing Address is invalidated. If Address + Length is not
> + aligned on a cache line boundary, then the entire instruction cache line
> + containing Address + Length -1 is invalidated. This function may choose to
> + invalidate the entire instruction cache if that is more efficient than
> + invalidating the specified range. If Length is 0, then no instruction cache
> + lines are invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the instruction cache lines to
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> +
> + @param Length The number of bytes to invalidate from the instruction cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateInstructionCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back and invalidates the entire data cache in cache coherency domain
> + of the calling CPU.
> +
> + Writes back and invalidates the entire data cache in cache coherency domain
> + of the calling CPU. This function guarantees that all dirty cache lines are
> + written back to system memory, and also invalidates all the data cache lines
> + in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackInvalidateDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
> +}
> +
> +/**
> + Writes back and invalidates a range of data cache lines in the cache
> + coherency domain of the calling CPU.
> +
> + Writes back and invalidates the data cache lines specified by Address and
> + Length. If Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is written back and invalidated. If Address +
> + Length is not aligned on a cache line boundary, then the entire data cache
> + line containing Address + Length -1 is written back and invalidated. This
> + function may choose to write back and invalidate the entire data cache if
> + that is more efficient than writing back and invalidating the specified
> + range. If Length is 0, then no data cache lines are written back and
> + invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back and
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> + @param Length The number of bytes to write back and invalidate from the
> + data cache.
> +
> + @return Address of cache invalidation.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackInvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back the entire data cache in cache coherency domain of the calling
> + CPU.
> +
> + Writes back the entire data cache in cache coherency domain of the calling
> + CPU. This function guarantees that all dirty cache lines are written back to
> + system memory. This function may also invalidate all the data cache lines in
> + the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> +}
> +
> +/**
> + Writes back a range of data cache lines in the cache coherency domain of the
> + calling CPU.
> +
> + Writes back the data cache lines specified by Address and Length. If Address
> + is not aligned on a cache line boundary, then entire data cache line
> + containing Address is written back. If Address + Length is not aligned on a
> + cache line boundary, then the entire data cache line containing Address +
> + Length -1 is written back. This function may choose to write back the entire
> + data cache if that is more efficient than writing back the specified range.
> + If Length is 0, then no data cache lines are written back. This function may
> + also invalidate all the data cache lines in the specified range of the cache
> + coherency domain of the calling CPU. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing
> + mode, then Address is a virtual address.
> + @param Length The number of bytes to write back from the data cache.
> +
> + @return Address of cache written in main memory.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Invalidates the entire data cache in cache coherency domain of the calling
> + CPU.
> +
> + Invalidates the entire data cache in cache coherency domain of the calling
> + CPU. This function must be used with care because dirty cache lines are not
> + written back to system memory. It is typically used for cache diagnostics. If
> + the CPU does not support invalidation of the entire data cache, then a write
> + back and invalidate operation should be performed on the entire data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateDataCache (
> + VOID
> + )
> +{
> + RiscVInvalidateDataCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of data cache lines in the cache coherency domain of the
> + calling CPU.
> +
> + Invalidates the data cache lines specified by Address and Length. If Address
> + is not aligned on a cache line boundary, then entire data cache line
> + containing Address is invalidated. If Address + Length is not aligned on a
> + cache line boundary, then the entire data cache line containing Address +
> + Length -1 is invalidated. This function must never invalidate any cache lines
> + outside the specified range. If Length is 0, then no data cache lines are
> + invalidated. Address is returned. This function must be used with care
> + because dirty cache lines are not written back to system memory. It is
> + typically used for cache diagnostics. If the CPU does not support
> + invalidation of a data cache range, then a write back and invalidate
> + operation should be performed on the data cache range.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to invalidate. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing mode,
> + then Address is a virtual address.
> + @param Length The number of bytes to invalidate from the data cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + return Address;
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
@ 2019-09-26 23:39 ` Leif Lindholm
2019-10-01 8:49 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 23:39 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:35AM +0800, Abner Chang wrote:
> RISC-V MMIO library instance. RISC-V only supports memory map I/O.
We need fewer, not more, C implementations of MMIO accessors.
While this set doesn't need to wait for upstream to get sorted, please
just use IoLibArm.c which should be completely equivalent to what you
have implemented here.
/
Leif
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
> 2 files changed, 607 insertions(+), 2 deletions(-)
> create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> index 457cce9..fbb568e 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> @@ -2,13 +2,14 @@
> # Instance of I/O Library using compiler intrinsics.
> #
> # I/O Library that uses compiler intrinsics to perform IN and OUT instructions
> -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
> +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated into MMIO requests.
> # MMIO requests are forwarded directly to memory. For EBC, I/O port requests
> # ASSERT().
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -25,7 +26,7 @@
>
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> @@ -55,6 +56,9 @@
> [Sources.AARCH64]
> IoLibArm.c
>
> +[Sources.RISCV64]
> + IoLibRiscV.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> new file mode 100644
> index 0000000..789928b
> --- /dev/null
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> @@ -0,0 +1,601 @@
> +/** @file
> + Common I/O Library routines for RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +#include "BaseIoLibIntrinsicInternal.h"
> +
> +/**
> + Reads an 8-bit MMIO register.
> +
> + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioRead8 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT8*)Address;
> +}
> +
> +/**
> + Writes an 8-bit MMIO register.
> +
> + Writes the 8-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + )
> +{
> + *(volatile UINT8 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 16-bit MMIO register.
> +
> + Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioRead16 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT16 *)Address;
> +}
> +
> +/**
> + Writes a 16-bit MMIO register.
> +
> + Writes the 16-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + *(volatile UINT16 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit MMIO register.
> +
> + Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioRead32 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT32 *)Address;
> +}
> +
> +/**
> + Writes a 32-bit MMIO register.
> +
> + Writes the 32-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The valu return *(volatile UINT8*)Address;
> + to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + *(volatile UINT32 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit MMIO register.
> +
> + Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioRead64 (
> + IN UINTN Address
> + )
> +{
> + return *(volatile UINT64 *)Address;
> +}
> +
> +/**
> + Writes a 64-bit MMIO register.
> +
> + Writes the 64-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + *(volatile UINT64 *)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads an 8-bit I/O port.
> +
> + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +IoRead8 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes an 8-bit I/O port.
> +
> + Writes the 8-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +
> +UINT8
> +EFIAPI
> +IoWrite8 (
> + IN UINTN Port,
> + IN UINT8 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 16-bit I/O port.
> +
> + Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoRead16 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 16-bit I/O port.
> +
> + Writes the 16-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoWrite16 (
> + IN UINTN Port,
> + IN UINT16 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 32-bit I/O port.
> +
> + Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoRead32 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 32-bit I/O port.
> +
> + Writes the 32-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoWrite32 (
> + IN UINTN Port,
> + IN UINT32 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 64-bit I/O port.
> +
> + Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoRead64 (
> + IN UINTN Port
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 64-bit I/O port.
> +
> + Writes the 64-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written to the I/O port.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoWrite64 (
> + IN UINTN Port,
> + IN UINT64 Value
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads an 8-bit I/O port fifo into a block of memory.
> +
> + Reads the 8-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into an 8-bit I/O port fifo.
> +
> + Writes the 8-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 16-bit I/O port fifo into a block of memory.
> +
> + Reads the 16-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 16-bit I/O port fifo.
> +
> + Writes the 16-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 32-bit I/O port fifo into a block of memory.
> +
> + Reads the 32-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 32-bit I/O port fifo.
> +
> + Writes the 32-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
> + ASSERT (FALSE);
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
@ 2019-09-26 23:46 ` Leif Lindholm
2019-10-15 4:02 ` Abner Chang
[not found] ` <15CDB6324F411B37.30896@groups.io>
0 siblings, 2 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 23:46 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> Support RISC-V image relocation.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++++++++++++++++++
> 5 files changed, 152 insertions(+), 1 deletion(-)
> create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> index 07bb62f..97e0ff4 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> @@ -1,6 +1,6 @@
> /** @file
> Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
> - only supports relocating IA32, x64, IPF, and EBC images.
> + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
>
> Caution: This file requires additional review when modified.
> This library will have external input - PE/COFF image.
> @@ -17,6 +17,7 @@
>
> Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> index 395c140..b190494 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> @@ -3,6 +3,7 @@
> # The IPF version library supports loading IPF and EBC PE/COFF image.
> # The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
> # The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> +# The RISC-V version library support loading RISC-V images.
> #
> # Caution: This module requires additional review when modified.
> # This library will have external input - PE/COFF image.
> @@ -11,6 +12,7 @@
> #
> # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -41,6 +43,9 @@
> [Sources.ARM]
> Arm/PeCoffLoaderEx.c
>
> +[Sources.RISCV64]
> + RiscV/PeCoffLoaderEx.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> index b0ea702..8616ca3 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> @@ -4,6 +4,7 @@
> // The IPF version library supports loading IPF and EBC PE/COFF image.
> // The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
> // The X64 version library support loading IA32, X64 and EBC PE/COFF images.
> +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
> //
> // Caution: This module requires additional review when modified.
> // This library will have external input - PE/COFF image.
> @@ -12,6 +13,7 @@
> //
> // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent
> //
> diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> index b74277f..9c33703 100644
> --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> @@ -2,6 +2,7 @@
> Declaration of internal functions in PE/COFF Lib.
>
> Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
You only get to add copyright when you otherwise modify the file :)
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> new file mode 100644
> index 0000000..8eb37f9
> --- /dev/null
> +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> @@ -0,0 +1,142 @@
> +/** @file
> + PE/Coff loader for RISC-V PE image
> +
> + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +#include "BasePeCoffLibInternals.h"
> +#include <Library/BaseLib.h>
> +
> +//
> +// RISC-V definition.
> +//
> +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> +#define RISCV_IMM_BITS 12
> +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> +#define RISCV_CONST_HIGH_PART(VALUE) \
> + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
This looked familiar, so I had a look.
This block is copied around - it exists in:
- BaseTools/Source/C/Common/PeCoffLoaderEx.c
- BaseTools/Source/C/GenFw/Elf64Convert.c
- MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
This needs to be moved somewhere central and included elsewhere.
BaseTools and MdePkg unfortunately duplicate a lot of stuff, but this
still belongs in a common header file for either.
> +
> +/**
> + Performs an RISC-V specific relocation fixup and is a no-op on
> + other instruction sets.
> + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
> + types. We have to know the lower 12-bit fixup first then we can deal
> + carry over on high 20-bit fixup. So we log the high 20-bit in
> + FixupData.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeCoffLoaderRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + UINT32 Value;
> + UINT32 Value2;
> + UINT32 *RiscVHi20Fixup;
> +
> + switch ((*Reloc) >> 12) {
> + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> +
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
> + (RV_X (*(UINT32 *)Fixup, 0, 20));
> + }
> + break;
> +
> + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> + if (RiscVHi20Fixup != NULL) {
> + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
> + if (Value2 & (RISCV_IMM_REACH/2)) {
> + Value2 |= ~(RISCV_IMM_REACH-1);
> + }
> + Value += Value2;
> + Value += (UINT32)Adjust;
> + Value2 = RISCV_CONST_HIGH_PART (Value);
> + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> + Value &= RISCV_IMM_REACH - 1;
> + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
> + }
> + break;
> +
> + default:
> + return RETURN_UNSUPPORTED;
> +
> + }
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Returns TRUE if the machine type of PE/COFF image is supported. Supported
> + does not mean the image can be executed it means the PE/COFF loader supports
> + loading and relocating of the image type. It's up to the caller to support
> + the entry point.
> +
> + @param Machine Machine type from the PE Header.
> +
> + @return TRUE if this PE/COFF loader can load the image
> +
> +**/
> +BOOLEAN
> +PeCoffLoaderImageFormatSupported (
> + IN UINT16 Machine
> + )
> +{
> + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine == IMAGE_FILE_MACHINE_RISCV64)) {
RISCV32 is not supported by this set.
/
Leif
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Performs an Itanium-based specific re-relocation fixup and is a no-op on other
> + instruction sets. This is used to re-relocated the image into the EFI virtual
> + space for runtime calls.
> +
> + @param Reloc The pointer to the relocation record.
> + @param Fixup The pointer to the address to fix up.
> + @param FixupData The pointer to a buffer to log the fixups.
> + @param Adjust The offset to adjust the fixup.
> +
> + @return Status code.
> +
> +**/
> +RETURN_STATUS
> +PeHotRelocateImageEx (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + return RETURN_UNSUPPORTED;
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
@ 2019-09-26 23:47 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-26 23:47 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:37AM +0800, Abner Chang wrote:
> Implement RISC-V CPU related functions in BaseCpuLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++-
> MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++--
> MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++
> 3 files changed, 27 insertions(+), 3 deletions(-)
> create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
>
> diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> index a7cb381..a95d8a0 100644
> --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> @@ -7,6 +7,7 @@
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -24,7 +25,7 @@
>
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources.IA32]
> @@ -59,6 +60,9 @@
> AArch64/CpuFlushTlb.asm | MSFT
> AArch64/CpuSleep.asm | MSFT
>
> +[Sources.RISCV64]
> + RiscV/Cpu.S
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> index fc95cda..85d56ce 100644
> --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
> @@ -1,12 +1,13 @@
> // /** @file
> // Instance of CPU Library for various architecture.
> //
> -// CPU Library implemented using ASM functions for IA-32 and X64,
> +// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
> // PAL CALLs for IPF, and empty functions for EBC.
> //
> // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent
> //
> @@ -15,5 +16,5 @@
>
> #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
>
> -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC."
> +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
>
> diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> new file mode 100644
> index 0000000..703b1e8
> --- /dev/null
> +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> @@ -0,0 +1,19 @@
> +//------------------------------------------------------------------------------
> +//
> +// CpuSleep for RISC-V
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +.data
> +.align 3
> +.section .text
> +
> +.global ASM_PFX(_CpuSleep)
> +
> +ASM_PFX(_CpuSleep):
> + wfi
> + ret
> +
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
@ 2019-09-27 0:19 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-27 0:19 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:38AM +0800, Abner Chang wrote:
> Support RISC-V cache related functions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
What is the purpose of the .c file?
Currently all I see it doing it printing some messages before calling
into assembly, and forcing Hungarian notation on the filenames.
There is no value in providing runtime notifications that
synchronization is not required - this is a library, we wil learn at
build time if our code is impacted by lack of some primitive.
Can you drop the .c file, rename the .S file Synchronization.S, and
renaming the functions in the .S:
InternalSyncCompareExchange32
InternalSyncCompareExchange64
InternalSyncIncrement
InternalSyncDecrement
U500 still builds fine after this change.
/
Leif
> ---
> .../BaseSynchronizationLib.inf | 6 +
> .../RiscV64/Synchronization.c | 183 +++++++++++++++++++++
> .../RiscV64/SynchronizationAsm.S | 78 +++++++++
> 3 files changed, 267 insertions(+)
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> index 446bc19..c16ef9d 100755
> --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> @@ -3,6 +3,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -78,6 +79,11 @@
> AArch64/Synchronization.S | GCC
> AArch64/Synchronization.asm | MSFT
>
> +[Sources.RISCV64]
> + Synchronization.c
> + RiscV64/Synchronization.c | GCC
> + RiscV64/SynchronizationAsm.S
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> new file mode 100644
> index 0000000..e210b74
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> @@ -0,0 +1,183 @@
> +/** @file
> + Implementation of synchronization functions on RISC-V
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/DebugLib.h>
> +
> +UINT32
> +SyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT32 CompareValue,
> + IN UINT32 ExchangeValue
> +);
> +
> +UINT64
> +SyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> +);
> +
> +UINT32
> +SyncSyncIncrement32 (
> + IN volatile UINT32 *Value
> + );
> +
> +UINT32
> +SyncSyncDecrement32 (
> + IN volatile UINT32 *Value
> + );
> +
> +/**
> + Performs an atomic compare exchange operation on a 16-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 16-bit
> + unsigned integer specified by Value. If Value is equal to
> + CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to
> + CompareValue, then Value is returned. The compare exchange
> + operation must be performed using MP safe mechanisms.
> +
> + @param Value A pointer to the 16-bit value for the
> + compare exchange operation.
> + @param CompareValue 16-bit value used in compare operation.
> + @param ExchangeValue 16-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT16
> +EFIAPI
> +InternalSyncCompareExchange16 (
> + IN volatile UINT16 *Value,
> + IN UINT16 CompareValue,
> + IN UINT16 ExchangeValue
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO operation\n", __FUNCTION__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs an atomic compare exchange operation on a 32-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 32-bit
> + unsigned integer specified by Value. If Value is equal to
> + CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to
> + CompareValue, then Value is returned. The compare exchange
> + operation must be performed using MP safe mechanisms.
> +
> + @param Value A pointer to the 32-bit value for the
> + compare exchange operation.
> + @param CompareValue 32-bit value used in compare operation.
> + @param ExchangeValue 32-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT32 CompareValue,
> + IN UINT32 ExchangeValue
> + )
> +{
> +
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncCompareExchange32(Value, CompareValue, ExchangeValue);
> +}
> +
> +/**
> + Performs an atomic compare exchange operation on a 64-bit unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
> + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
> + The compare exchange operation must be performed using MP safe mechanisms.
> +
> + @param Value A pointer to the 64-bit value for the compare exchange
> + operation.
> + @param CompareValue 64-bit value used in compare operation.
> + @param ExchangeValue 64-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT64
> +EFIAPI
> +InternalSyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT64)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncCompareExchange64 (Value, CompareValue, ExchangeValue);
> +}
> +
> +/**
> + Performs an atomic increment of an 32-bit unsigned integer.
> +
> + Performs an atomic increment of the 32-bit unsigned integer specified by
> + Value and returns the incremented value. The increment operation must be
> + performed using MP safe mechanisms. The state of the return value is not
> + guaranteed to be MP safe.
> +
> + @param Value A pointer to the 32-bit value to increment.
> +
> + @return The incremented value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncIncrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncSyncIncrement32 (Value);
> +}
> +
> +/**
> + Performs an atomic decrement of an 32-bit unsigned integer.
> +
> + Performs an atomic decrement of the 32-bit unsigned integer specified by
> + Value and returns the decrement value. The decrement operation must be
> + performed using MP safe mechanisms. The state of the return value is not
> + guaranteed to be MP safe.
> +
> + @param Value A pointer to the 32-bit value to decrement.
> +
> + @return The decrement value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncDecrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + if (((UINTN)Value % sizeof (UINT32)) != 0) {
> + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__));
> + ASSERT (FALSE);
> + }
> + return SyncSyncDecrement32 (Value);
> +}
> diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> new file mode 100644
> index 0000000..943e274
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> @@ -0,0 +1,78 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V synchronization functions.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +#include <Base.h>
> +
> +.data
> +
> +.text
> +.align 3
> +
> +.global ASM_PFX(SyncCompareExchange32)
> +.global ASM_PFX(SyncCompareExchange64)
> +.global ASM_PFX(SyncSyncIncrement32)
> +.global ASM_PFX(SyncSyncDecrement32)
> +
> +//
> +// ompare and xchange a 32-bit value.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (SyncCompareExchange32):
> + lr.w a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.w a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit:
> + mv a0, a3
> + ret
> +
> +.global ASM_PFX(SyncCompareExchange64)
> +
> +//
> +// Compare and xchange a 64-bit value.
> +//
> +// @param a0 : Pointer to 64-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (SyncCompareExchange64):
> + lr.d a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.d a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit2:
> + mv a0, a3
> + ret
> +
> +//
> +// Performs an atomic increment of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (SyncSyncIncrement32):
> + li a1, 1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> +
> +//
> +// Performs an atomic decrement of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (SyncSyncDecrement32):
> + li a1, -1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
@ 2019-09-30 18:31 ` Leif Lindholm
2019-10-15 2:32 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 18:31 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:41AM +0800, Abner Chang wrote:
> This library provides CSR assembly functions to read/write RISC-V
> specific Control and Status registers.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++
> RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 +++++++++++++++++++++++++++
> RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++
Please ensure you have set up an orderfile, as described on
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-guide-for-edk2-contributors-and-maintainers
or by executing BaseTools/Scripts/SetupGit.py inside each repository.
> 3 files changed, 217 insertions(+)
> create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
> create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
> create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
>
> diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h
> new file mode 100644
> index 0000000..c84d599
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h
> @@ -0,0 +1,68 @@
> +/** @file
> + RISC-V CPU library definitions.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _RISCV_CPU_LIB_H_
> +#define _RISCV_CPU_LIB_H_
Please drop leading _.
> +
> +#include "RiscV.h"
Hmm. This raises two concerns.
First - style-wise, "" should not be used for anything but local (same
directory) include files.
Secondly, there are two separate files called RiscV.h introduced by
this patch series:
RiscVPkg/Include/IndustryStandard/RiscV.h
RiscVPkg/Include/RiscV.h
Have these been split solely in order to have one directly includable
in assembler?
If so, please merge them (in the IndustryStandard one), and put the
C-specific bits inside an #ifndef __ASSEMBLY__ statement.
If not, please provide a description of their logical split, and
rename one of them.
> +
> +/**
> + RISCV_TRAP_HANDLER
> +**/
> +typedef
> +VOID
> +(EFIAPI *RISCV_TRAP_HANDLER)(
> + VOID
> + );
> +
> +VOID
> +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
Please keep all names referring to architectural registers
identifiable. A quick Internet search suggests this may mean Machine
Scratch Register?
> +
> +UINT32
> +RiscVGetScratch (VOID);
> +
> +UINT32
> +RiscVGetTrapCause (VOID);
> +
> +UINT64
> +RiscVReadMachineTimer (VOID);
> +
> +VOID
> +RiscVSetMachineTimerCmp (UINT64);
Cmp neds expanding to its full name.
> +
> +UINT64
> +RiscVReadMachineTimerCmp(VOID);
> +
> +UINT64
> +RiscVReadMachineIE(VOID);
> +
> +UINT64
> +RiscVReadMachineIP(VOID);
IE/IP needs expanding, unless these are the names used in the
architecture reference. If it is, this file needs those terms
introduced in a glossary section at the start of this file.
> +
> +UINT64
> +RiscVReadMachineStatus(VOID);
> +
> +VOID
> +RiscVWriteMachineStatus(UINT64);
> +
> +UINT64
> +RiscVReadMachineTvec(VOID);
> +
> +UINT64
> +RiscVReadMisa (VOID);
Tvec/Misa need the same treatment as IE/IP.
If the M stands for Machine, it should be written out fully, and
likely isa should be Isa.
> +
> +UINT64
> +RiscVReadMVendorId (VOID);
> +
> +UINT64
> +RiscVReadMArchId (VOID);
> +
> +UINT64
> +RiscVReadMImplId (VOID);
Impl needs expanding - I can't tell whether that means Implementation
or Implmenter.
For all 3 above, is that M only an abbreviated Machine? If so, please
write it out fully.
> +
> +#endif
> diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> new file mode 100644
> index 0000000..f372397
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> @@ -0,0 +1,115 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V CPU functions.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +#include <Base.h>
> +#include <RiscV.h>
> +
> +.data
> +
> +.text
> +.align 3
> +
> +.global ASM_PFX(RiscVSetScratch)
> +.global ASM_PFX(RiscVGetScratch)
> +.global ASM_PFX(RiscVGetMachineTrapCause)
> +.global ASM_PFX(RiscVReadMachineIE)
> +.global ASM_PFX(RiscVReadMachineIP)
> +.global ASM_PFX(RiscVReadMachineStatus)
> +.global ASM_PFX(RiscVWriteMachineStatus)
> +.global ASM_PFX(RiscVReadMachineTvec)
> +.global ASM_PFX(RiscVReadMisa)
> +.global ASM_PFX(RiscVReadMVendorId)
> +.global ASM_PFX(RiscVReadMArchId)
> +.global ASM_PFX(RiscVReadMImplId)
This could get a lot neater if you replicate what we have for the
ARM/AARCH64 ports and implement an ASM_FUNC macro that does both the
global, and the prefix (and some more stuff that is less imortant now
we use lto anyway).
Have a look in ArmPkg/Include/AsmMacroIoLib*.h
> +//
> +// Set machine mode scratch.
> +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
> +//
> +ASM_PFX (RiscVSetScratch):
> + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
> + ret
> +
> +//
> +// Get machine mode scratch.
> +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
> +//
> +ASM_PFX (RiscVGetScratch):
> + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
> + ret
> +
> +//
> +// Get machine trap cause CSR.
> +//
> +ASM_PFX (RiscVGetMachineTrapCause):
> + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
> + ret
> +
> +//
> +// Get machine interrupt enable
> +//
> +ASM_PFX (RiscVReadMachineIE):
> + csrr a0, RISCV_CSR_MACHINE_MIE
> + ret
> +
> +//
> +// Get machine interrupt pending
> +//
> +ASM_PFX (RiscVReadMachineIP):
> + csrr a0, RISCV_CSR_MACHINE_MIP
> + ret
> +
> +//
> +// Get machine status
> +//
> +ASM_PFX(RiscVReadMachineStatus):
> + csrr a0, RISCV_CSR_MACHINE_MSTATUS
> + ret
> +
> +//
> +// Set machine status
> +//
> +ASM_PFX(RiscVWriteMachineStatus):
> + csrw RISCV_CSR_MACHINE_MSTATUS, a0
> + ret
> +
> +//
> +// Get machine trap vector
> +//
> +ASM_PFX(RiscVReadMachineTvec):
> + csrr a0, RISCV_CSR_MACHINE_MTVEC
> + ret
> +
> +//
> +// Read machine ISA
> +//
> +ASM_PFX(RiscVReadMisa):
> + csrr a0, RISCV_CSR_MACHINE_MISA
> + ret
> +
> +//
> +// Read machine vendor ID
> +//
> +ASM_PFX(RiscVReadMVendorId):
> + csrr a0, RISCV_CSR_MACHINE_MVENDORID
> + ret
> +
> +//
> +// Read machine architecture ID
> +//
> +ASM_PFX(RiscVReadMArchId):
> + csrr a0, RISCV_CSR_MACHINE_MARCHID
> + ret
> +
> +//
> +// Read machine implementation ID
> +//
> +ASM_PFX(RiscVReadMImplId):
> + csrr a0, RISCV_CSR_MACHINE_MIMPID
> + ret
> +
> diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> new file mode 100644
> index 0000000..fc9131b
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> @@ -0,0 +1,34 @@
> +## @file
> +# RISC-V RV64 CPU library
> +#
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVCpuLib
> + FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVCpuLib
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> +
> +[Sources.RISCV64]
> + Cpu.S
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
Please sort the above two alphabetically.
/
Leif
> + RiscVPkg/RiscVPkg.dec
> +
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
@ 2019-09-30 19:15 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 19:15 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:42AM +0800, Abner Chang wrote:
> Initial RISC-V Supervisor Mode trap handler
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../RiscVExceptionLib/CpuExceptionHandler.S | 88 ++++++++++
> .../CpuExceptionHandlerDxeLib.inf | 42 +++++
> .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++++++++++++++++
> .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 ++
> 4 files changed, 325 insertions(+)
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
>
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
> new file mode 100644
> index 0000000..cffe485
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
Since the actual handling is done elsewhere, would CpuExceptionEntry.S
be a more descriptive filename?
> @@ -0,0 +1,88 @@
> +/** @file
> + RISC-V Processor supervisor mode trap handler
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <RiscV.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_trap.h>
> +
> + .align 3
> + .section .entry, "ax", %progbits
> + .globl _strap_handler
> +_strap_handler:
Please rename this one:
- Drop _ from function name.
- Rename to proper CamelCase. Suggest: SupervisorTrapHandler.
> + addi sp, sp, -34*8
Please add spaces around '*', throughout.
> + /* Save all general regisers except SP and T0 */
> + sd ra, 1*8(sp)
> + sd gp, 2*8(sp)
> + sd tp, 3*8(sp)
> + sd t1, 4*8(sp)
> + sd t2, 5*8(sp)
> + sd s0, 6*8(sp)
> + sd s1, 7*8(sp)
> + sd a0, 8*8(sp)
> + sd a1, 9*8(sp)
> + sd a2, 10*8(sp)
> + sd a3, 11*8(sp)
> + sd a4, 12*8(sp)
> + sd a5, 13*8(sp)
> + sd a6, 14*8(sp)
> + sd a7, 15*8(sp)
> + sd s2, 16*8(sp)
> + sd s3, 17*8(sp)
> + sd s4, 18*8(sp)
> + sd s5, 19*8(sp)
> + sd s6, 20*8(sp)
> + sd s7, 21*8(sp)
> + sd s8, 22*8(sp)
> + sd s9, 23*8(sp)
> + sd s10, 24*8(sp)
> + sd s11, 25*8(sp)
> + sd t3, 26*8(sp)
> + sd t4, 27*8(sp)
> + sd t5, 28*8(sp)
> + sd t6, 29*8(sp)
> +
> + /* Call C routine */
Something like "Call main trap handling routine in x.c" would be more
helpful.
> + call RiscVSupervisorModeTrapHandler
> +
> + /* Restore all general regisers except SP and T0 */
> + ld ra, 1*8(sp)
> + ld gp, 2*8(sp)
> + ld tp, 3*8(sp)
> + ld t1, 4*8(sp)
> + ld t2, 5*8(sp)
> + ld s0, 6*8(sp)
> + ld s1, 7*8(sp)
> + ld a0, 8*8(sp)
> + ld a1, 9*8(sp)
> + ld a2, 10*8(sp)
> + ld a3, 11*8(sp)
> + ld a4, 12*8(sp)
> + ld a5, 13*8(sp)
> + ld a6, 14*8(sp)
> + ld a7, 15*8(sp)
> + ld s2, 16*8(sp)
> + ld s3, 17*8(sp)
> + ld s4, 18*8(sp)
> + ld s5, 19*8(sp)
> + ld s6, 20*8(sp)
> + ld s7, 21*8(sp)
> + ld s8, 22*8(sp)
> + ld s9, 23*8(sp)
> + ld s10, 24*8(sp)
> + ld s11, 25*8(sp)
> + ld t3, 26*8(sp)
> + ld t4, 27*8(sp)
> + ld t5, 28*8(sp)
> + ld t6, 29*8(sp)
> + addi sp, sp, 34*8
> + sret
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> new file mode 100644
> index 0000000..e5871dc
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> @@ -0,0 +1,42 @@
> +## @file
> +# RISC-V CPU Exception Handler Library
> +#
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = CpuExceptionHandlerLib
> + MODULE_UNI_FILE = CpuExceptionHandlerLib.uni
> + FILE_GUID = 16309FCF-E900-459C-B071-052118394D11
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = CpuExceptionHandlerLib
> + CONSTRUCTOR = CpuExceptionHandlerLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources.RISCV64]
> + CpuExceptionHandler.S
> +
> +[Sources.common]
> + CpuExceptionHandlerLib.c
> +
> +[LibraryClasses]
> + UefiBootServicesTableLib
> + BaseLib
> + DebugLib
> + RiscVCpuLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + RiscVPkg/RiscVPkg.dec
Please sort LibraryClasses and Packages alphabetically.
> +
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> new file mode 100644
> index 0000000..8c75be0
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> @@ -0,0 +1,182 @@
> +/** @file
> + RISC-V Exception Handler library implementition.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/CpuExceptionHandlerLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RiscVCpuLib.h>
> +#include <sbi/sbi_types.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_encoding.h>
Please sort sbi includes alphabetically.
> +
> +
> +extern void _strap_handler(void);
Please add this to a local include file.
> +EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2];
This (thankfully) seems to be global to the local file only.
Could it be renamed with a 'm' prefix and given STATIC attribute?
> +/**
> + Initializes all CPU exceptions entries and provides the default exception handlers.
> +
> + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
> + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
> + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
> + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
> +
> + @param[in] VectorInfo Pointer to reserved vector list.
> +
> + @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
> + with default exception handlers.
> + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
> + @retval EFI_UNSUPPORTED This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionHandlers (
> + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
> +
> + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
> + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
> + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
> + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
> +
> + @param[in] VectorInfo Pointer to reserved vector list.
> +
> + @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
> + with default interrupt/exception handlers.
> + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
> + @retval EFI_UNSUPPORTED This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuInterruptHandlers (
> + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Registers a function to be called from the processor interrupt handler.
> +
> + This function registers and enables the handler specified by InterruptHandler for a processor
> + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
> + handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
> + The installed handler is called once for each processor interrupt or exception.
> + NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
> + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
> +
> + @param[in] InterruptType Defines which interrupt or exception to hook.
> + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
> + when a processor interrupt occurs. If this parameter is NULL, then the handler
> + will be uninstalled.
> +
> + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
> + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
> + previously installed.
> + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
> + previously installed.
> + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
> + or this function is not supported.
> +**/
> +EFI_STATUS
> +EFIAPI
> +RegisterCpuInterruptHandler (
> + IN EFI_EXCEPTION_TYPE InterruptType,
> + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> + )
> +{
> +
> + DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler));
> + gInterruptHandlers[InterruptType] = InterruptHandler;
> + return EFI_SUCCESS;
> +}
> +/**
> + Machine mode trap handler.
> +
> +**/
> +VOID
> +RiscVSupervisorModeTrapHandler (
> + VOID
> + )
> +{
> + EFI_SYSTEM_CONTEXT RiscVSystemContext;
> +
> + //
> + // Check scasue register.
> + //
> + if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) {
> + gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
> + }
> +}
> +
> +/**
> + Initializes all CPU exceptions entries with optional extra initializations.
> +
> + By default, this method should include all functionalities implemented by
> + InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
> + This could be done by calling InitializeCpuExceptionHandlers() directly
> + in this method besides the extra works.
> +
> + InitData is optional and its use and content are processor arch dependent.
> + The typical usage of it is to convey resources which have to be reserved
> + elsewhere and are necessary for the extra initializations of exception.
> +
> + @param[in] VectorInfo Pointer to reserved vector list.
> + @param[in] InitData Pointer to data optional for extra initializations
> + of exception.
> +
> + @retval EFI_SUCCESS The exceptions have been successfully
> + initialized.
> + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid
> + content.
> + @retval EFI_UNSUPPORTED This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionHandlersEx (
> + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
> + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
> + )
> +{
> + return InitializeCpuExceptionHandlers (VectorInfo);
> +}
> +
> +/**
> + The constructor function to initial interrupt handlers in
> + RISCV_MACHINE_MODE_CONTEXT.
> +
> + @param ImageHandle The firmware allocated handle for the EFI image.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The destructor completed successfully.
> + @retval Other value The destructor did not complete successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuExceptionHandlerLibConstructor (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + //
> + // Set Superviosr mode trap handler.
> + //
> + csr_write(CSR_STVEC, _strap_handler);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> new file mode 100644
> index 0000000..00cca22
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys."
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys."
Library.
/
Leif
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
@ 2019-09-30 19:46 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 19:46 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:43AM +0800, Abner Chang wrote:
> Timer library for RISC-V
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++++
> RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++++++++++++++++
> RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +++
> RiscVPkg/RiscVPkg.dec | 9 +
> 4 files changed, 259 insertions(+)
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
>
> diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> new file mode 100644
> index 0000000..af27049
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> @@ -0,0 +1,34 @@
> +## @file
> +# RISC-V Timer Library Instance.
> +#
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = BaseRiscVTimerLib
> + FILE_GUID = FB648CF5-91BE-4737-9023-FD807AC6D96D
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = TimerLib
> +
> +[Sources]
> + RiscVTimerLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[Pcd]
> + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
> + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + RiscVCpuLib
> + RiscVPlatformTimerLib
> +
> diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> new file mode 100644
> index 0000000..acb8c77
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> @@ -0,0 +1,195 @@
> +/** @file
> + RISC-V instance of Timer Library.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <RiscVTimerLib.h>
> +
> +/**
> + Stalls the CPU for at least the given number of ticks.
> +
> + Stalls the CPU for at least the given number of ticks. It's invoked by
> + MicroSecondDelay() and NanoSecondDelay().
> +
> + @param Delay A period of time to delay in ticks.
> +
> +**/
> +VOID
> +InternalRiscVTimerDelay (
> + IN UINT32 Delay
> + )
> +{
> + UINT32 Ticks;
> + UINT32 Times;
> +
> + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
> + Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
> + do {
> + //
> + // The target timer count is calculated here
> + //
> + Ticks = RiscVReadMachineTimer () + Delay;
> + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
> + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
> + CpuPause ();
> + }
> + } while (Times-- > 0);
> +}
> +
> +/**
> + Stalls the CPU for at least the given number of microseconds.
> +
> + Stalls the CPU for the number of microseconds specified by MicroSeconds.
> +
> + @param MicroSeconds The minimum number of microseconds to delay.
> +
> + @return MicroSeconds
> +
> +**/
> +UINTN
> +EFIAPI
> +MicroSecondDelay (
> + IN UINTN MicroSeconds
> + )
> +{
> + InternalRiscVTimerDelay (
> + (UINT32)DivU64x32 (
> + MultU64x32 (
> + MicroSeconds,
> + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
> + ),
> + 1000000u
> + )
> + );
> + return MicroSeconds;
> +}
> +
> +/**
> + Stalls the CPU for at least the given number of nanoseconds.
> +
> + Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
> +
> + @param NanoSeconds The minimum number of nanoseconds to delay.
> +
> + @return NanoSeconds
> +
> +**/
> +UINTN
> +EFIAPI
> +NanoSecondDelay (
> + IN UINTN NanoSeconds
> + )
> +{
> + InternalRiscVTimerDelay (
> + (UINT32)DivU64x32 (
> + MultU64x32 (
> + NanoSeconds,
> + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
> + ),
> + 1000000000u
> + )
> + );
> + return NanoSeconds;
> +}
> +
> +/**
> + Retrieves the current value of a 64-bit free running performance counter.
> +
> + Retrieves the current value of a 64-bit free running performance counter. The
> + counter can either count up by 1 or count down by 1. If the physical
> + performance counter counts by a larger increment, then the counter values
> + must be translated. The properties of the counter can be retrieved from
> + GetPerformanceCounterProperties().
> +
> + @return The current value of the free running performance counter.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetPerformanceCounter (
> + VOID
> + )
> +{
> + return (UINT64)RiscVReadMachineTimer ();
> +}
> +
> +/**return
> + Retrieves the 64-bit frequency in Hz and the range of performance counter
> + values.
> +
> + If StartValue is not NULL, then the value that the performance counter starts
> + with immediately after is it rolls over is returned in StartValue. If
> + EndValue is not NULL, then the value that the performance counter end with
> + immediately before it rolls over is returned in EndValue. The 64-bit
> + frequency of the performance counter in Hz is always returned. If StartValue
> + is less than EndValue, then the performance counter counts up. If StartValue
> + is greater than EndValue, then the performance counter counts down. For
> + example, a 64-bit free running counter that counts up would have a StartValue
> + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
> + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
> +
> + @param StartValue The value the performance counter starts with when it
> + rolls over.
> + @param EndValue The value that the performance counter ends with before
> + it rolls over.
> +
> + @return The frequency in Hz.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetPerformanceCounterProperties (
> + OUT UINT64 *StartValue, OPTIONAL
> + OUT UINT64 *EndValue OPTIONAL
> + )
> +{
> + if (StartValue != NULL) {
> + *StartValue = 0;
> + }
> +
> + if (EndValue != NULL) {
> + *EndValue = 32 - 1;
> + }
> +
> + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);
> +}
> +
> +/**
> + Converts elapsed ticks of performance counter to time in nanoseconds.
> +
> + This function converts the elapsed ticks of running performance counter to
> + time value in unit of nanoseconds.
> +
> + @param Ticks The number of elapsed ticks of running performance counter.
> +
> + @return The elapsed time in nanoseconds.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetTimeInNanoSecond (
> + IN UINT64 Ticks
> + )
> +{
> + UINT64 NanoSeconds;
> + UINT32 Remainder;
> +
> + //
> + // Ticks
> + // Time = --------- x 1,000,000,000
> + // Frequency
> + //
> + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u);
> +
> + //
> + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
> + // will not overflow 64-bit.
> + //
> + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
> +
> + return NanoSeconds;
> +}
> diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
> new file mode 100644
> index 0000000..bac3a70
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
> @@ -0,0 +1,21 @@
> +/** @file
> + RISC-V timer library definitions.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#ifndef _RISCV_TIMER_LIB_INTERNAL_H_
> +#define _RISCV_TIMER_LIB_INTERNAL_H_
> +
> +#include <Uefi.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include <Library/RiscVCpuLib.h>
This header file includes only include statements.
Please delete the file and move the includes to the .c file, sorted
alphabtically.
/
Leif
> +
> +#endif // _RISCV_TIMER_LIB_INTERNAL_H_
> diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
> index 74314e8..a91392f 100644
> --- a/RiscVPkg/RiscVPkg.dec
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -23,5 +23,14 @@
> [Guids]
> gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
>
> +[PcdsFixedAtBuild]
> + #
> + # 1000000000
> + # PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
> + # PcdRiscVMachineTimerFrequencyInHerz
> + #
> + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UINT64|0x00001010
> + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011
> +
> [UserExtensions.TianoCore."ExtraFiles"]
> RiscVPkgExtra.uni
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
@ 2019-09-30 20:03 ` Leif Lindholm
2019-10-15 1:21 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:03 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:44AM +0800, Abner Chang wrote:
> EDK2 RISC-V OpenSBI library which pull in external source files under
> RiscVPkg/opensbi to the build process.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
>
> diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> new file mode 100644
> index 0000000..640ffba
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> @@ -0,0 +1,52 @@
> +## @file
> +# RISC-V Opensbi Library Instance.
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVOpensbiLib
> + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVOpensbiLib
> +
> +[Sources]
> + ../../opensbi/lib/sbi/riscv_asm.c
Please move the opensbi directory to here instead.
/
Leif
> + ../../opensbi/lib/sbi/riscv_atomic.c
> + ../../opensbi/lib/sbi/riscv_hardfp.S
> + ../../opensbi/lib/sbi/riscv_locks.c
> + ../../opensbi/lib/sbi/riscv_unpriv.c
> + ../../opensbi/lib/sbi/sbi_console.c
> + ../../opensbi/lib/sbi/sbi_ecall.c
> + ../../opensbi/lib/sbi/sbi_emulate_csr.c
> + ../../opensbi/lib/sbi/sbi_fifo.c
> + ../../opensbi/lib/sbi/sbi_hart.c
> + ../../opensbi/lib/sbi/sbi_illegal_insn.c
> + ../../opensbi/lib/sbi/sbi_init.c
> + ../../opensbi/lib/sbi/sbi_ipi.c
> + ../../opensbi/lib/sbi/sbi_misaligned_ldst.c
> + ../../opensbi/lib/sbi/sbi_scratch.c
> + ../../opensbi/lib/sbi/sbi_string.c
> + ../../opensbi/lib/sbi/sbi_system.c
> + ../../opensbi/lib/sbi/sbi_timer.c
> + ../../opensbi/lib/sbi/sbi_tlb.c
> + ../../opensbi/lib/sbi/sbi_trap.c
> + ../../opensbi/lib/utils/sys/clint.c
> + ../../opensbi/lib/utils/irqchip/plic.c
> + ../../opensbi/lib/utils/serial/sifive-uart.c
> + ../../opensbi/lib/utils/serial/uart8250.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + RiscVCpuLib
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
@ 2019-09-30 20:15 ` Leif Lindholm
2019-09-30 20:44 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:15 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:45AM +0800, Abner Chang wrote:
> RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE
> phase.
>
> RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI
> interface.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++
> .../RiscVDxeIplHandoffLib.inf | 32 +++++++
> .../RiscVDxeIplHandoffOpenSbiLib.c | 102 +++++++++++++++++++++
> .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++
> 4 files changed, 208 insertions(+)
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
>
> diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> new file mode 100644
> index 0000000..211b4e8
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> @@ -0,0 +1,41 @@
> +/** @file
> + RISC-V platform level DXE core hand off library
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +/**
> + RISC-V platform DXE IPL to DXE core handoff process.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param BaseOfStack Base address of stack
> + @param TopOfStack Top address of stack
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +
> +VOID
> +RiscVPlatformHandOffToDxeCore (
> + IN VOID *BaseOfStack,
> + IN VOID *TopOfStack,
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + )
> +{
> +
> + //
> + // Transfer the control to the entry point of DxeCore.
> + //
> + SwitchStack (
> + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
> + HobList.Raw,
> + NULL,
> + TopOfStack
> + );
> +}
> diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> new file mode 100644
> index 0000000..986db1d
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> @@ -0,0 +1,32 @@
> +## @file
> +# Instance of RISC-V DXE IPL to DXE core handoff platform library
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVPlatformDxeIplLib
> + FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
> +
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> + RiscVDxeIplHandoffLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + RiscVCpuLib
> + RiscVOpensbiLib
> +
> diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> new file mode 100644
> index 0000000..c640fd2
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> @@ -0,0 +1,102 @@
> +/** @file
> + RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include <sbi/sbi.h>
> +#include <sbi/sbi_hart.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_init.h>
> +#include <sbi/riscv_encoding.h>
> +#include <Library/RiscVCpuLib.h>
> +#include <Library/RiscVPlatformDxeIpl.h>
Please sort include files alphabetically.
> +
> +/**
> + RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
> + This function is executed in RISC-V Supervisor mode.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param BaseOfStack Base address of stack
> + @param TopOfStack Top address of stack
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +VOID
> +RiscVDxeIplHandoffOpenSbiHandler (
> + IN UINTN HardId,
> + IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
> + )
> +{
> + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n"));
I would prefer not having [OpenSBI] tags all over EDK2 code.
Use %a __FUNCTION__ if you want to indicate location.
This applies to the whole file.
> +
> + SwitchStack (
> + (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
> + ThisSwitchContext->HobList.Raw,
> + NULL,
> + ThisSwitchContext->TopOfStack
> + );
> +
> + //
> + // Shold never came back.
> + //
> + __builtin_unreachable();
Please use the UNREACHABLE () macro from Base.h.
/
Leif
> +}
> +
> +
> +/**
> + RISC-V platform DXE IPL to DXE core handoff process.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param BaseOfStack Base address of stack
> + @param TopOfStack Top address of stack
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +VOID
> +RiscVPlatformHandOffToDxeCore (
> + IN VOID *BaseOfStack,
> + IN VOID *TopOfStack,
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + )
> +{
> + struct sbi_scratch *ThisScratch;
> + OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
> +
> + DEBUG ((DEBUG_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n"));
> + //
> + // Setup next address in OpenSBI scratch
> + //
> + OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
> + OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
> + OpenSbiSwitchModeContext.HobList = HobList;
> + OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
> + ThisScratch = sbi_scratch_thishart_ptr ();
> + ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext;
> + ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler;
> + ThisScratch->next_mode = PRV_S;
> +
> + DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
> + DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack));
> + DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList));
> + DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
> + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
> + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
> + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
> + sbi_init (ThisScratch);
> +}
> diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> new file mode 100644
> index 0000000..262071d
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> @@ -0,0 +1,33 @@
> +## @file
> +# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVPlatformDxeIplLib
> + FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
> +
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> + RiscVDxeIplHandoffOpenSbiLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + RiscVCpuLib
> + RiscVOpensbiLib
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
@ 2019-09-30 20:31 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:31 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:46AM +0800, Abner Chang wrote:
> Implementation of RISC-V platform level DxeIPL
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++-
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 ++++++++++++++++++++++
> RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 +++++++++++++
> 3 files changed, 124 insertions(+), 1 deletion(-)
> create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index 98bc17f..5532323 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -7,6 +7,7 @@
> #
> # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -25,7 +26,7 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
> #
>
> [Sources]
> @@ -49,6 +50,9 @@
> [Sources.ARM, Sources.AARCH64]
> Arm/DxeLoadFunc.c
>
> +[Sources.RISCV64]
> + RiscV64/DxeLoadFunc.c
> +
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> @@ -56,6 +60,9 @@
> [Packages.ARM, Packages.AARCH64]
> ArmPkg/ArmPkg.dec
>
> +[Packages.RISCV64]
> + RiscVPkg/RiscVPkg.dec
> +
> [LibraryClasses]
> PcdLib
> MemoryAllocationLib
> @@ -75,6 +82,10 @@
> [LibraryClasses.ARM, LibraryClasses.AARCH64]
> ArmMmuLib
>
> +[LibraryClasses.RISCV64]
> + RiscVPlatformDxeIplLib
> + RiscVOpensbiLib
> +
> [Ppis]
> gEfiDxeIplPpiGuid ## PRODUCES
> gEfiPeiDecompressPpiGuid ## PRODUCES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> new file mode 100644
> index 0000000..d3c7f9d
> --- /dev/null
> +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> @@ -0,0 +1,71 @@
> +/** @file
> + RISC-V specific functionality for DxeLoad.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "DxeIpl.h"
> +#include "Library/RiscVPlatformDxeIpl.h"
Please use <>.
(Yes, I know all other architectures do this wrong in this module.)
> +
> +typedef
> +VOID*
> +(EFIAPI *DXEENTRYPOINT) (
> + IN VOID *HobStart
> + );
> +
> +/**
> + Transfers control to DxeCore.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +VOID
> +HandOffToDxeCore (
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + )
> +{
> + VOID *BaseOfStack;
> + VOID *TopOfStack;
> + EFI_STATUS Status;
> + //
> + //
> + // Allocate 128KB for the Stack
> + //
> + BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
> + ASSERT (BaseOfStack != NULL);
I think this deserves a DEBUG_ERROR message as well, given that we're
now also about to start overwriting things at some small offset from
address 0.
> +
> + //
> + // Compute the top of the stack we were allocated. Pre-allocate a UINTN
> + // for safety.
> + //
> + TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
> + TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
> +
> + //
> + // End of PEI phase signal
> + //
> + Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
> + ASSERT_EFI_ERROR (Status);
> +
Probably also deserves an ERROR.
> + //
> + // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
> + //
> + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
> +
> + DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack));
> +
> + //
> + // Transfer the control to the entry point of DxeCore.
> + //
> + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList);
> +}
> +
> diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> new file mode 100644
> index 0000000..4763397
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> @@ -0,0 +1,41 @@
> +/** @file
> + Header file of RISC-V platform DXE IPL
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _RISC_V_PLATFORM_DXEIPL_H_
> +#define _RISC_V_PLATFORM_DXEIPL_H_
Please drop leading _.
/
Leif
> +
> +typedef struct {
> + VOID *TopOfStack;
> + VOID *BaseOfStack;
> + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;
> + EFI_PEI_HOB_POINTERS HobList;
> +} OPENSBI_SWITCH_MODE_CONTEXT;
> +
> +/**
> + RISC-V platform DXE IPL to DXE core handoff process.
> +
> + This function performs a CPU architecture specific operations to execute
> + the entry point of DxeCore with the parameters of HobList.
> + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> +
> + @param BaseOfStack Base address of stack
> + @param TopOfStack Top address of stack
> + @param DxeCoreEntryPoint The entry point of DxeCore.
> + @param HobList The start of HobList passed to DxeCore.
> +
> +**/
> +
> +VOID
> +RiscVPlatformHandOffToDxeCore (
> + IN VOID *BaseOfStack,
> + IN VOID *TopOfStack,
> + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> + IN EFI_PEI_HOB_POINTERS HobList
> + );
> +#endif
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
2019-09-30 20:15 ` [edk2-devel] " Leif Lindholm
@ 2019-09-30 20:44 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:44 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 30, 2019 at 09:15:57PM +0100, Leif Lindholm wrote:
> On Mon, Sep 23, 2019 at 08:31:45AM +0800, Abner Chang wrote:
> > RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE
> > phase.
> >
> > RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI
> > interface.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++
> > .../RiscVDxeIplHandoffLib.inf | 32 +++++++
> > .../RiscVDxeIplHandoffOpenSbiLib.c | 102 +++++++++++++++++++++
> > .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++
> > 4 files changed, 208 insertions(+)
> > create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> > create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> > create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> > create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> >
> > diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> > new file mode 100644
> > index 0000000..211b4e8
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> > @@ -0,0 +1,41 @@
> > +/** @file
> > + RISC-V platform level DXE core hand off library
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +**/
> > +
> > +/**
> > + RISC-V platform DXE IPL to DXE core handoff process.
> > +
> > + This function performs a CPU architecture specific operations to execute
> > + the entry point of DxeCore with the parameters of HobList.
> > + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> > +
> > + @param BaseOfStack Base address of stack
> > + @param TopOfStack Top address of stack
> > + @param DxeCoreEntryPoint The entry point of DxeCore.
> > + @param HobList The start of HobList passed to DxeCore.
> > +
> > +**/
> > +
> > +VOID
> > +RiscVPlatformHandOffToDxeCore (
> > + IN VOID *BaseOfStack,
> > + IN VOID *TopOfStack,
> > + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> > + IN EFI_PEI_HOB_POINTERS HobList
> > + )
> > +{
> > +
> > + //
> > + // Transfer the control to the entry point of DxeCore.
> > + //
> > + SwitchStack (
> > + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
> > + HobList.Raw,
> > + NULL,
> > + TopOfStack
> > + );
> > +}
> > diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> > new file mode 100644
> > index 0000000..986db1d
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> > @@ -0,0 +1,32 @@
> > +## @file
> > +# Instance of RISC-V DXE IPL to DXE core handoff platform library
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVPlatformDxeIplLib
> > + FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
> > + MODULE_TYPE = PEIM
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
> > +
> > +#
> > +# VALID_ARCHITECTURES = RISCV64
> > +#
> > +
> > +[Sources]
> > + RiscVDxeIplHandoffLib.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +[LibraryClasses]
> > + DebugLib
> > + RiscVCpuLib
> > + RiscVOpensbiLib
> > +
> > diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> > new file mode 100644
> > index 0000000..c640fd2
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
> > @@ -0,0 +1,102 @@
> > +/** @file
> > + RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +**/
> > +
> > +#include <PiPei.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/BaseLib.h>
> > +
> > +#include <sbi/sbi.h>
> > +#include <sbi/sbi_hart.h>
> > +#include <sbi/sbi_scratch.h>
> > +#include <sbi/sbi_init.h>
> > +#include <sbi/riscv_encoding.h>
> > +#include <Library/RiscVCpuLib.h>
> > +#include <Library/RiscVPlatformDxeIpl.h>
>
> Please sort include files alphabetically.
>
> > +
> > +/**
> > + RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
> > + This function is executed in RISC-V Supervisor mode.
> > +
> > + This function performs a CPU architecture specific operations to execute
> > + the entry point of DxeCore with the parameters of HobList.
> > + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> > +
> > + @param BaseOfStack Base address of stack
> > + @param TopOfStack Top address of stack
> > + @param DxeCoreEntryPoint The entry point of DxeCore.
> > + @param HobList The start of HobList passed to DxeCore.
> > +
> > +**/
> > +VOID
> > +RiscVDxeIplHandoffOpenSbiHandler (
> > + IN UINTN HardId,
> > + IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
> > + )
> > +{
> > + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n"));
>
> I would prefer not having [OpenSBI] tags all over EDK2 code.
> Use %a __FUNCTION__ if you want to indicate location.
> This applies to the whole file.
>
> > +
> > + SwitchStack (
> > + (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
> > + ThisSwitchContext->HobList.Raw,
> > + NULL,
> > + ThisSwitchContext->TopOfStack
> > + );
> > +
> > + //
> > + // Shold never came back.
> > + //
> > + __builtin_unreachable();
>
> Please use the UNREACHABLE () macro from Base.h.
>
> /
> Leif
>
> > +}
> > +
> > +
> > +/**
> > + RISC-V platform DXE IPL to DXE core handoff process.
> > +
> > + This function performs a CPU architecture specific operations to execute
> > + the entry point of DxeCore with the parameters of HobList.
> > + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
> > +
> > + @param BaseOfStack Base address of stack
> > + @param TopOfStack Top address of stack
> > + @param DxeCoreEntryPoint The entry point of DxeCore.
> > + @param HobList The start of HobList passed to DxeCore.
> > +
> > +**/
> > +VOID
> > +RiscVPlatformHandOffToDxeCore (
> > + IN VOID *BaseOfStack,
> > + IN VOID *TopOfStack,
> > + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
> > + IN EFI_PEI_HOB_POINTERS HobList
> > + )
> > +{
> > + struct sbi_scratch *ThisScratch;
> > + OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
> > +
> > + DEBUG ((DEBUG_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n"));
> > + //
> > + // Setup next address in OpenSBI scratch
> > + //
> > + OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
> > + OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
> > + OpenSbiSwitchModeContext.HobList = HobList;
> > + OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
> > + ThisScratch = sbi_scratch_thishart_ptr ();
> > + ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext;
> > + ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler;
Oh yes - these (unsigned long) statements need to be be replaced with
something better. Is UINTN insufficient?
In fact, there are several additional instances in Include/sbi/sbi.h.
/
Leif
> > + ThisScratch->next_mode = PRV_S;
> > +
> > + DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
> > + DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack));
> > + DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList));
> > + DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
> > + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
> > + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
> > + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
> > + sbi_init (ThisScratch);
> > +}
> > diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> > new file mode 100644
> > index 0000000..262071d
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
> > @@ -0,0 +1,33 @@
> > +## @file
> > +# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVPlatformDxeIplLib
> > + FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
> > + MODULE_TYPE = PEIM
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
> > +
> > +#
> > +# VALID_ARCHITECTURES = RISCV64
> > +#
> > +
> > +[Sources]
> > + RiscVDxeIplHandoffOpenSbiLib.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +[LibraryClasses]
> > + DebugLib
> > + RiscVCpuLib
> > + RiscVOpensbiLib
> > +
> > --
> > 2.7.4
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
@ 2019-09-30 20:54 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:54 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:47AM +0800, Abner Chang wrote:
> Implementation of RISC-V PEI Service Table Pointer library using
> RISC-V OpenSbi.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../PeiServicesTablePointerLibOpenSbi.inf | 38 +++++++
> .../PeiServicesTablePointerLibOpenSbi.uni | 23 ++++
> .../PeiServicesTablePointerOpenSbi.c | 121 +++++++++++++++++++++
> 3 files changed, 182 insertions(+)
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
>
> diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> new file mode 100644
> index 0000000..0b029ae
> --- /dev/null
> +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> @@ -0,0 +1,38 @@
> +## @file
> +# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
> +#
> +# PEI Services Table Pointer Library implementation that retrieves a pointer to the
> +# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = PeiServicesTablePointerLibOpenSbi
> + MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni
> + FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
> +
> + CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor
> +
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> + PeiServicesTablePointerOpenSbi.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + RiscVCpuLib
> + RiscVOpensbiLib
> diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> new file mode 100644
> index 0000000..f6fad8b
> --- /dev/null
> +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> @@ -0,0 +1,23 @@
> +// /** @file
> +//
> +// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
> +//
> +// PEI Services Table Pointer Library implementation that retrieves a pointer to the
> +// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
> +//
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// This program and the accompanying materials
> +// are licensed and made available under the terms and conditions of the BSD License
> +// which accompanies this distribution. The full text of the license may be found at
> +// http://opensource.org/licenses/bsd-license.php.
> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
> +
> diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> new file mode 100644
> index 0000000..915964f
> --- /dev/null
> +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> @@ -0,0 +1,121 @@
> +/** @file
> + PEI Services Table Pointer Library.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RiscVCpuLib.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/SbiFirmwareContext.h>
Please sort the include files alphabetically.
> +
> +/**
> + Caches a pointer PEI Services Table.
> +
> + Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
> + in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
> + Pre-EFI Initialization Core Interface Specification.
> +
> + If PeiServicesTablePointer is NULL, then ASSERT().
> +
> + @param PeiServicesTablePointer The address of PeiServices pointer.
> +**/
> +VOID
> +EFIAPI
> +SetPeiServicesTablePointer (
> + IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
> + )
> +{
> + struct sbi_platform *ThisSbiPlatform;
> + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
> +
> + ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
> + FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
> + FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
> +
> + DEBUG ((DEBUG_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Context at 0x%x\n",
Please drop the [OpenSBI] tag from the message.
> + PeiServicesTablePointer,
> + ThisSbiPlatform->firmware_context
> + ));
Indentation is off.
/
Leif
> +}
> +
> +/**
> + Retrieves the cached value of the PEI Services Table pointer.
> +
> + Returns the cached value of the PEI Services Table pointer in a CPU specific manner
> + as specified in the CPU binding section of the Platform Initialization Pre-EFI
> + Initialization Core Interface Specification.
> +
> + If the cached PEI Services Table pointer is NULL, then ASSERT().
> +
> + @return The pointer to PeiServices.
> +
> +**/
> +CONST EFI_PEI_SERVICES **
> +EFIAPI
> +GetPeiServicesTablePointer (
> + VOID
> + )
> +{
> + struct sbi_platform *ThisSbiPlatform;
> + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
> +
> + ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
> + FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
> + return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
> +}
> +
> +/**
> + The constructor function caches the pointer to PEI services.
> +
> + The constructor function caches the pointer to PEI services.
> + It will always return EFI_SUCCESS.
> +
> + @param FileHandle The handle of FFS header the loaded driver.
> + @param PeiServices The pointer to the PEI services.
> +
> + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiServicesTablePointerLibOpenSbiConstructor (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + SetPeiServicesTablePointer (PeiServices);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Perform CPU specific actions required to migrate the PEI Services Table
> + pointer from temporary RAM to permanent RAM.
> +
> + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
> + immediately preceding the Interrupt Descriptor Table (IDT) in memory.
> + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
> + immediately preceding the Interrupt Descriptor Table (IDT) in memory.
> + For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
> + a dedicated CPU register. This means that there is no memory storage
> + associated with storing the PEI Services Table pointer, so no additional
> + migration actions are required for Itanium or ARM CPUs.
> +
> +**/
> +VOID
> +EFIAPI
> +MigratePeiServicesTablePointer (
> + VOID
> + )
> +{
> + //
> + // PEI Services Table pointer is cached in the global variable. No additional
> + // migration actions are required.
> + //
> + return;
> +}
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
@ 2019-09-30 20:56 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 20:56 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:48AM +0800, Abner Chang wrote:
> NULL instance of RISC-V Platform Temporary Memory library.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../Library/RiscVPlatformTempMemoryInitLib.h | 17 +++++++++++
> .../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++++++++++++++++++++++
> .../Riscv64/TempMemInit.S | 26 +++++++++++++++++
> 3 files changed, 77 insertions(+)
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
> create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
> create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
>
> diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
> new file mode 100644
> index 0000000..11dfcfb
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
> @@ -0,0 +1,17 @@
> +/** @file
> + RISC-V package definitions.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _RISCV_PLATFORM_TEMP_MEM_LIB_H_
> +#define _RISCV_PLATFORM_TEMP_MEM_LIB_H_
> +
> +#include "RiscV.h"
If you drop the leading _ above, and use <> for include:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +
> +VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
> +UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID);
> +UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID);
> +#endif
> diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
> new file mode 100644
> index 0000000..12fa497
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
> @@ -0,0 +1,34 @@
> +## @file
> +# RISC-V platform temporary memory library.
> +#
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVPlatformTempMemoryInitLibNull
> + FILE_GUID = 67294857-C0F8-4ACB-8237-D91FE506B710
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVPlatformTempMemoryInitLib
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> +
> +[Sources.RISCV64]
> + Riscv64/TempMemInit.S
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +
> diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
> new file mode 100644
> index 0000000..61a9923
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
> @@ -0,0 +1,26 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V RiscVPlatformTemporaryMemInit.
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +#include <Base.h>
> +
> +.data
> +
> +.text
> +.align 3
> +
> +.global ASM_PFX(RiscVPlatformTemporaryMemInit)
> +
> +//
> +// @retval a0 Temporary memory base.
> +// a1 Temporary memory size.
> +//
> +ASM_PFX(RiscVPlatformTemporaryMemInit):
> + li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
> + li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
> + ret
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
@ 2019-09-30 21:11 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 21:11 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:49AM +0800, Abner Chang wrote:
> The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V
> platform level timer library.
>
> Due to RISC-V timer CSR is platform implementation specific,
Please expand CSR.
> RISC-V CPU DXE driver invokes platform level timer library
> to access to timer CSRs.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 ++++++++++++++++++++++++++++++
> RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++++++++++++++
> RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++++++
> RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 ++
> RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 ++
> 5 files changed, 607 insertions(+)
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
>
> diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
> new file mode 100644
> index 0000000..30d1115
> --- /dev/null
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
> @@ -0,0 +1,318 @@
> +/** @file
> + RISC-V CPU DXE driver.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "CpuDxe.h"
> +
> +//
> +// Global Variables
> +//
> +BOOLEAN InterruptState = FALSE;
Global variables need m or g prefix.
> +EFI_HANDLE mCpuHandle = NULL;
> +BOOLEAN mIsFlushingGCD;
Please use STATIC on variables global only in current file.
> +
> +EFI_CPU_ARCH_PROTOCOL gCpu = {
> + CpuFlushCpuDataCache,
> + CpuEnableInterrupt,
> + CpuDisableInterrupt,
> + CpuGetInterruptState,
> + CpuInit,
> + CpuRegisterInterruptHandler,
> + CpuGetTimerValue,
> + CpuSetMemoryAttributes,
> + 1, // NumberOfTimers
> + 4 // DmaBufferAlignment
> +};
> +
> +//
> +// CPU Arch Protocol Functions
> +//
> +
> +/**
> + Flush CPU data cache. If the instruction cache is fully coherent
> + with all DMA operations then function can just return EFI_SUCCESS.
> +
> + @param This Protocol instance structure
> + @param Start Physical address to start flushing from.
> + @param Length Number of bytes to flush. Round up to chipset
> + granularity.
> + @param FlushType Specifies the type of flush operation to perform.
> +
> + @retval EFI_SUCCESS If cache was flushed
> + @retval EFI_UNSUPPORTED If flush type is not supported.
> + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuFlushCpuDataCache (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_PHYSICAL_ADDRESS Start,
> + IN UINT64 Length,
> + IN EFI_CPU_FLUSH_TYPE FlushType
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Enables CPU interrupts.
> +
> + @param This Protocol instance structure
> +
> + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuEnableInterrupt (
> + IN EFI_CPU_ARCH_PROTOCOL *This
> + )
> +{
> + EnableInterrupts ();
> + InterruptState = TRUE;
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Disables CPU interrupts.
> +
> + @param This Protocol instance structure
> +
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuDisableInterrupt (
> + IN EFI_CPU_ARCH_PROTOCOL *This
> + )
> +{
> + DisableInterrupts ();
> + InterruptState = FALSE;
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Return the state of interrupts.
> +
> + @param This Protocol instance structure
> + @param State Pointer to the CPU's current interrupt state
> +
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> + @retval EFI_INVALID_PARAMETER State is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuGetInterruptState (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + OUT BOOLEAN *State
> + )
> +{
> + if (State == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *State = InterruptState;
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Generates an INIT to the CPU.
> +
> + @param This Protocol instance structure
> + @param InitType Type of CPU INIT to perform
> +
> + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
> + seen.
> + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuInit (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_CPU_INIT_TYPE InitType
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Registers a function to be called from the CPU interrupt handler.
> +
> + @param This Protocol instance structure
> + @param InterruptType Defines which interrupt to hook. IA-32
> + valid range is 0x00 through 0xFF
> + @param InterruptHandler A pointer to a function of type
> + EFI_CPU_INTERRUPT_HANDLER that is called
> + when a processor interrupt occurs. A null
> + pointer is an error condition.
> +
> + @retval EFI_SUCCESS If handler installed or uninstalled.
> + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
> + for InterruptType was previously installed.
> + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
> + InterruptType was not previously installed.
> + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
> + is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuRegisterInterruptHandler (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_EXCEPTION_TYPE InterruptType,
> + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> + )
> +{
> + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
> +}
> +
> +
> +/**
> + Returns a timer value from one of the CPU's internal timers. There is no
> + inherent time interval between ticks but is a function of the CPU frequency.
> +
> + @param This - Protocol instance structure.
> + @param TimerIndex - Specifies which CPU timer is requested.
> + @param TimerValue - Pointer to the returned timer value.
> + @param TimerPeriod - A pointer to the amount of time that passes
> + in femtoseconds (10-15) for each increment
> + of TimerValue. If TimerValue does not
> + increment at a predictable rate, then 0 is
> + returned. The amount of time that has
> + passed between two calls to GetTimerValue()
> + can be calculated with the formula
> + (TimerValue2 - TimerValue1) * TimerPeriod.
> + This parameter is optional and may be NULL.
> +
> + @retval EFI_SUCCESS - If the CPU timer count was returned.
> + @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
> + @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
> + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuGetTimerValue (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN UINT32 TimerIndex,
> + OUT UINT64 *TimerValue,
> + OUT UINT64 *TimerPeriod OPTIONAL
> + )
> +{
> + if (TimerValue == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (TimerIndex != 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *TimerValue = (UINT64)RiscVReadMachineTimer ();
> + if (TimerPeriod != NULL) {
> + *TimerPeriod = DivU64x32 (
> + 1000000000000000u,
> + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
> + );
> + }
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
> +
> + This function modifies the attributes for the memory region specified by BaseAddress and
> + Length from their current attributes to the attributes specified by Attributes.
> +
> + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> + @param BaseAddress The physical address that is the start address of a memory region.
> + @param Length The size in bytes of the memory region.
> + @param Attributes The bit mask of attributes to set for the memory region.
> +
> + @retval EFI_SUCCESS The attributes were set for the memory region.
> + @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
> + BaseAddress and Length cannot be modified.
> + @retval EFI_INVALID_PARAMETER Length is zero.
> + Attributes specified an illegal combination of attributes that
> + cannot be set together.
> + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
> + the memory resource range.
> + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
> + resource range specified by BaseAddress and Length.
> + The bit mask of attributes is not support for the memory resource
> + range specified by BaseAddress and Length.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuSetMemoryAttributes (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT64 Length,
> + IN UINT64 Attributes
> + )
> +{
> + DEBUG ((DEBUG_INFO, "%a:Set memory attributes not supported yet\n", __FUNCTION__));
Suggest space after :.
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Initialize the state information for the CPU Architectural Protocol.
> +
> + @param ImageHandle Image handle this driver.
> + @param SystemTable Pointer to the System Table.
> +
> + @retval EFI_SUCCESS Thread can be successfully created
> + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> + @retval EFI_DEVICE_ERROR Cannot create the thread
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpu (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Machine mode handler is initiated in CpuExceptionHandlerLibConstructor in
> + // CpuExecptionHandlerLib.
> + //
> +
> + //
> + // Make sure interrupts are disabled
> + //
> + DisableInterrupts ();
> +
> + //
> + // Install CPU Architectural Protocol
> + //
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mCpuHandle,
> + &gEfiCpuArchProtocolGuid, &gCpu,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> + return Status;
> +}
> +
> diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
> new file mode 100644
> index 0000000..e423fae
> --- /dev/null
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
> @@ -0,0 +1,206 @@
> +/** @file
> + RISC-V CPU DXE module header file.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _CPU_DXE_H_
> +#define _CPU_DXE_H_
Please drop leading _.
> +
> +#include <PiDxe.h>
> +
> +#include <Protocol/Cpu.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/CpuLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/CpuExceptionHandlerLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/RiscVCpuLib.h>
Please keep only the include statements required for this file.
(And please sort the remaining ones alphabetically.)
> +
> +/**
> + Flush CPU data cache. If the instruction cache is fully coherent
> + with all DMA operations then function can just return EFI_SUCCESS.
> +
> + @param This Protocol instance structure
> + @param Start Physical address to start flushing from.
> + @param Length Number of bytes to flush. Round up to chipset
> + granularity.
> + @param FlushType Specifies the type of flush operation to perform.
> +
> + @retval EFI_SUCCESS If cache was flushed
> + @retval EFI_UNSUPPORTED If flush type is not supported.
> + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuFlushCpuDataCache (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_PHYSICAL_ADDRESS Start,
> + IN UINT64 Length,
> + IN EFI_CPU_FLUSH_TYPE FlushType
> + );
> +
> +/**
> + Enables CPU interrupts.
> +
> + @param This Protocol instance structure
> +
> + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuEnableInterrupt (
> + IN EFI_CPU_ARCH_PROTOCOL *This
> + );
> +
> +/**
> + Disables CPU interrupts.
> +
> + @param This Protocol instance structure
> +
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuDisableInterrupt (
> + IN EFI_CPU_ARCH_PROTOCOL *This
> + );
> +
> +/**
> + Return the state of interrupts.
> +
> + @param This Protocol instance structure
> + @param State Pointer to the CPU's current interrupt state
> +
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> + @retval EFI_INVALID_PARAMETER State is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuGetInterruptState (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + OUT BOOLEAN *State
> + );
> +
> +/**
> + Generates an INIT to the CPU.
> +
> + @param This Protocol instance structure
> + @param InitType Type of CPU INIT to perform
> +
> + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
> + seen.
> + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuInit (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_CPU_INIT_TYPE InitType
> + );
> +
> +/**
> + Registers a function to be called from the CPU interrupt handler.
> +
> + @param This Protocol instance structure
> + @param InterruptType Defines which interrupt to hook. IA-32
> + valid range is 0x00 through 0xFF
> + @param InterruptHandler A pointer to a function of type
> + EFI_CPU_INTERRUPT_HANDLER that is called
> + when a processor interrupt occurs. A null
> + pointer is an error condition.
> +
> + @retval EFI_SUCCESS If handler installed or uninstalled.
> + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
> + for InterruptType was previously installed.
> + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
> + InterruptType was not previously installed.
> + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
> + is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuRegisterInterruptHandler (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_EXCEPTION_TYPE InterruptType,
> + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> + );
> +
> +/**
> + Returns a timer value from one of the CPU's internal timers. There is no
> + inherent time interval between ticks but is a function of the CPU frequency.
> +
> + @param This - Protocol instance structure.
> + @param TimerIndex - Specifies which CPU timer is requested.
> + @param TimerValue - Pointer to the returned timer value.
> + @param TimerPeriod - A pointer to the amount of time that passes
> + in femtoseconds (10-15) for each increment
> + of TimerValue. If TimerValue does not
> + increment at a predictable rate, then 0 is
> + returned. The amount of time that has
> + passed between two calls to GetTimerValue()
> + can be calculated with the formula
> + (TimerValue2 - TimerValue1) * TimerPeriod.
> + This parameter is optional and may be NULL.
> +
> + @retval EFI_SUCCESS - If the CPU timer count was returned.
> + @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
> + @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
> + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuGetTimerValue (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN UINT32 TimerIndex,
> + OUT UINT64 *TimerValue,
> + OUT UINT64 *TimerPeriod OPTIONAL
> + );
> +
> +/**
> + Set memory cacheability attributes for given range of memeory.
> +
> + @param This Protocol instance structure
> + @param BaseAddress Specifies the start address of the
> + memory range
> + @param Length Specifies the length of the memory range
> + @param Attributes The memory cacheability for the memory range
> +
> + @retval EFI_SUCCESS If the cacheability of that memory range is
> + set successfully
> + @retval EFI_UNSUPPORTED If the desired operation cannot be done
> + @retval EFI_INVALID_PARAMETER The input parameter is not correct,
> + such as Length = 0
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuSetMemoryAttributes (
> + IN EFI_CPU_ARCH_PROTOCOL *This,
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT64 Length,
> + IN UINT64 Attributes
> + );
> +
> +#endif
> +
> diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> new file mode 100644
> index 0000000..1931f45
> --- /dev/null
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> @@ -0,0 +1,56 @@
> +## @file
> +# RISC-V CPU DXE module.
> +#
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = CpuDxe
> + MODULE_UNI_FILE = CpuDxe.uni
> + FILE_GUID = 1A1E4886-9517-440e-9FDE-3BE44CEE2136
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> +
> + ENTRY_POINT = InitializeCpu
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
Please sort alphabetically.
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + CpuLib
> + DebugLib
> + DxeServicesTableLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> + CpuExceptionHandlerLib
> + TimerLib
> + SynchronizationLib
> + HobLib
> + ReportStatusCodeLib
> + RiscVCpuLib
> + RiscVPlatformTimerLib
Please sort the above alphabetically.
Also please check whether *all* of these are really used by this
driver.
/
Leif
> +
> +[Sources]
> + CpuDxe.c
> + CpuDxe.h
> +
> +[Protocols]
> + gEfiCpuArchProtocolGuid ## PRODUCES
> +
> +[Pcd]
> + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
> +
> +[Depex]
> + TRUE
> +
> +[UserExtensions.TianoCore."ExtraFiles"]
> + CpuDxeExtra.uni
> diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> new file mode 100644
> index 0000000..460141a
> --- /dev/null
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V CPU Architecture Protocol"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver installs CPU Architecture Protocol."
> +
> diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> new file mode 100644
> index 0000000..6f819f0
> --- /dev/null
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> @@ -0,0 +1,14 @@
> +// /** @file
> +// CpuDxe Localized Strings and Content
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +#string STR_PROPERTIES_MODULE_NAME
> +#language en-US
> +"RISC-V Architectural DXE Driver"
> +
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
@ 2019-09-30 22:39 ` Leif Lindholm
2019-10-14 11:27 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 22:39 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:52AM +0800, Abner Chang wrote:
> RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
> and type 44 records.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++++
> RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++++
> RiscVPkg/RiscVPkg.dec | 6 +
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 +++++++++++++++++++++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++++
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
> .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
> 8 files changed, 613 insertions(+)
> create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
> create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
>
> diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include/ProcessorSpecificDataHob.h
> new file mode 100644
> index 0000000..6798a9d
> --- /dev/null
> +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h
None of the things defined in here are HOBs, they are structures to
hold information that will be put into HOBs.
Can we merge all of these definitions into
SmbiosProcessorSpecificData.h and delete this file?
> @@ -0,0 +1,95 @@
> +/** @file
> + Definition of Processor Specific Data HOB.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
> +#define _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
Please drop leading _.
> +
> +#include <IndustryStandard/SmBios.h>
This file also uses Uefi.h, please include it, so we don't depend on
other files pulling it in for us.
> +
> +#define TO_BE_FILLED 0
> +#define TO_BE_FILLED_BY_VENDOR 0
> +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
> +#define TO_BE_FILLED_BY_CODE 0
These defines are never used, please drop,
> +
> +#pragma pack(1)
> +
> +///
> +/// RISC-V processor specific data HOB
> +///
> +typedef struct {
> + EFI_GUID ParentPrcessorGuid;
> + UINTN ParentProcessorUid;
> + EFI_GUID CoreGuid;
> + VOID *Context; // The additional information of this core which
> + // built in PEI phase and carried to DXE phase.
> + // The content is pocessor or platform specific.
> + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
> +} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB;
> +
> +///
> +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
> +///
> +typedef struct {
> + EFI_GUID PrcessorGuid;
> + UINTN ProcessorUid;
> + SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
> + UINT16 EndingZero;
Please align indentation of struct members.
> +} RISC_V_PROCESSOR_TYPE4_DATA_HOB;
> +
> +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
> +
> +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
> + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
> + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
> + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
> +
> +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
> +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
> +
> +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
> +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> +
> +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
> +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
> +
> +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
> +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> +///
> +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
> +///
> +typedef struct {
> + EFI_GUID PrcessorGuid;
> + UINTN ProcessorUid;
> + SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
> + UINT16 EndingZero;
> +} RISC_V_PROCESSOR_TYPE7_DATA_HOB;
> +
> +///
> +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
> +///
> +typedef struct {
> + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor;
> + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache;
> + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache;
> + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache;
> + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache;
> +} RISC_V_PROCESSOR_SMBIOS_DATA_HOB;
I don't see this structure being used anywhere - can it be deleted?
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> new file mode 100644
> index 0000000..36aa4ab
> --- /dev/null
> +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> @@ -0,0 +1,58 @@
> +/** @file
> + Industry Standard Definitions of RISC-V Processor Specific data defined in
> + below link for complaiant with SMBIOS Table Specification v3.3.0.
> + https://github.com/riscv/riscv-smbios
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
> +#define _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
Drop leading _.
> +
> +#include <IndustryStandard/SmBios.h>
> +
> +#include <RiscV.h>
> +
> +#pragma pack(1)
> +
> +typedef enum{
> + RegisterUnsupported = 0x00,
> + RegisterLen32 = 0x01,
> + RegisterLen64 = 0x02,
> + RegisterLen128 = 0x03
> +} RISC_V_REGISTER_LENGTH;
> +
> +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
> +
> +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
> +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
> +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
> +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
> +
> +///
> +/// RISC-V processor specific data for SMBIOS type 44
> +///
> +typedef struct {
> + UINT16 Revision;
> + UINT8 Length;
> + RISCV_UINT128 HartId;
> + UINT8 BootHartId;
> + RISCV_UINT128 MachineVendorId;
> + RISCV_UINT128 MachineArchId;
> + RISCV_UINT128 MachineImplId;
> + UINT32 InstSetSupported;
> + UINT8 PrivilegeModeSupported;
> + RISCV_UINT128 MModeExcepDelegation;
> + RISCV_UINT128 MModeInterruptDelegation;
> + UINT8 HartXlen;
> + UINT8 MachineModeXlen;
> + UINT8 Reserved;
> + UINT8 SupervisorModeXlen;
> + UINT8 UserModeXlen;
> +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
> +
> +#pragma pack()
> +#endif
> +
> diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
> index a91392f..b316223 100644
> --- a/RiscVPkg/RiscVPkg.dec
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -24,6 +24,12 @@
> gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
>
> [PcdsFixedAtBuild]
> + # Processor Specific Data GUID HOB GUID
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
> +
> #
> # 1000000000
> # PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> new file mode 100644
> index 0000000..032f559
> --- /dev/null
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> @@ -0,0 +1,339 @@
> +/** @file
> + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "RiscVSmbiosDxe.h"
> +
> +#define RISCV_SMBIOS_DEBUG_INFO 1
I would greatly prefer if we could drop this and
If there's still active development of the tables, I can go along with
keeping it while on the -staging branch, but it needs to go before the
port is merged to edk2 master.
You can use DEBUG_VERBOSE instead.
> +
> +EFI_SMBIOS_PROTOCOL *Smbios;
mSmBios. And STATIC.
> +
> +/**
> + This function builds SMBIOS type 7 record according to
> + the given RISC_V_PROCESSOR_TYPE7_DATA_HOB.
> +
> + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
> + @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_DATA_HOB
> + @param SmbiosHandle Pointer to SMBIOS_HANDLE
> +
> + @retval EFI_STATUS
> +
> +**/
> +static
STATIC
> +EFI_STATUS
> +BuildSmbiosType7 (
> + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
> + IN RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob,
> + OUT SMBIOS_HANDLE *SmbiosHandle
> +)
> +{
> + EFI_STATUS Status;
> + SMBIOS_HANDLE Handle;
> +
> + if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
> + Type4DataHob->ProcessorUid != Type7DataHob->ProcessorUid) {
> + return EFI_INVALID_PARAMETER;
> + }
> + Handle = SMBIOS_HANDLE_PI_RESERVED;
> + Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
> + Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
> + Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
> + Type7DataHob->EndingZero = 0;
> + Status = Smbios->Add (Smbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 7\n"));
> + return Status;
> + }
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
> +#if RISCV_SMBIOS_DEBUG_INFO
> + DEBUG ((DEBUG_INFO, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
> + DEBUG ((DEBUG_INFO, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
> + DEBUG ((DEBUG_INFO, " ==============================\n"));
> + DEBUG ((DEBUG_INFO, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
> + DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
> + DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
> + DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
> + DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
> + DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
> + DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
> + DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
> + DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
> + DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
> +#endif
> +
> + *SmbiosHandle = Handle;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function builds SMBIOS type 4 record according to
> + the given RISC_V_PROCESSOR_TYPE4_DATA_HOB.
> +
> + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
> + @param SmbiosHandle Pointer to SMBIOS_HANDLE
> +
> + @retval EFI_STATUS
> +
> +**/
> +static
> +EFI_STATUS
> +BuildSmbiosType4 (
> + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
> + OUT SMBIOS_HANDLE *SmbiosHandle
> + )
> +{
> + EFI_HOB_GUID_TYPE *GuidHob;
The code would be more readable if this was called something like Type7Hob.
> + RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData;
> + SMBIOS_HANDLE Cache;
> + SMBIOS_HANDLE Processor;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 4.\n"));
Again, please avoid the custom [] message tags - add %a __FUNCTION__
where helpul. Throughout.
> + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
> + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
> +
> + Type4DataHob->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
> + Type4DataHob->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
> + Type4DataHob->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
> + GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
> + if (GuidHob == NULL) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS Type7 data HOB found.\n"));
> + return EFI_NOT_FOUND;
> + }
> + //
> + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
> + //
> + do {
> + Type7HobData = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
> + Status = BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
> + Type4DataHob->SmbiosType4Processor.L1CacheHandle = Cache;
> + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
> + Type4DataHob->SmbiosType4Processor.L2CacheHandle = Cache;
> + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
> + Type4DataHob->SmbiosType4Processor.L3CacheHandle = Cache;
> + } else {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Improper cache level of SMBIOS handle %d\n", Cache));
> + }
> + GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
> + } while (GuidHob != NULL);
> +
> + //
> + // Build SMBIOS Type 4 record
> + //
> + Processor = SMBIOS_HANDLE_PI_RESERVED;
> + Type4DataHob->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
> + Type4DataHob->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
> + Type4DataHob->SmbiosType4Processor.Hdr.Handle = 0;
> + Type4DataHob->EndingZero = 0;
> + Status = Smbios->Add (Smbios, NULL, &Processor, &Type4DataHob->SmbiosType4Processor.Hdr);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 4\n"));
> + return Status;
> + }
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
> +#if RISCV_SMBIOS_DEBUG_INFO
> + DEBUG ((DEBUG_INFO, " Socket StringID: %d\n", Type4DataHob->SmbiosType4Processor.Socket));
> + DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorType));
> + DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily));
> + DEBUG ((DEBUG_INFO, " Processor Manufacture StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture));
> + DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n", \
> + Type4DataHob->SmbiosType4Processor.ProcessorId.Signature, Type4DataHob->SmbiosType4Processor.ProcessorId.FeatureFlags));
> + DEBUG ((DEBUG_INFO, " Processor Version StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorVersion));
> + DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4DataHob->SmbiosType4Processor.Voltage));
> + DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n", Type4DataHob->SmbiosType4Processor.ExternalClock));
> + DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.MaxSpeed));
> + DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.CurrentSpeed));
> + DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4DataHob->SmbiosType4Processor.Status));
> + DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorUpgrade));
> + DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L1CacheHandle));
> + DEBUG ((DEBUG_INFO, " L2 Cache Handle: 0x%x\n",Type4DataHob->SmbiosType4Processor.L2CacheHandle));
> + DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L3CacheHandle));
> + DEBUG ((DEBUG_INFO, " Serial Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.SerialNumber));
> + DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n", Type4DataHob->SmbiosType4Processor.AssetTag));
> + DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.PartNumber));
> + DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount));
> + DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount));
> + DEBUG ((DEBUG_INFO, " Thread Count: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount));
> + DEBUG ((DEBUG_INFO, " Processor Characteristics: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics));
> + DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily2));
> + DEBUG ((DEBUG_INFO, " Core Count 2: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount2));
> + DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount2));
> + DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount2));
> +#endif
> +
> + *SmbiosHandle = Processor;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function builds SMBIOS type 44 record according..
> +
> + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
> + @param Type4Handle SMBIOS handle of type 4
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +BuildSmbiosType44 (
> + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
> + IN SMBIOS_HANDLE Type4Handle
> + )
> +{
> + EFI_HOB_GUID_TYPE *GuidHob;
ProcessorSpecificDataHob? Or Type44Hob?
> + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData;
> + SMBIOS_HANDLE RiscVType44;
> + SMBIOS_TABLE_TYPE44 *Type44Ptr;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 44 for...\n"));
> +#if RISCV_SMBIOS_DEBUG_INFO
> + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
> + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
> +#endif
> +
> + GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
> + if (GuidHob == NULL) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC_V_PROCESSOR_SPECIFIC_DATA_HOB found.\n"));
> + return EFI_NOT_FOUND;
> + }
> + //
> + // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for multiple cores.
> + //
> + do {
> + ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
> + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4DataHob->PrcessorGuid) ||
> + ProcessorSpecificData->ParentProcessorUid != Type4DataHob->ProcessorUid) {
> + GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
> + if (GuidHob == NULL) {
> + break;
> + }
> + continue;
> + }
> +
> +#if RISCV_SMBIOS_DEBUG_INFO
> + DEBUG ((DEBUG_INFO, "[ ================================\n"));
> + DEBUG ((DEBUG_INFO, "[ Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
> +#endif
> +
> + Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
> + if (Type44Ptr == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
> + Type44Ptr->Hdr.Handle = 0;
> + Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
> + Type44Ptr->RefHandle = Type4Handle;
> + Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
> + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4DataHob->SmbiosType4Processor.ProcessorFamily2 -
> + ProcessorFamilyRiscvRV32 + \
> + ProcessorSpecificBlockArchTypeRiscVRV32;
> + CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
> +
> +#if RISCV_SMBIOS_DEBUG_INFO
> + DEBUG ((DEBUG_INFO, "[ Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
> + DEBUG ((DEBUG_INFO, " HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
> + DEBUG ((DEBUG_INFO, " Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
> + DEBUG ((DEBUG_INFO, " PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
> + DEBUG ((DEBUG_INFO, " MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
> + DEBUG ((DEBUG_INFO, " MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
> + DEBUG ((DEBUG_INFO, " HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
> + DEBUG ((DEBUG_INFO, " MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
> + DEBUG ((DEBUG_INFO, " SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
> + DEBUG ((DEBUG_INFO, " UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
> + DEBUG ((DEBUG_INFO, " InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
> + DEBUG ((DEBUG_INFO, " MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
> + DEBUG ((DEBUG_INFO, " MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
> + DEBUG ((DEBUG_INFO, " MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
> +#endif
> +
> + //
> + // Add to SMBIOS table.
> + //
> + RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 44\n"));
> + return Status;
> + }
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
> +
> + GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
> + } while (GuidHob != NULL);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Entry point of RISC-V SMBIOS builder.
> +
> + @param ImageHandle Image handle this driver.
> + @param SystemTable Pointer to the System Table.
> +
> + @retval EFI_SUCCESS Thread can be successfully created
> + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> + @retval EFI_DEVICE_ERROR Cannot create the thread
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +RiscVSmbiosBuilderEntry (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HOB_GUID_TYPE *GuidHob;
Type4Hob?
> + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData;
> + SMBIOS_HANDLE Processor;
> +
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a entry\n", __FUNCTION__));
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSmbiosProtocolGuid,
> + NULL,
> + (VOID **)&Smbios
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS Protocol fail\n"));
> + return Status;
> + }
> + GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
> + if (GuidHob == NULL) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS information found.\n"));
> + return EFI_NOT_FOUND;
> + }
> + Type4HobData = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
> + Status = EFI_NOT_FOUND;
> + //
> + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
> + //
> + do {
> + Status = BuildSmbiosType4 (Type4HobData, &Processor);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 4 created.\n"));
> + ASSERT (FALSE);
> + }
> + Status = BuildSmbiosType44 (Type4HobData, Processor);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 44 found.\n"));
> + ASSERT (FALSE);
> + }
> +
> + GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
> + } while (GuidHob != NULL);
> + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a exit\n", __FUNCTION__));
> + return Status;
> +}
> +
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> new file mode 100644
> index 0000000..dfa1fc6
> --- /dev/null
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> @@ -0,0 +1,32 @@
> +/** @file
> + RISC-V SMBIOS Builder DXE module header file.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _RISC_V_SMBIOS_DXE_H_
> +#define _RISC_V_SMBIOS_DXE_H_
> +
> +#include <PiDxe.h>
> +
> +#include <Protocol/Cpu.h>
> +#include <Protocol/Smbios.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/HobLib.h>
> +
> +#include <SmbiosProcessorSpecificData.h>
> +#include <ProcessorSpecificDataHob.h>
Please move all of these include statements to the files that actually
use them, then delete this file.
> +
> +#endif
> +
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> new file mode 100644
> index 0000000..59b814a
> --- /dev/null
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> @@ -0,0 +1,58 @@
> +## @file
> +# RISC-V SMBIOS DXE module.
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVSmbiosDxe
> + MODULE_UNI_FILE = RiscVSmbiosDxe.uni
> + FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = RiscVSmbiosBuilderEntry
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
Please sort alphabetically.
/
Leif
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + CpuLib
> + DebugLib
> + DxeServicesTableLib
> + HobLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Sources]
> + RiscVSmbiosDxe.c
> + RiscVSmbiosDxe.h
> +
> +[Protocols]
> + gEfiSmbiosProtocolGuid # Consumed
> +
> +[Guids]
> +
> +
> +[Pcd]
> +
> +[FixedPcd]
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
> + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
> +
> +[Depex]
> + gEfiSmbiosProtocolGuid
> +
> +[UserExtensions.TianoCore."ExtraFiles"]
> + RiscVSmbiosDxeExtra.uni
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> new file mode 100644
> index 0000000..1bffe09
> --- /dev/null
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> @@ -0,0 +1,12 @@
> +// /** @file
> +//
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor SMBIOS Builder"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Processor SMBIOS Type 4, 7, 44 records."
> +
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> new file mode 100644
> index 0000000..4b37ca2
> --- /dev/null
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +// RISC-V SMBIOS Builder Localized Strings and Content
> +//
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +#string STR_PROPERTIES_MODULE_NAME
> +#language en-US
> +"RISC-V SMBIOS Record Builder DXE Driver"
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
@ 2019-09-30 22:48 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 22:48 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:54AM +0800, Abner Chang wrote:
> Add RiscVEdk2Readme.md
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> RiscVEdk2Readme.md | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 RiscVEdk2Readme.md
>
> diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md
> new file mode 100644
> index 0000000..ec691fe
> --- /dev/null
> +++ b/RiscVEdk2Readme.md
> @@ -0,0 +1,34 @@
> +This branch is used to contribute RISC-V architecture to EDK2
> +
> +The branch owner:<br>
No HTML tags please
> +Abner Chang < abner.chang@hpe.com > <br>
> +Gilbert Chen < gilbert.chen@hpe.com >
> +
> +## RISC-V EDK2 Port Introduction
> +RISC-V is an open ISA which was designed to support research and education of computer architecture, but now it becomes
> +a standard open Instruction Set Architecture for industry implementations. The RISC-V edk2 project is to create a new processor binding in UEFI spec and have the RISC-V edk2 implementation. The goal is to have RISC-V edk2 port as the firmware reference
> +for RISC-V platforms.
Please reflow the document to 80 character line length.
Please also add a link to this document from the top of Readme.md.
> +
> +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V OpenSbi (https://github.com/riscv/opensbi) library integrated. RiscVPkg provides the generic and common modules of RISC-V prcessor. The first edk2 RISC-V platform is SiFive U500 FPGA whcih is maintained in U500Pkg under Platform/RiscV/SiFive in edk2-platform repository.
> +
> +## RISC-V EDK2 Package
> +```
> +RiscVPkg - RISC-V processor package. This package provides RISC-V processor related protocols/libraries accroding
> + to UEFI specification and edk2 implementations.
> +```
> +## Toolchain of RISC-V EDK2 port
> +To build edk2 RISC-V platform requires GCC RISC-V toolchain,
So far so good.
> refer
> to https://github.com/riscv/riscv-gnu-toolchain for the details.
Postponing the full resolution of the issue in order to enable others
to start working this is fine, but this should not be presented as a
normal part of development.
Suggest staing something like:
"Due to not yet tracked down bugs, only the following toolchain is
known to produce bootable binaries."
> The
> commit ID 64879b24 of riscv-gnu-toolchain repository is verified to
> build RISC-V edk2 platform and boot to EFI SHELL successfully.
With which toolchain has it been successfully built? On which Linux
distribution? Or on cygwin? Or both?
/
Leif
> You have to clone the toolchain from above link and check out commit:64879b24 for building RISC-V edk2 port. The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase transition. We are still figuring out the root cause.
> +
> +## EDK2 Build Target
> +"RISCV64" ARCH is the RISC-V architecture which currently supported and verified. The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in tools_def.txt.<br>
> +Below is the edk2 build options for building RISC-V RV64 platform, <br>
> +```
> +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5
> +```
> +For example, <br>
> +```
> +build -a RISCV64 -p Platform/SiFive/U500/U500.dsc -t GCC5
> +```
> +
> +Make sure RISC-V toolchain is built succesfully and the toolchain binaries are generated in somewhere you specified when building toolchain. 'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries. <br>
> +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-' before you build RISC-V edk2 port.
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
@ 2019-09-30 22:50 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 22:50 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:55AM +0800, Abner Chang wrote:
> Add maintainer and reviewer of RiscVPkg.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> Maintainers.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Maintainers.txt b/Maintainers.txt
> index 919bacc..11449a5 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -408,6 +408,11 @@ F: PcAtChipsetPkg/
> W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
> M: Ray Ni <ray.ni@intel.com>
>
> +RiscVPkg: RISCV64 architecture modules
> +F: RISCV64/
F: */RiscV64/
Also, you need an entry for RiscVPkg.
Verify for yourselves that python BaseTools/Scripts/GetMaintainer.py
produces expected results before submitting v3.
/
Leif
> +M: Abner Chang <abner.chang@hpe.com>
> +R: Gilbert Chen <gilbert.chen@hpe.com>
> +
> SecurityPkg
> F: SecurityPkg/
> W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
@ 2019-09-30 22:51 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 22:51 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:40AM +0800, Abner Chang wrote:
> Add RISCV64 Arch.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> NetworkPkg/Network.dsc.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
> index c7f4328..b484f9b 100644
> --- a/NetworkPkg/Network.dsc.inc
> +++ b/NetworkPkg/Network.dsc.inc
> @@ -34,7 +34,7 @@
> !include NetworkPkg/NetworkComponents.dsc.inc
>
> !else
> -[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
> +[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64]
> !include NetworkPkg/NetworkComponents.dsc.inc
>
> !endif
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
@ 2019-09-30 22:51 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-09-30 22:51 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Sep 23, 2019 at 08:31:39AM +0800, Abner Chang wrote:
> Add RISCV64 Arch.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> MdeModulePkg/Logo/Logo.inf | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
> index 0182025..243748c 100644
> --- a/MdeModulePkg/Logo/Logo.inf
> +++ b/MdeModulePkg/Logo/Logo.inf
> @@ -19,7 +19,7 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Binaries]
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
@ 2019-10-01 8:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 108+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-01 8:44 UTC (permalink / raw)
To: devel, abner.chang
On 9/23/19 2:31 AM, Abner Chang wrote:
> Implement RISC-V cache maintenance functions in
> BaseCacheMaintenanceLib.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../BaseCacheMaintenanceLib.inf | 4 +
> .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++
> 2 files changed, 254 insertions(+)
> create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> index ec7feec..d9bfa04 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> @@ -6,6 +6,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -41,6 +42,9 @@
> [Sources.AARCH64]
> ArmCache.c
>
> +[Sources.RISCV64]
> + RiscVCache.c
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> new file mode 100644
> index 0000000..d8e4665
> --- /dev/null
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -0,0 +1,250 @@
> +/** @file
> + RISC-V specific functionality for cache.
> +
> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + RISC-V invalidate instruction cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateInstCacheAsm (
> + VOID
> + );
> +
> +/**
> + RISC-V invalidate data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateDataCacheAsm (
> + VOID
> + );
> +
> +/**
> + Invalidates the entire instruction cache in cache coherency domain of the
> + calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateInstructionCache (
> + VOID
> + )
> +{
> + RiscVInvalidateInstCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of instruction cache lines in the cache coherency domain
> + of the calling CPU.
> +
> + Invalidates the instruction cache lines specified by Address and Length. If
> + Address is not aligned on a cache line boundary, then entire instruction
> + cache line containing Address is invalidated. If Address + Length is not
> + aligned on a cache line boundary, then the entire instruction cache line
> + containing Address + Length -1 is invalidated. This function may choose to
> + invalidate the entire instruction cache if that is more efficient than
> + invalidating the specified range. If Length is 0, then no instruction cache
> + lines are invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the instruction cache lines to
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> +
> + @param Length The number of bytes to invalidate from the instruction cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateInstructionCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
> + return Address;
> +}
> +
> +/**
> + Writes back and invalidates the entire data cache in cache coherency domain
> + of the calling CPU.
> +
> + Writes back and invalidates the entire data cache in cache coherency domain
> + of the calling CPU. This function guarantees that all dirty cache lines are
> + written back to system memory, and also invalidates all the data cache lines
> + in the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackInvalidateDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
> +}
> +
> +/**
> + Writes back and invalidates a range of data cache lines in the cache
> + coherency domain of the calling CPU.
> +
> + Writes back and invalidates the data cache lines specified by Address and
> + Length. If Address is not aligned on a cache line boundary, then entire data
> + cache line containing Address is written back and invalidated. If Address +
> + Length is not aligned on a cache line boundary, then the entire data cache
> + line containing Address + Length -1 is written back and invalidated. This
> + function may choose to write back and invalidate the entire data cache if
> + that is more efficient than writing back and invalidating the specified
> + range. If Length is 0, then no data cache lines are written back and
> + invalidated. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back and
> + invalidate. If the CPU is in a physical addressing mode, then
> + Address is a physical address. If the CPU is in a virtual
> + addressing mode, then Address is a virtual address.
> + @param Length The number of bytes to write back and invalidate from the
> + data cache.
> +
> + @return Address of cache invalidation.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackInvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
typo unsupportted -> unsupported
> + return Address;
> +}
> +
> +/**
> + Writes back the entire data cache in cache coherency domain of the calling
> + CPU.
> +
> + Writes back the entire data cache in cache coherency domain of the calling
> + CPU. This function guarantees that all dirty cache lines are written back to
> + system memory. This function may also invalidate all the data cache lines in
> + the cache coherency domain of the calling CPU.
> +
> +**/
> +VOID
> +EFIAPI
> +WriteBackDataCache (
> + VOID
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
Ditto,
> +}
> +
> +/**
> + Writes back a range of data cache lines in the cache coherency domain of the
> + calling CPU.
> +
> + Writes back the data cache lines specified by Address and Length. If Address
> + is not aligned on a cache line boundary, then entire data cache line
> + containing Address is written back. If Address + Length is not aligned on a
> + cache line boundary, then the entire data cache line containing Address +
> + Length -1 is written back. This function may choose to write back the entire
> + data cache if that is more efficient than writing back the specified range.
> + If Length is 0, then no data cache lines are written back. This function may
> + also invalidate all the data cache lines in the specified range of the cache
> + coherency domain of the calling CPU. Address is returned.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to write back. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing
> + mode, then Address is a virtual address.
> + @param Length The number of bytes to write back from the data cache.
> +
> + @return Address of cache written in main memory.
> +
> +**/
> +VOID *
> +EFIAPI
> +WriteBackDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
Ditto,
> + return Address;
> +}
> +
> +/**
> + Invalidates the entire data cache in cache coherency domain of the calling
> + CPU.
> +
> + Invalidates the entire data cache in cache coherency domain of the calling
> + CPU. This function must be used with care because dirty cache lines are not
> + written back to system memory. It is typically used for cache diagnostics. If
> + the CPU does not support invalidation of the entire data cache, then a write
> + back and invalidate operation should be performed on the entire data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +InvalidateDataCache (
> + VOID
> + )
> +{
> + RiscVInvalidateDataCacheAsm ();
> +}
> +
> +/**
> + Invalidates a range of data cache lines in the cache coherency domain of the
> + calling CPU.
> +
> + Invalidates the data cache lines specified by Address and Length. If Address
> + is not aligned on a cache line boundary, then entire data cache line
> + containing Address is invalidated. If Address + Length is not aligned on a
> + cache line boundary, then the entire data cache line containing Address +
> + Length -1 is invalidated. This function must never invalidate any cache lines
> + outside the specified range. If Length is 0, then no data cache lines are
> + invalidated. Address is returned. This function must be used with care
> + because dirty cache lines are not written back to system memory. It is
> + typically used for cache diagnostics. If the CPU does not support
> + invalidation of a data cache range, then a write back and invalidate
> + operation should be performed on the data cache range.
> +
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> +
> + @param Address The base address of the data cache lines to invalidate. If
> + the CPU is in a physical addressing mode, then Address is a
> + physical address. If the CPU is in a virtual addressing mode,
> + then Address is a virtual address.
> + @param Length The number of bytes to invalidate from the data cache.
> +
> + @return Address.
> +
> +**/
> +VOID *
> +EFIAPI
> +InvalidateDataCacheRange (
> + IN VOID *Address,
> + IN UINTN Length
> + )
> +{
> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
Ditto.
> + return Address;
> +}
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-09-26 23:39 ` [edk2-devel] " Leif Lindholm
@ 2019-10-01 8:49 ` Philippe Mathieu-Daudé
2019-10-01 9:07 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-01 8:49 UTC (permalink / raw)
To: devel, leif.lindholm, abner.chang
Hi Leif,
On 9/27/19 1:39 AM, Leif Lindholm wrote:
> On Mon, Sep 23, 2019 at 08:31:35AM +0800, Abner Chang wrote:
>> RISC-V MMIO library instance. RISC-V only supports memory map I/O.
>
> We need fewer, not more, C implementations of MMIO accessors.
> While this set doesn't need to wait for upstream to get sorted, please
> just use IoLibArm.c which should be completely equivalent to what you
> have implemented here.
This shows this file name is misleading. However I can't come with a
clever one :/
>> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>> ---
>> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
>> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
>> 2 files changed, 607 insertions(+), 2 deletions(-)
>> create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>> index 457cce9..fbb568e 100644
>> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>> @@ -2,13 +2,14 @@
>> # Instance of I/O Library using compiler intrinsics.
>> #
>> # I/O Library that uses compiler intrinsics to perform IN and OUT instructions
>> -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
>> +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated into MMIO requests.
>> # MMIO requests are forwarded directly to memory. For EBC, I/O port requests
>> # ASSERT().
>> #
>> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
>> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>> +# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>> #
>> # SPDX-License-Identifier: BSD-2-Clause-Patent
>> #
>> @@ -25,7 +26,7 @@
>>
>>
>> #
>> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
>> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
>> #
>>
>> [Sources]
>> @@ -55,6 +56,9 @@
>> [Sources.AARCH64]
>> IoLibArm.c
>>
>> +[Sources.RISCV64]
>> + IoLibRiscV.c
>> +
>> [Packages]
>> MdePkg/MdePkg.dec
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>> new file mode 100644
>> index 0000000..789928b
>> --- /dev/null
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>> @@ -0,0 +1,601 @@
>> +/** @file
>> + Common I/O Library routines for RISC-V
>> +
>> + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +**/
>> +
>> +#include "BaseIoLibIntrinsicInternal.h"
>> +
>> +/**
>> + Reads an 8-bit MMIO register.
>> +
>> + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
>> + returned. This function must guarantee that all MMIO read and write
>> + operations are serialized.
>> +
>> + If 8-bit MMIO register operations are not supported, then ASSERT().
>> +
>> + @param Address The MMIO register to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +MmioRead8 (
>> + IN UINTN Address
>> + )
>> +{
>> + return *(volatile UINT8*)Address;
>> +}
>> +
>> +/**
>> + Writes an 8-bit MMIO register.
>> +
>> + Writes the 8-bit MMIO register specified by Address with the value specified
>> + by Value and returns Value. This function must guarantee that all MMIO read
>> + and write operations are serialized.
>> +
>> + If 8-bit MMIO register operations are not supported, then ASSERT().
>> +
>> + @param Address The MMIO register to write.
>> + @param Value The value to write to the MMIO register.
>> +
>> + @return Value.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +MmioWrite8 (
>> + IN UINTN Address,
>> + IN UINT8 Value
>> + )
>> +{
>> + *(volatile UINT8 *)Address = Value;
>> + return Value;
>> +}
>> +
>> +/**
>> + Reads a 16-bit MMIO register.
>> +
>> + Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
>> + returned. This function must guarantee that all MMIO read and write
>> + operations are serialized.
>> +
>> + If 16-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +MmioRead16 (
>> + IN UINTN Address
>> + )
>> +{
>> + return *(volatile UINT16 *)Address;
>> +}
>> +
>> +/**
>> + Writes a 16-bit MMIO register.
>> +
>> + Writes the 16-bit MMIO register specified by Address with the value specified
>> + by Value and returns Value. This function must guarantee that all MMIO read
>> + and write operations are serialized.
>> +
>> + If 16-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to write.
>> + @param Value The value to write to the MMIO register.
>> +
>> + @return Value.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +MmioWrite16 (
>> + IN UINTN Address,
>> + IN UINT16 Value
>> + )
>> +{
>> + *(volatile UINT16 *)Address = Value;
>> + return Value;
>> +}
>> +
>> +/**
>> + Reads a 32-bit MMIO register.
>> +
>> + Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
>> + returned. This function must guarantee that all MMIO read and write
>> + operations are serialized.
>> +
>> + If 32-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +MmioRead32 (
>> + IN UINTN Address
>> + )
>> +{
>> + return *(volatile UINT32 *)Address;
>> +}
>> +
>> +/**
>> + Writes a 32-bit MMIO register.
>> +
>> + Writes the 32-bit MMIO register specified by Address with the value specified
>> + by Value and returns Value. This function must guarantee that all MMIO read
>> + and write operations are serialized.
>> +
>> + If 32-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to write.
>> + @param Value The valu return *(volatile UINT8*)Address;
>> + to write to the MMIO register.
>> +
>> + @return Value.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +MmioWrite32 (
>> + IN UINTN Address,
>> + IN UINT32 Value
>> + )
>> +{
>> + *(volatile UINT32 *)Address = Value;
>> + return Value;
>> +}
>> +
>> +/**
>> + Reads a 64-bit MMIO register.
>> +
>> + Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
>> + returned. This function must guarantee that all MMIO read and write
>> + operations are serialized.
>> +
>> + If 64-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 64-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT64
>> +EFIAPI
>> +MmioRead64 (
>> + IN UINTN Address
>> + )
>> +{
>> + return *(volatile UINT64 *)Address;
>> +}
>> +
>> +/**
>> + Writes a 64-bit MMIO register.
>> +
>> + Writes the 64-bit MMIO register specified by Address with the value specified
>> + by Value and returns Value. This function must guarantee that all MMIO read
>> + and write operations are serialized.
>> +
>> + If 64-bit MMIO register operations are not supported, then ASSERT().
>> + If Address is not aligned on a 64-bit boundary, then ASSERT().
>> +
>> + @param Address The MMIO register to write.
>> + @param Value The value to write to the MMIO register.
>> +
>> +**/
>> +UINT64
>> +EFIAPI
>> +MmioWrite64 (
>> + IN UINTN Address,
>> + IN UINT64 Value
>> + )
>> +{
>> + *(volatile UINT64 *)Address = Value;
>> + return Value;
>> +}
>> +
>> +/**
>> + Reads an 8-bit I/O port.
>> +
>> + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 8-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +IoRead8 (
>> + IN UINTN Port
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Writes an 8-bit I/O port.
>> +
>> + Writes the 8-bit I/O port specified by Port with the value specified by Value
>> + and returns Value. This function must guarantee that all I/O read and write
>> + operations are serialized.
>> +
>> + If 8-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Value The value to write to the I/O port.
>> +
>> + @return The value written the I/O port.
>> +
>> +**/
>> +
>> +UINT8
>> +EFIAPI
>> +IoWrite8 (
>> + IN UINTN Port,
>> + IN UINT8 Value
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Reads a 16-bit I/O port.
>> +
>> + Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 16-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +IoRead16 (
>> + IN UINTN Port
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Writes a 16-bit I/O port.
>> +
>> + Writes the 16-bit I/O port specified by Port with the value specified by Value
>> + and returns Value. This function must guarantee that all I/O read and write
>> + operations are serialized.
>> +
>> + If 16-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Value The value to write to the I/O port.
>> +
>> + @return The value written the I/O port.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +IoWrite16 (
>> + IN UINTN Port,
>> + IN UINT16 Value
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Reads a 32-bit I/O port.
>> +
>> + Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 32-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +IoRead32 (
>> + IN UINTN Port
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Writes a 32-bit I/O port.
>> +
>> + Writes the 32-bit I/O port specified by Port with the value specified by Value
>> + and returns Value. This function must guarantee that all I/O read and write
>> + operations are serialized.
>> +
>> + If 32-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Value The value to write to the I/O port.
>> +
>> + @return The value written the I/O port.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +IoWrite32 (
>> + IN UINTN Port,
>> + IN UINT32 Value
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Reads a 64-bit I/O port.
>> +
>> + Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 64-bit I/O port operations are not supported, then ASSERT().
>> + If Port is not aligned on a 64-bit boundary, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> +
>> + @return The value read.
>> +
>> +**/
>> +UINT64
>> +EFIAPI
>> +IoRead64 (
>> + IN UINTN Port
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Writes a 64-bit I/O port.
>> +
>> + Writes the 64-bit I/O port specified by Port with the value specified by Value
>> + and returns Value. This function must guarantee that all I/O read and write
>> + operations are serialized.
>> +
>> + If 64-bit I/O port operations are not supported, then ASSERT().
>> + If Port is not aligned on a 64-bit boundary, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Value The value to write to the I/O port.
>> +
>> + @return The value written to the I/O port.
>> +
>> +**/
>> +UINT64
>> +EFIAPI
>> +IoWrite64 (
>> + IN UINTN Port,
>> + IN UINT64 Value
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> + return 0;
>> +}
>> +
>> +/**
>> + Reads an 8-bit I/O port fifo into a block of memory.
>> +
>> + Reads the 8-bit I/O fifo port specified by Port.
>> + The port is read Count times, and the read data is
>> + stored in the provided Buffer.
>> +
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 8-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> + @param Count The number of times to read I/O port.
>> + @param Buffer The buffer to store the read data into.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoReadFifo8 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> +
>> +/**
>> + Writes a block of memory into an 8-bit I/O port fifo.
>> +
>> + Writes the 8-bit I/O fifo port specified by Port.
>> + The port is written Count times, and the write data is
>> + retrieved from the provided Buffer.
>> +
>> + This function must guarantee that all I/O write and write operations are
>> + serialized.
>> +
>> + If 8-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Count The number of times to write I/O port.
>> + @param Buffer The buffer to retrieve the write data from.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoWriteFifo8 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> +
>> +/**
>> + Reads a 16-bit I/O port fifo into a block of memory.
>> +
>> + Reads the 16-bit I/O fifo port specified by Port.
>> + The port is read Count times, and the read data is
>> + stored in the provided Buffer.
>> +
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 16-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> + @param Count The number of times to read I/O port.
>> + @param Buffer The buffer to store the read data into.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoReadFifo16 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> +
>> +/**
>> + Writes a block of memory into a 16-bit I/O port fifo.
>> +
>> + Writes the 16-bit I/O fifo port specified by Port.
>> + The port is written Count times, and the write data is
>> + retrieved from the provided Buffer.
>> +
>> + This function must guarantee that all I/O write and write operations are
>> + serialized.
>> +
>> + If 16-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Count The number of times to write I/O port.
>> + @param Buffer The buffer to retrieve the write data from.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoWriteFifo16 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> +
>> +/**
>> + Reads a 32-bit I/O port fifo into a block of memory.
>> +
>> + Reads the 32-bit I/O fifo port specified by Port.
>> + The port is read Count times, and the read data is
>> + stored in the provided Buffer.
>> +
>> + This function must guarantee that all I/O read and write operations are
>> + serialized.
>> +
>> + If 32-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to read.
>> + @param Count The number of times to read I/O port.
>> + @param Buffer The buffer to store the read data into.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoReadFifo32 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> +
>> +/**
>> + Writes a block of memory into a 32-bit I/O port fifo.
>> +
>> + Writes the 32-bit I/O fifo port specified by Port.
>> + The port is written Count times, and the write data is
>> + retrieved from the provided Buffer.
>> +
>> + This function must guarantee that all I/O write and write operations are
>> + serialized.
>> +
>> + If 32-bit I/O port operations are not supported, then ASSERT().
>> +
>> + @param Port The I/O port to write.
>> + @param Count The number of times to write I/O port.
>> + @param Buffer The buffer to retrieve the write data from.
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +IoWriteFifo32 (
>> + IN UINTN Port,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__));
>> + ASSERT (FALSE);
>> +}
>> --
>> 2.7.4
>>
>>
>>
>>
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-01 8:49 ` Philippe Mathieu-Daudé
@ 2019-10-01 9:07 ` Leif Lindholm
2019-10-02 1:30 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-01 9:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: devel, abner.chang
On Tue, Oct 01, 2019 at 10:49:38AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Leif,
>
> On 9/27/19 1:39 AM, Leif Lindholm wrote:
> > On Mon, Sep 23, 2019 at 08:31:35AM +0800, Abner Chang wrote:
> > > RISC-V MMIO library instance. RISC-V only supports memory map I/O.
> >
> > We need fewer, not more, C implementations of MMIO accessors.
> > While this set doesn't need to wait for upstream to get sorted, please
> > just use IoLibArm.c which should be completely equivalent to what you
> > have implemented here.
>
> This shows this file name is misleading. However I can't come with a clever
> one :/
This has been discussed before, only the current situation "works", so
sorting it out never takes priority (I know it doesn't for me).
There should be exactly one variant of IoLib.c. Well, these days we
need a separate one for ARM/AARCH64 under hw virtualization.
IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same
requirements. And now x86 uses NASM regardless of build platform, I
think it would make sense to move the contents of IoLibGcc and
IoLibMsc into assembler.
/
Leif
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> > > MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++++++
> > > 2 files changed, 607 insertions(+), 2 deletions(-)
> > > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-01 9:07 ` Leif Lindholm
@ 2019-10-02 1:30 ` Abner Chang
2019-10-02 9:13 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-02 1:30 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org,
Philippe Mathieu-Daudé
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Tuesday, October 1, 2019 5:07 PM
> To: Philippe Mathieu-Daudé <philmd@redhat.com>
> Cc: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>
> On Tue, Oct 01, 2019 at 10:49:38AM +0200, Philippe Mathieu-Daudé wrote:
> > Hi Leif,
> >
> > On 9/27/19 1:39 AM, Leif Lindholm wrote:
> > > On Mon, Sep 23, 2019 at 08:31:35AM +0800, Abner Chang wrote:
> > > > RISC-V MMIO library instance. RISC-V only supports memory map I/O.
> > >
> > > We need fewer, not more, C implementations of MMIO accessors.
> > > While this set doesn't need to wait for upstream to get sorted,
> > > please just use IoLibArm.c which should be completely equivalent to
> > > what you have implemented here.
> >
> > This shows this file name is misleading. However I can't come with a
> > clever one :/
>
> This has been discussed before, only the current situation "works", so sorting
> it out never takes priority (I know it doesn't for me).
>
> There should be exactly one variant of IoLib.c. Well, these days we need a
> separate one for ARM/AARCH64 under hw virtualization.
>
> IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same requirements.
> And now x86 uses NASM regardless of build platform, I think it would make
> sense to move the contents of IoLibGcc and IoLibMsc into assembler.
That looks weird and doesn't make sense to use Arm code for RISC-V even the functionality is exactly the same to IoLibRiscV. I will still keep it as IoLibRiscV.c until there is a generic IoLib for different arch.
.
>
> /
> Leif
>
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> > > > MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601
> +++++++++++++++++++++
> > > > 2 files changed, 607 insertions(+), 2 deletions(-)
> > > > create mode 100644
> > > > MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-02 1:30 ` Abner Chang
@ 2019-10-02 9:13 ` Leif Lindholm
2019-10-02 16:14 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-02 9:13 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist)
Cc: devel@edk2.groups.io, Philippe Mathieu-Daudé
On Wed, Oct 02, 2019 at 01:30:12AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > There should be exactly one variant of IoLib.c. Well, these days we need a
> > separate one for ARM/AARCH64 under hw virtualization.
> >
> > IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same requirements.
> > And now x86 uses NASM regardless of build platform, I think it would make
> > sense to move the contents of IoLibGcc and IoLibMsc into assembler.
>
> That looks weird and doesn't make sense to use Arm code for RISC-V
> even the functionality is exactly the same to IoLibRiscV. I will
> still keep it as IoLibRiscV.c until there is a generic IoLib for
> different arch.
This is C code. It is no more weird to use "another architecture's"
code than it is to add another file doing exactly the same thing but
pretending it is "for" another architecture.
And one of those options does not pile up even more code duplication
in the tree.
But you are welcome to convince some other maintainer of the opposite.
/
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-02 9:13 ` Leif Lindholm
@ 2019-10-02 16:14 ` Abner Chang
2019-10-02 16:27 ` Andrew Fish
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-02 16:14 UTC (permalink / raw)
To: Leif Lindholm
Cc: devel@edk2.groups.io, Philippe Mathieu-Daudé,
Michael D Kinney, Liming Gao
Thanks Leif, let me check with maintainers.
Hi Mike and Liming,
How do you think about to use IoLibArm as the I/O lib instance for RISC-V arch? I personally don't like to use IoLibArm.c in [Source.RISCV64] section, instead I would like to use IoLibRiscV.c which conform with current source file organization under BaseIoLibIntrinsics. What's your preference?
Thanks
Abner
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Wednesday, October 2, 2019 5:13 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Philippe Mathieu-Daudé <philmd@redhat.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>
> On Wed, Oct 02, 2019 at 01:30:12AM +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> > > There should be exactly one variant of IoLib.c. Well, these days we
> > > need a separate one for ARM/AARCH64 under hw virtualization.
> > >
> > > IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same requirements.
> > > And now x86 uses NASM regardless of build platform, I think it would
> > > make sense to move the contents of IoLibGcc and IoLibMsc into
> assembler.
> >
> > That looks weird and doesn't make sense to use Arm code for RISC-V
> > even the functionality is exactly the same to IoLibRiscV. I will still
> > keep it as IoLibRiscV.c until there is a generic IoLib for different
> > arch.
>
> This is C code. It is no more weird to use "another architecture's"
> code than it is to add another file doing exactly the same thing but
> pretending it is "for" another architecture.
>
> And one of those options does not pile up even more code duplication in the
> tree.
>
> But you are welcome to convince some other maintainer of the opposite.
>
> /
> Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-02 16:14 ` Abner Chang
@ 2019-10-02 16:27 ` Andrew Fish
2019-10-02 16:35 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Fish @ 2019-10-02 16:27 UTC (permalink / raw)
To: devel, abner.chang
Cc: Leif Lindholm, Philippe Mathieu-Daudé, Mike Kinney,
Liming Gao
[-- Attachment #1: Type: text/plain, Size: 2653 bytes --]
> On Oct 2, 2019, at 11:14 AM, Abner Chang <abner.chang@hpe.com> wrote:
>
> Thanks Leif, let me check with maintainers.
>
> Hi Mike and Liming,
> How do you think about to use IoLibArm as the I/O lib instance for RISC-V arch? I personally don't like to use IoLibArm.c in [Source.RISCV64] section, instead I would like to use IoLibRiscV.c which conform with current source file organization under BaseIoLibIntrinsics. What's your preference?
>
Abner,
So is the plan to just copy IoLibArm.c to IoLibRiskV.c? I kind of agree with Leif that having two copies of the same thing does not make sense. I do see your point about naming, but maybe the issue the IoLibArm.c name. I don't see anything ARM specific in IoLibArm.c it seems to me it is generic C code for a platform that does not have IO Ports. So I guess we could just change the file name of IoLibArm.c to IoLibNoIo.c and have ARM and RISC-V point at the common file?
Thanks,
Andrew Fish
> Thanks
> Abner
>
>> -----Original Message-----
>> From: Leif Lindholm [mailto:leif.lindholm@linaro.org <mailto:leif.lindholm@linaro.org>]
>> Sent: Wednesday, October 2, 2019 5:13 PM
>> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com <mailto:abner.chang@hpe.com>>
>> Cc: devel@edk2.groups.io <mailto:devel@edk2.groups.io>; Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>>
>> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
>> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>>
>> On Wed, Oct 02, 2019 at 01:30:12AM +0000, Chang, Abner (HPS SW/FW
>> Technologist) wrote:
>>>> There should be exactly one variant of IoLib.c. Well, these days we
>>>> need a separate one for ARM/AARCH64 under hw virtualization.
>>>>
>>>> IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same requirements.
>>>> And now x86 uses NASM regardless of build platform, I think it would
>>>> make sense to move the contents of IoLibGcc and IoLibMsc into
>> assembler.
>>>
>>> That looks weird and doesn't make sense to use Arm code for RISC-V
>>> even the functionality is exactly the same to IoLibRiscV. I will still
>>> keep it as IoLibRiscV.c until there is a generic IoLib for different
>>> arch.
>>
>> This is C code. It is no more weird to use "another architecture's"
>> code than it is to add another file doing exactly the same thing but
>> pretending it is "for" another architecture.
>>
>> And one of those options does not pile up even more code duplication in the
>> tree.
>>
>> But you are welcome to convince some other maintainer of the opposite.
>>
>> /
>> Leif
>
>
[-- Attachment #2: Type: text/html, Size: 9519 bytes --]
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-02 16:27 ` Andrew Fish
@ 2019-10-02 16:35 ` Leif Lindholm
2019-10-03 0:52 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-02 16:35 UTC (permalink / raw)
To: devel, afish
Cc: abner.chang, Philippe Mathieu-Daudé, Mike Kinney, Liming Gao
On Wed, Oct 02, 2019 at 11:27:16AM -0500, Andrew Fish via Groups.Io wrote:
>
>
> > On Oct 2, 2019, at 11:14 AM, Abner Chang <abner.chang@hpe.com> wrote:
> >
> > Thanks Leif, let me check with maintainers.
> >
> > Hi Mike and Liming,
> > How do you think about to use IoLibArm as the I/O lib instance for RISC-V arch? I personally don't like to use IoLibArm.c in [Source.RISCV64] section, instead I would like to use IoLibRiscV.c which conform with current source file organization under BaseIoLibIntrinsics. What's your preference?
> >
>
> Abner,
>
> So is the plan to just copy IoLibArm.c to IoLibRiskV.c? I kind of
> agree with Leif that having two copies of the same thing does not
> make sense. I do see your point about naming, but maybe the issue
> the IoLibArm.c name. I don't see anything ARM specific in
> IoLibArm.c it seems to me it is generic C code for a platform that
> does not have IO Ports. So I guess we could just change the file
> name of IoLibArm.c to IoLibNoIo.c and have ARM and RISC-V point at
> the common file?
Works for me.
We can untangle the remaining mess unrelated from the Risc-V upstreaming.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-02 16:35 ` Leif Lindholm
@ 2019-10-03 0:52 ` Abner Chang
2019-10-03 8:38 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-03 0:52 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org, afish@apple.com
Cc: Philippe Mathieu-Daudé, Mike Kinney, Liming Gao
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Thursday, October 3, 2019 12:35 AM
> To: devel@edk2.groups.io; afish@apple.com
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
> Philippe Mathieu-Daudé <philmd@redhat.com>; Mike Kinney
> <michael.d.kinney@intel.com>; Liming Gao <liming.gao@intel.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>
> On Wed, Oct 02, 2019 at 11:27:16AM -0500, Andrew Fish via Groups.Io wrote:
> >
> >
> > > On Oct 2, 2019, at 11:14 AM, Abner Chang <abner.chang@hpe.com>
> wrote:
> > >
> > > Thanks Leif, let me check with maintainers.
> > >
> > > Hi Mike and Liming,
> > > How do you think about to use IoLibArm as the I/O lib instance for RISC-V
> arch? I personally don't like to use IoLibArm.c in [Source.RISCV64] section,
> instead I would like to use IoLibRiscV.c which conform with current source file
> organization under BaseIoLibIntrinsics. What's your preference?
> > >
> >
> > Abner,
> >
> > So is the plan to just copy IoLibArm.c to IoLibRiskV.c? I kind of
> > agree with Leif that having two copies of the same thing does not make
> > sense. I do see your point about naming, but maybe the issue the
> > IoLibArm.c name. I don't see anything ARM specific in IoLibArm.c it
> > seems to me it is generic C code for a platform that does not have IO
> > Ports. So I guess we could just change the file name of IoLibArm.c to
> > IoLibNoIo.c and have ARM and RISC-V point at the common file?
Yes, naming is my concern. No technical issues here.
Thanks for this suggestion.
>
> Works for me.
> We can untangle the remaining mess unrelated from the Risc-V upstreaming.
Leif, I will rename IoLibRiscV.c to IoLibNoIo.c in the next version of patches. You can adopt the new file in ARM side later.
Thanks
Abner
>
> Best Regards,
>
> Leif
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-03 0:52 ` Abner Chang
@ 2019-10-03 8:38 ` Leif Lindholm
2019-10-03 11:34 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-03 8:38 UTC (permalink / raw)
To: devel, abner.chang
Cc: afish@apple.com, Philippe Mathieu-Daudé, Mike Kinney,
Liming Gao, Palmer Dabbelt
On Thu, Oct 03, 2019 at 12:52:57AM +0000, Abner Chang wrote:
> > > So is the plan to just copy IoLibArm.c to IoLibRiskV.c? I kind of
> > > agree with Leif that having two copies of the same thing does not make
> > > sense. I do see your point about naming, but maybe the issue the
> > > IoLibArm.c name. I don't see anything ARM specific in IoLibArm.c it
> > > seems to me it is generic C code for a platform that does not have IO
> > > Ports. So I guess we could just change the file name of IoLibArm.c to
> > > IoLibNoIo.c and have ARM and RISC-V point at the common file?
>
> Yes, naming is my concern. No technical issues here.
> Thanks for this suggestion.
>
> > Works for me.
> > We can untangle the remaining mess unrelated from the Risc-V upstreaming.
>
> Leif, I will rename IoLibRiscV.c to IoLibNoIo.c in the next version
> of patches. You can adopt the new file in ARM side later.
The suggestion was to rename IoLibArm.c. If you're insisting on
keeping your duplicated version, you're back to looking for another
maintainer to convince that this is the better solution.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-03 8:38 ` Leif Lindholm
@ 2019-10-03 11:34 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-03 11:34 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
Cc: afish@apple.com, Philippe Mathieu-Daudé, Mike Kinney,
Liming Gao, Palmer Dabbelt
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Thursday, October 3, 2019 4:38 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: afish@apple.com; Philippe Mathieu-Daudé <philmd@redhat.com>; Mike
> Kinney <michael.d.kinney@intel.com>; Liming Gao <liming.gao@intel.com>;
> Palmer Dabbelt <palmer@sifive.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
>
> On Thu, Oct 03, 2019 at 12:52:57AM +0000, Abner Chang wrote:
> > > > So is the plan to just copy IoLibArm.c to IoLibRiskV.c? I kind of
> > > > agree with Leif that having two copies of the same thing does not
> > > > make sense. I do see your point about naming, but maybe the issue
> > > > the IoLibArm.c name. I don't see anything ARM specific in
> > > > IoLibArm.c it seems to me it is generic C code for a platform that
> > > > does not have IO Ports. So I guess we could just change the file
> > > > name of IoLibArm.c to IoLibNoIo.c and have ARM and RISC-V point at
> the common file?
> >
> > Yes, naming is my concern. No technical issues here.
> > Thanks for this suggestion.
> >
> > > Works for me.
> > > We can untangle the remaining mess unrelated from the Risc-V
> upstreaming.
> >
> > Leif, I will rename IoLibRiscV.c to IoLibNoIo.c in the next version of
> > patches. You can adopt the new file in ARM side later.
>
> The suggestion was to rename IoLibArm.c. If you're insisting on keeping your
> duplicated version, you're back to looking for another maintainer to convince
> that this is the better solution.
Ah, yes. Rename IoLibArm.c to IoLibNoIo.h. I am good with this.
>
> Best Regards,
>
> Leif
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2019-09-30 22:39 ` [edk2-devel] " Leif Lindholm
@ 2019-10-14 11:27 ` Abner Chang
2019-10-14 11:56 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-14 11:27 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, October 1, 2019 6:40 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29]
> RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
>
> On Mon, Sep 23, 2019 at 08:31:52AM +0800, Abner Chang wrote:
> > RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
> > and type 44 records.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++++
> > RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++++
> > RiscVPkg/RiscVPkg.dec | 6 +
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339
> +++++++++++++++++++++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
> > .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
> > 8 files changed, 613 insertions(+)
> > create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
> > create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > create mode 100644
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> >
> > diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h
> > b/RiscVPkg/Include/ProcessorSpecificDataHob.h
> > new file mode 100644
> > index 0000000..6798a9d
> > --- /dev/null
> > +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h
>
> None of the things defined in here are HOBs, they are structures to hold
> information that will be put into HOBs.
> Can we merge all of these definitions into SmbiosProcessorSpecificData.h
> and delete this file?
No. SmbiosProcessorSpecificData.h defines the structure declared in RISC-V SMBIOS processor specific data spec (https://github.com/riscv/riscv-smbios).
ProcessorSpecificDataHob is the implementation to deliver processor information in HOB for building SMBIOS type 44 record.
I would like to keep these two files separately.
>
> > @@ -0,0 +1,95 @@
> > +/** @file
> > + Definition of Processor Specific Data HOB.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
> > +#define _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
>
> Please drop leading _.
>
> > +
> > +#include <IndustryStandard/SmBios.h>
>
> This file also uses Uefi.h, please include it, so we don't depend on other files
> pulling it in for us.
>
> > +
> > +#define TO_BE_FILLED 0
> > +#define TO_BE_FILLED_BY_VENDOR 0
> > +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 #define
> > +TO_BE_FILLED_BY_CODE 0
>
> These defines are never used, please drop,
These definitions are used in platform code to indicates the value is not set correctly and should be set by certain code.
>
> > +
> > +#pragma pack(1)
> > +
> > +///
> > +/// RISC-V processor specific data HOB /// typedef struct {
> > + EFI_GUID ParentPrcessorGuid;
> > + UINTN ParentProcessorUid;
> > + EFI_GUID CoreGuid;
> > + VOID *Context; // The additional information of this core which
> > + // built in PEI phase and carried to DXE phase.
> > + // The content is pocessor or platform specific.
> > + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; }
> > +RISC_V_PROCESSOR_SPECIFIC_DATA_HOB;
> > +
> > +///
> > +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB /// typedef struct
> > +{
> > + EFI_GUID PrcessorGuid;
> > + UINTN ProcessorUid;
> > + SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
> > + UINT16 EndingZero;
>
> Please align indentation of struct members.
>
> > +} RISC_V_PROCESSOR_TYPE4_DATA_HOB;
> > +
> > +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
> > +
> > +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
> > + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
> > + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
> > + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
> > +
> > +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
> #define
> > +RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 <<
> > +RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 <<
> > +RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
> > +
> > +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
> #define
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 <<
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0
> <<
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1
> <<
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2
> <<
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3
> <<
> > +RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
> > +
> > +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
> > +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 <<
> RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 <<
> RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
> > +
> > +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
> > +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 <<
> RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 <<
> RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 <<
> RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 <<
> RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> > + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 <<
> > +RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
> > +///
> > +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB /// typedef struct {
> > + EFI_GUID PrcessorGuid;
> > + UINTN ProcessorUid;
> > + SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
> > + UINT16 EndingZero;
> > +} RISC_V_PROCESSOR_TYPE7_DATA_HOB;
> > +
> > +///
> > +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB /// typedef struct {
> > + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor;
> > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache;
> > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache;
> > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache;
> > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache; }
> > +RISC_V_PROCESSOR_SMBIOS_DATA_HOB;
>
> I don't see this structure being used anywhere - can it be deleted?
Used in platform code to build up processor information in HOB.
>
> > +
> > +#pragma pack()
> > +
> > +#endif
> > diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > new file mode 100644
> > index 0000000..36aa4ab
> > --- /dev/null
> > +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > @@ -0,0 +1,58 @@
> > +/** @file
> > + Industry Standard Definitions of RISC-V Processor Specific data
> > +defined in
> > + below link for complaiant with SMBIOS Table Specification v3.3.0.
> > + https://github.com/riscv/riscv-smbios
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
> > +#define _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
>
> Drop leading _.
>
> > +
> > +#include <IndustryStandard/SmBios.h>
> > +
> > +#include <RiscV.h>
> > +
> > +#pragma pack(1)
> > +
> > +typedef enum{
> > + RegisterUnsupported = 0x00,
> > + RegisterLen32 = 0x01,
> > + RegisterLen64 = 0x02,
> > + RegisterLen128 = 0x03
> > +} RISC_V_REGISTER_LENGTH;
> > +
> > +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
> > +
> > +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 <<
> 0)
> > +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01
> << 2)
> > +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
> > +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
> > +
> > +///
> > +/// RISC-V processor specific data for SMBIOS type 44 /// typedef
> > +struct {
> > + UINT16 Revision;
> > + UINT8 Length;
> > + RISCV_UINT128 HartId;
> > + UINT8 BootHartId;
> > + RISCV_UINT128 MachineVendorId;
> > + RISCV_UINT128 MachineArchId;
> > + RISCV_UINT128 MachineImplId;
> > + UINT32 InstSetSupported;
> > + UINT8 PrivilegeModeSupported;
> > + RISCV_UINT128 MModeExcepDelegation;
> > + RISCV_UINT128 MModeInterruptDelegation;
> > + UINT8 HartXlen;
> > + UINT8 MachineModeXlen;
> > + UINT8 Reserved;
> > + UINT8 SupervisorModeXlen;
> > + UINT8 UserModeXlen;
> > +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
> > +
> > +#pragma pack()
> > +#endif
> > +
> > diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec index
> > a91392f..b316223 100644
> > --- a/RiscVPkg/RiscVPkg.dec
> > +++ b/RiscVPkg/RiscVPkg.dec
> > @@ -24,6 +24,12 @@
> > gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, {
> > 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
> >
> > [PcdsFixedAtBuild]
> > + # Processor Specific Data GUID HOB GUID
> > +
> gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x2
> > + 0, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90,
> > + 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
> > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F,
> > + 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B,
> > + 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
> > +
> gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x
> 5B
> > + , 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0,
> > + 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
> > +
> gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0x
> BF
> > + , 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E,
> > + 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
> > +
> > #
> > # 1000000000
> > # PcdRiscVMachineTimerTickInNanoSecond =
> > ---------------------------------------
> > diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > new file mode 100644
> > index 0000000..032f559
> > --- /dev/null
> > +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > @@ -0,0 +1,339 @@
> > +/** @file
> > + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and
> type 44 records.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include "RiscVSmbiosDxe.h"
> > +
> > +#define RISCV_SMBIOS_DEBUG_INFO 1
>
> I would greatly prefer if we could drop this and If there's still active
> development of the tables, I can go along with keeping it while on the -
> staging branch, but it needs to go before the port is merged to edk2 master.
> You can use DEBUG_VERBOSE instead.
>
> > +
> > +EFI_SMBIOS_PROTOCOL *Smbios;
>
> mSmBios. And STATIC.
>
> > +
> > +/**
> > + This function builds SMBIOS type 7 record according to
> > + the given RISC_V_PROCESSOR_TYPE7_DATA_HOB.
> > +
> > + @param Type4DataHob Pointer to
> RISC_V_PROCESSOR_TYPE4_DATA_HOB
> > + @param Type7DataHob Pointer to
> RISC_V_PROCESSOR_TYPE7_DATA_HOB
> > + @param SmbiosHandle Pointer to SMBIOS_HANDLE
> > +
> > + @retval EFI_STATUS
> > +
> > +**/
> > +static
>
> STATIC
>
> > +EFI_STATUS
> > +BuildSmbiosType7 (
> > + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, IN
> > +RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob, OUT
> SMBIOS_HANDLE
> > +*SmbiosHandle
> > +)
> > +{
> > + EFI_STATUS Status;
> > + SMBIOS_HANDLE Handle;
> > +
> > + if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob-
> >PrcessorGuid) ||
> > + Type4DataHob->ProcessorUid != Type7DataHob->ProcessorUid) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > + Handle = SMBIOS_HANDLE_PI_RESERVED;
> > + Type7DataHob->SmbiosType7Cache.Hdr.Type =
> > +SMBIOS_TYPE_CACHE_INFORMATION;
> > + Type7DataHob->SmbiosType7Cache.Hdr.Length =
> > +sizeof(SMBIOS_TABLE_TYPE7);
> > + Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
> > + Type7DataHob->EndingZero = 0;
> > + Status = Smbios->Add (Smbios, NULL, &Handle,
> > +&Type7DataHob->SmbiosType7Cache.Hdr);
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS
> Type 7\n"));
> > + return Status;
> > + }
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was
> > +added. SMBIOS Handle: 0x%x\n", Handle)); #if
> RISCV_SMBIOS_DEBUG_INFO
> > + DEBUG ((DEBUG_INFO, " Cache belone to processor GUID:
> %g\n", &Type7DataHob->PrcessorGuid));
> > + DEBUG ((DEBUG_INFO, " Cache belone processor UID:
> %d\n", Type7DataHob->ProcessorUid));
> > + DEBUG ((DEBUG_INFO, "
> ==============================\n"));
> > + DEBUG ((DEBUG_INFO, " Socket Designation: %d\n",
> Type7DataHob->SmbiosType7Cache.SocketDesignation));
> > + DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.CacheConfiguration));
> > + DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
> > + DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.InstalledSize));
> > + DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
> > + DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
> > + DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.CacheSpeed));
> > + DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
> > + DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.SystemCacheType));
> > + DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n",
> Type7DataHob->SmbiosType7Cache.Associativity));
> > +#endif
> > +
> > + *SmbiosHandle = Handle;
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + This function builds SMBIOS type 4 record according to
> > + the given RISC_V_PROCESSOR_TYPE4_DATA_HOB.
> > +
> > + @param Type4DataHob Pointer to
> RISC_V_PROCESSOR_TYPE4_DATA_HOB
> > + @param SmbiosHandle Pointer to SMBIOS_HANDLE
> > +
> > + @retval EFI_STATUS
> > +
> > +**/
> > +static
> > +EFI_STATUS
> > +BuildSmbiosType4 (
> > + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
> > + OUT SMBIOS_HANDLE *SmbiosHandle
> > + )
> > +{
> > + EFI_HOB_GUID_TYPE *GuidHob;
>
> The code would be more readable if this was called something like Type7Hob.
>
> > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData;
> SMBIOS_HANDLE
> > + Cache; SMBIOS_HANDLE Processor; EFI_STATUS Status;
> > +
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type
> > + 4.\n"));
>
> Again, please avoid the custom [] message tags - add %a __FUNCTION__
> where helpul. Throughout.
>
> > + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n",
> &Type4DataHob->PrcessorGuid));
> > + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n",
> Type4DataHob->ProcessorUid));
> > +
> > + Type4DataHob->SmbiosType4Processor.L1CacheHandle =
> > + RISC_V_CACHE_INFO_NOT_PROVIDED;
> > + Type4DataHob->SmbiosType4Processor.L2CacheHandle =
> > + RISC_V_CACHE_INFO_NOT_PROVIDED;
> > + Type4DataHob->SmbiosType4Processor.L3CacheHandle =
> > + RISC_V_CACHE_INFO_NOT_PROVIDED; GuidHob =
> (EFI_HOB_GUID_TYPE
> > + *)GetFirstGuidHob ((EFI_GUID
> > + *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
> > + if (GuidHob == NULL) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS
> Type7 data HOB found.\n"));
> > + return EFI_NOT_FOUND;
> > + }
> > + //
> > + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple
> processors.
> > + //
> > + do {
> > + Type7HobData = (RISC_V_PROCESSOR_TYPE7_DATA_HOB
> *)GET_GUID_HOB_DATA (GuidHob);
> > + Status = BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + if ((Type7HobData->SmbiosType7Cache.SystemCacheType &
> RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> > + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
> > + Type4DataHob->SmbiosType4Processor.L1CacheHandle = Cache;
> > + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType &
> RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> > + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
> > + Type4DataHob->SmbiosType4Processor.L2CacheHandle = Cache;
> > + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType &
> RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
> > + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
> > + Type4DataHob->SmbiosType4Processor.L3CacheHandle = Cache;
> > + } else {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Improper cache
> level of SMBIOS handle %d\n", Cache));
> > + }
> > + GuidHob = GetNextGuidHob((EFI_GUID
> > + *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid),
> > + GET_NEXT_HOB(GuidHob)); } while (GuidHob != NULL);
> > +
> > + //
> > + // Build SMBIOS Type 4 record
> > + //
> > + Processor = SMBIOS_HANDLE_PI_RESERVED;
> > + Type4DataHob->SmbiosType4Processor.Hdr.Type =
> > +SMBIOS_TYPE_PROCESSOR_INFORMATION;
> > + Type4DataHob->SmbiosType4Processor.Hdr.Length =
> > +sizeof(SMBIOS_TABLE_TYPE4);
> > + Type4DataHob->SmbiosType4Processor.Hdr.Handle = 0;
> > + Type4DataHob->EndingZero = 0;
> > + Status = Smbios->Add (Smbios, NULL, &Processor,
> > +&Type4DataHob->SmbiosType4Processor.Hdr);
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS
> Type 4\n"));
> > + return Status;
> > + }
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was
> > +added. SMBIOS Handle: 0x%x\n", Processor)); #if
> RISCV_SMBIOS_DEBUG_INFO
> > + DEBUG ((DEBUG_INFO, " Socket StringID: %d\n",
> Type4DataHob->SmbiosType4Processor.Socket));
> > + DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ProcessorType));
> > + DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ProcessorFamily));
> > + DEBUG ((DEBUG_INFO, " Processor Manufacture StringID:
> %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture));
> > + DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n", \
> > + Type4DataHob->SmbiosType4Processor.ProcessorId.Signature,
> Type4DataHob->SmbiosType4Processor.ProcessorId.FeatureFlags));
> > + DEBUG ((DEBUG_INFO, " Processor Version StringID: %d\n",
> Type4DataHob->SmbiosType4Processor.ProcessorVersion));
> > + DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4DataHob-
> >SmbiosType4Processor.Voltage));
> > + DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ExternalClock));
> > + DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.MaxSpeed));
> > + DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.CurrentSpeed));
> > + DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4DataHob-
> >SmbiosType4Processor.Status));
> > + DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ProcessorUpgrade));
> > + DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.L1CacheHandle));
> > + DEBUG ((DEBUG_INFO, " L2 Cache Handle:
> 0x%x\n",Type4DataHob->SmbiosType4Processor.L2CacheHandle));
> > + DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.L3CacheHandle));
> > + DEBUG ((DEBUG_INFO, " Serial Number StringID: %d\n",
> Type4DataHob->SmbiosType4Processor.SerialNumber));
> > + DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n",
> Type4DataHob->SmbiosType4Processor.AssetTag));
> > + DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n",
> Type4DataHob->SmbiosType4Processor.PartNumber));
> > + DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4DataHob-
> >SmbiosType4Processor.CoreCount));
> > + DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n",
> Type4DataHob->SmbiosType4Processor.EnabledCoreCount));
> > + DEBUG ((DEBUG_INFO, " Thread Count: %d\n",
> Type4DataHob->SmbiosType4Processor.ThreadCount));
> > + DEBUG ((DEBUG_INFO, " Processor Characteristics: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics));
> > + DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n",
> Type4DataHob->SmbiosType4Processor.ProcessorFamily2));
> > + DEBUG ((DEBUG_INFO, " Core Count 2: %d\n",
> Type4DataHob->SmbiosType4Processor.CoreCount2));
> > + DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n",
> Type4DataHob->SmbiosType4Processor.EnabledCoreCount2));
> > + DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n",
> Type4DataHob->SmbiosType4Processor.ThreadCount2));
> > +#endif
> > +
> > + *SmbiosHandle = Processor;
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + This function builds SMBIOS type 44 record according..
> > +
> > + @param Type4DataHob Pointer to
> RISC_V_PROCESSOR_TYPE4_DATA_HOB
> > + @param Type4Handle SMBIOS handle of type 4
> > +
> > + @retval EFI_STATUS
> > +
> > +**/
> > +EFI_STATUS
> > +BuildSmbiosType44 (
> > + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
> > + IN SMBIOS_HANDLE Type4Handle
> > + )
> > +{
> > + EFI_HOB_GUID_TYPE *GuidHob;
>
> ProcessorSpecificDataHob? Or Type44Hob?
>
> > + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData;
> > + SMBIOS_HANDLE RiscVType44;
> > + SMBIOS_TABLE_TYPE44 *Type44Ptr;
> > + EFI_STATUS Status;
> > +
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 44
> > +for...\n")); #if RISCV_SMBIOS_DEBUG_INFO
> > + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n",
> &Type4DataHob->PrcessorGuid));
> > + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n",
> Type4DataHob->ProcessorUid));
> > +#endif
> > +
> > + GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID
> > + *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
> > + if (GuidHob == NULL) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No
> RISC_V_PROCESSOR_SPECIFIC_DATA_HOB found.\n"));
> > + return EFI_NOT_FOUND;
> > + }
> > + //
> > + // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for
> multiple cores.
> > + //
> > + do {
> > + ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
> *)GET_GUID_HOB_DATA (GuidHob);
> > + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid,
> &Type4DataHob->PrcessorGuid) ||
> > + ProcessorSpecificData->ParentProcessorUid != Type4DataHob-
> >ProcessorUid) {
> > + GuidHob = GetNextGuidHob((EFI_GUID
> *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid),
> GET_NEXT_HOB(GuidHob));
> > + if (GuidHob == NULL) {
> > + break;
> > + }
> > + continue;
> > + }
> > +
> > +#if RISCV_SMBIOS_DEBUG_INFO
> > + DEBUG ((DEBUG_INFO,
> "[ ================================\n"));
> > + DEBUG ((DEBUG_INFO, "[ Core GUID: %g\n",
> &ProcessorSpecificData->CoreGuid));
> > +#endif
> > +
> > + Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) +
> sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending
> zero.
> > + if (Type44Ptr == NULL) {
> > + return EFI_NOT_FOUND;
> > + }
> > + Type44Ptr->Hdr.Type =
> SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
> > + Type44Ptr->Hdr.Handle = 0;
> > + Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) +
> sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
> > + Type44Ptr->RefHandle = Type4Handle;
> > + Type44Ptr->ProcessorSpecificBlock.Length =
> sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
> > + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =
> Type4DataHob->SmbiosType4Processor.ProcessorFamily2 -
> > + ProcessorFamilyRiscvRV32 + \
> > + ProcessorSpecificBlockArchTypeRiscVRV32;
> > + CopyMem ((VOID *)(Type44Ptr + 1), (VOID
> > + *)&ProcessorSpecificData->ProcessorSpecificData, sizeof
> > + (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
> > +
> > +#if RISCV_SMBIOS_DEBUG_INFO
> > + DEBUG ((DEBUG_INFO, "[ Core type: %d\n", Type44Ptr-
> >ProcessorSpecificBlock.ProcessorArchType));
> > + DEBUG ((DEBUG_INFO, " HartId = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >HartId.Value64_L));
> > + DEBUG ((DEBUG_INFO, " Is Boot Hart? = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >BootHartId));
> > + DEBUG ((DEBUG_INFO, " PrivilegeModeSupported =
> 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr +
> 1))->PrivilegeModeSupported));
> > + DEBUG ((DEBUG_INFO, " MModeExcepDelegation =
> 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr +
> 1))->MModeExcepDelegation.Value64_L));
> > + DEBUG ((DEBUG_INFO, " MModeInterruptDelegation =
> 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr +
> 1))->MModeInterruptDelegation.Value64_L));
> > + DEBUG ((DEBUG_INFO, " HartXlen = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >HartXlen));
> > + DEBUG ((DEBUG_INFO, " MachineModeXlen = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >MachineModeXlen));
> > + DEBUG ((DEBUG_INFO, " SupervisorModeXlen = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >SupervisorModeXlen));
> > + DEBUG ((DEBUG_INFO, " UserModeXlen = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >UserModeXlen));
> > + DEBUG ((DEBUG_INFO, " InstSetSupported = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >InstSetSupported));
> > + DEBUG ((DEBUG_INFO, " MachineVendorId = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >MachineVendorId.Value64_L));
> > + DEBUG ((DEBUG_INFO, " MachineArchId = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >MachineArchId.Value64_L));
> > + DEBUG ((DEBUG_INFO, " MachineImplId = 0x%x\n",
> ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-
> >MachineImplId.Value64_L));
> > +#endif
> > +
> > + //
> > + // Add to SMBIOS table.
> > + //
> > + RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
> > + Status = Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS
> Type 44\n"));
> > + return Status;
> > + }
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was
> > + added. SMBIOS Handle: 0x%x\n", RiscVType44));
> > +
> > + GuidHob = GetNextGuidHob((EFI_GUID
> > +*)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid),
> > +GET_NEXT_HOB(GuidHob));
> > + } while (GuidHob != NULL);
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Entry point of RISC-V SMBIOS builder.
> > +
> > + @param ImageHandle Image handle this driver.
> > + @param SystemTable Pointer to the System Table.
> > +
> > + @retval EFI_SUCCESS Thread can be successfully created
> > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data
> structure
> > + @retval EFI_DEVICE_ERROR Cannot create the thread
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +RiscVSmbiosBuilderEntry (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_HOB_GUID_TYPE *GuidHob;
>
> Type4Hob?
>
> > + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData;
> SMBIOS_HANDLE
> > + Processor;
> > +
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a entry\n",
> > + __FUNCTION__));
> > +
> > + Status = gBS->LocateProtocol (
> > + &gEfiSmbiosProtocolGuid,
> > + NULL,
> > + (VOID **)&Smbios
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS
> Protocol fail\n"));
> > + return Status;
> > + }
> > + GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID
> > + *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
> > + if (GuidHob == NULL) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS
> information found.\n"));
> > + return EFI_NOT_FOUND;
> > + }
> > + Type4HobData = (RISC_V_PROCESSOR_TYPE4_DATA_HOB
> *)GET_GUID_HOB_DATA
> > + (GuidHob); Status = EFI_NOT_FOUND; // // Go through each
> > + RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
> > + //
> > + do {
> > + Status = BuildSmbiosType4 (Type4HobData, &Processor);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS
> type 4 created.\n"));
> > + ASSERT (FALSE);
> > + }
> > + Status = BuildSmbiosType44 (Type4HobData, Processor);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS
> type 44 found.\n"));
> > + ASSERT (FALSE);
> > + }
> > +
> > + GuidHob = GetNextGuidHob((EFI_GUID
> > +*)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid),
> > +GET_NEXT_HOB(GuidHob));
> > + } while (GuidHob != NULL);
> > + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a exit\n",
> > +__FUNCTION__));
> > + return Status;
> > +}
> > +
> > diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > new file mode 100644
> > index 0000000..dfa1fc6
> > --- /dev/null
> > +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > @@ -0,0 +1,32 @@
> > +/** @file
> > + RISC-V SMBIOS Builder DXE module header file.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef _RISC_V_SMBIOS_DXE_H_
> > +#define _RISC_V_SMBIOS_DXE_H_
> > +
> > +#include <PiDxe.h>
> > +
> > +#include <Protocol/Cpu.h>
> > +#include <Protocol/Smbios.h>
> > +
> > +#include <Library/UefiDriverEntryPoint.h> #include
> > +<Library/UefiBootServicesTableLib.h>
> > +#include <Library/DxeServicesTableLib.h> #include <Library/BaseLib.h>
> > +#include <Library/BaseMemoryLib.h> #include
> > +<Library/MemoryAllocationLib.h> #include <Library/DebugLib.h>
> > +#include <Library/UefiLib.h> #include <Library/HobLib.h>
> > +
> > +#include <SmbiosProcessorSpecificData.h> #include
> > +<ProcessorSpecificDataHob.h>
>
> Please move all of these include statements to the files that actually use
> them, then delete this file.
>
> > +
> > +#endif
> > +
> > diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > new file mode 100644
> > index 0000000..59b814a
> > --- /dev/null
> > +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > @@ -0,0 +1,58 @@
> > +## @file
> > +# RISC-V SMBIOS DXE module.
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> # # SPDX-License-Identifier:
> > +BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVSmbiosDxe
> > + MODULE_UNI_FILE = RiscVSmbiosDxe.uni
> > + FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
> > + MODULE_TYPE = DXE_DRIVER
> > + VERSION_STRING = 1.0
> > + ENTRY_POINT = RiscVSmbiosBuilderEntry
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + MdeModulePkg/MdeModulePkg.dec
>
> Please sort alphabetically.
>
> /
> Leif
>
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + BaseMemoryLib
> > + CpuLib
> > + DebugLib
> > + DxeServicesTableLib
> > + HobLib
> > + MemoryAllocationLib
> > + UefiBootServicesTableLib
> > + UefiDriverEntryPoint
> > + UefiLib
> > +
> > +[Sources]
> > + RiscVSmbiosDxe.c
> > + RiscVSmbiosDxe.h
> > +
> > +[Protocols]
> > + gEfiSmbiosProtocolGuid # Consumed
> > +
> > +[Guids]
> > +
> > +
> > +[Pcd]
> > +
> > +[FixedPcd]
> > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
> > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
> > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
> > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
> > +
> > +[Depex]
> > + gEfiSmbiosProtocolGuid
> > +
> > +[UserExtensions.TianoCore."ExtraFiles"]
> > + RiscVSmbiosDxeExtra.uni
> > diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > new file mode 100644
> > index 0000000..1bffe09
> > --- /dev/null
> > +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > @@ -0,0 +1,12 @@
> > +// /** @file
> > +//
> > +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent // // **/
> > +
> > +#string STR_MODULE_ABSTRACT #language en-US "RISC-V
> Processor SMBIOS Builder"
> > +
> > +#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V
> Processor SMBIOS Type 4, 7, 44 records."
> > +
> > diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> > b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> > new file mode 100644
> > index 0000000..4b37ca2
> > --- /dev/null
> > +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> > @@ -0,0 +1,13 @@
> > +// /** @file
> > +// RISC-V SMBIOS Builder Localized Strings and Content // //
> > +Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent // // **/
> > +
> > +#string STR_PROPERTIES_MODULE_NAME
> > +#language en-US
> > +"RISC-V SMBIOS Record Builder DXE Driver"
> > +
> > --
> > 2.7.4
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2019-10-14 11:27 ` Abner Chang
@ 2019-10-14 11:56 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-10-14 11:56 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Oct 14, 2019 at 11:27:51AM +0000, Abner Chang wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Tuesday, October 1, 2019 6:40 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29]
> > RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
> >
> > On Mon, Sep 23, 2019 at 08:31:52AM +0800, Abner Chang wrote:
> > > RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
> > > and type 44 records.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++++
> > > RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++++
> > > RiscVPkg/RiscVPkg.dec | 6 +
> > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339
> > +++++++++++++++++++++
> > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
> > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++++
> > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
> > > .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
> > > 8 files changed, 613 insertions(+)
> > > create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
> > > create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > > create mode 100644
> > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> > >
> > > diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h
> > > b/RiscVPkg/Include/ProcessorSpecificDataHob.h
> > > new file mode 100644
> > > index 0000000..6798a9d
> > > --- /dev/null
> > > +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h
> >
> > None of the things defined in here are HOBs, they are structures to hold
> > information that will be put into HOBs.
> > Can we merge all of these definitions into SmbiosProcessorSpecificData.h
> > and delete this file?
>
> No. SmbiosProcessorSpecificData.h defines the structure declared in
> RISC-V SMBIOS processor specific data spec
> (https://github.com/riscv/riscv-smbios).
> ProcessorSpecificDataHob is the implementation to deliver processor
> information in HOB for building SMBIOS type 44 record.
Fair enough.
Nevertheless, I find it confusing to refer to the structures being
bundled together into a HOB as if theye were themselves HOB.
An alternative naming scheme for me woud be to rename the file
ProcessorSpecificHobData.h and the structs _HOB_DATA instead of
_DATA_HOB. But I am fully open to replacing these with better names.
> I would like to keep these two files separately.
This is fine, as long as the above concern is addressed.
> > > @@ -0,0 +1,95 @@
> > > +/** @file
> > > + Definition of Processor Specific Data HOB.
> > > +
> > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > > + rights reserved.<BR>
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +#ifndef _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
> > > +#define _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_
> >
> > Please drop leading _.
> >
> > > +
> > > +#include <IndustryStandard/SmBios.h>
> >
> > This file also uses Uefi.h, please include it, so we don't depend on other files
> > pulling it in for us.
> >
> > > +
> > > +#define TO_BE_FILLED 0
> > > +#define TO_BE_FILLED_BY_VENDOR 0
> > > +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 #define
> > > +TO_BE_FILLED_BY_CODE 0
> >
> > These defines are never used, please drop,
>
> These definitions are used in platform code to indicates the value
> is not set correctly and should be set by certain code.
Yes they are, sorry. I had inadvertently checked out the wrong branch
when searching for its use. This and all such related comments can be
ignored.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
2019-09-26 22:56 ` [edk2-devel] " Leif Lindholm
@ 2019-10-14 16:47 ` Abner Chang
2019-10-14 18:23 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-14 16:47 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, September 27, 2019 6:57 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29]
> MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
>
> On Mon, Sep 23, 2019 at 08:31:32AM +0800, Abner Chang wrote:
> > Add RISC-V RV64 BaseLib functions.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > MdePkg/Include/Library/BaseLib.h | 26 ++
> > MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
> > MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++
> > MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +++
> > MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++
> > MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++
> > MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++
> > MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 +++
> > .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++
> > MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++
> > .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++
> > MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++
> > MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++
> > .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++
> > MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264
> +++++++++++++++++++++
> > 15 files changed, 670 insertions(+), 1 deletion(-) create mode
> > 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> >
> > diff --git a/MdePkg/Include/Library/BaseLib.h
> > b/MdePkg/Include/Library/BaseLib.h
> > index 2a75bc0..b8c8512 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -4,6 +4,8 @@
> >
> > Copyright (c) 2006 - 2019, Intel Corporation. All rights
> > reserved.<BR> Portions copyright (c) 2008 - 2009, Apple Inc. All
> > rights reserved.<BR>
> > +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> > +Development LP. All rights reserved.<BR>
> > +
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -124,6 +126,30 @@ typedef struct {
> >
> > #endif // defined (MDE_CPU_AARCH64)
> >
> > +#if defined (MDE_CPU_RISCV64)
> > +///
> > +/// The RISC-V architecture context buffer used by SetJump() and
> LongJump().
> > +///
> > +typedef struct {
> > + UINT64 RA;
> > + UINT64 S0;
> > + UINT64 S1;
> > + UINT64 S2;
> > + UINT64 S3;
> > + UINT64 S4;
> > + UINT64 S5;
> > + UINT64 S6;
> > + UINT64 S7;
> > + UINT64 S8;
> > + UINT64 S9;
> > + UINT64 S10;
> > + UINT64 S11;
> > + UINT64 SP;
> > +} BASE_LIBRARY_JUMP_BUFFER;
> > +
> > +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
> > +
> > +#endif // defined (MDE_CPU_RISCV64)
> >
> > //
> > // String Services
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> > b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 3586beb..28d5795 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -4,6 +4,7 @@
> > # Copyright (c) 2007 - 2019, Intel Corporation. All rights
> > reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All
> > rights reserved.<BR> # Portions copyright (c) 2011 - 2013, ARM Ltd.
> > All rights reserved.<BR>
> > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR>
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@
> > LIBRARY_CLASS = BaseLib
> >
> > #
> > -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> > +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> > #
> >
> > [Sources]
> > @@ -381,6 +382,21 @@
> > AArch64/CpuBreakpoint.asm | MSFT
> > AArch64/SpeculationBarrier.asm | MSFT
> >
> > +[Sources.RISCV64]
> > + Math64.c
> > + RiscV64/Unaligned.c
> > + RiscV64/InternalSwitchStack.c
> > + RiscV64/CpuBreakpoint.c
> > + RiscV64/GetInterruptState.c
> > + RiscV64/DisableInterrupts.c
> > + RiscV64/EnableInterrupts.c
> > + RiscV64/CpuPause.c
> > + RiscV64/RiscVSetJumpLongJump.S | GCC
> > + RiscV64/RiscVCpuBreakpoint.S | GCC
> > + RiscV64/RiscVCpuPause.S | GCC
> > + RiscV64/RiscVInterrupt.S | GCC
> > + RiscV64/FlushCache.S | GCC
> > +
> > [Packages]
> > MdePkg/MdePkg.dec
> >
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> > b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> > new file mode 100644
> > index 0000000..d82b1d5
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> > @@ -0,0 +1,27 @@
> > +/** @file
> > + CPU breakpoint for RISC-V
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +extern VOID RiscVCpuBreakpoint (VOID);
> > +
> > +/**
> > + Generates a breakpoint on the CPU.
> > +
> > + Generates a breakpoint on the CPU. The breakpoint must be
> > + implemented such that code can resume normal execution after the
> breakpoint.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +CpuBreakpoint (
> > + VOID
> > + )
> > +{
> > + RiscVCpuBreakpoint ();
> > +}
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> > b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> > new file mode 100644
> > index 0000000..8eb6b65
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> > @@ -0,0 +1,29 @@
> > +/** @file
> > + CPU pause for RISC-V
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +extern VOID RiscVCpuPause (VOID);
> > +
> > +
> > +/**
> > + Requests CPU to pause for a short period of time.
> > +
> > + Requests CPU to pause for a short period of time. Typically used in
> > + MP systems to prevent memory starvation while waiting for a spin lock.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +CpuPause (
> > + VOID
> > + )
> > +{
> > + RiscVCpuPause ();
> > +}
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> > b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> > new file mode 100644
> > index 0000000..7ee5eb1
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> > @@ -0,0 +1,24 @@
> > +/** @file
> > + CPU disable interrupt function for RISC-V
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > +"BaseLibInternals.h"
> > +
> > +extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
> > +
> > +/**
> > + Disables CPU interrupts.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +DisableInterrupts (
> > + VOID
> > + )
> > +{
> > + RiscVDisableSupervisorModeInterrupts (); }
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> > b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> > new file mode 100644
> > index 0000000..9aa0d9a
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> > @@ -0,0 +1,25 @@
> > +/** @file
> > + CPU enable interrupt function for RISC-V
> > +
> > + Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP.
> > + All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
> > +
> > +/**
> > + Enables CPU interrupts.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +EnableInterrupts (
> > + VOID
> > + )
> > +{
> > + RiscVEnableSupervisorModeInterrupt (); }
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> > b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> > new file mode 100644
> > index 0000000..0ef0213
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> > @@ -0,0 +1,21 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// RISC-V cache operation.
> > +//
> > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +
> > +.align 3
> > +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
> > +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
> > +
> > +ASM_PFX(RiscVInvalidateInstCacheAsm):
> > + fence.i
> > + ret
> > +
> > +ASM_PFX(RiscVInvalidateDataCacheAsm):
> > + fence
> > + ret
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> > b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> > new file mode 100644
> > index 0000000..8f764fb
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> > @@ -0,0 +1,35 @@
> > +/** @file
> > + CPU get interrupt state function for RISC-V
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
> > +
> > +/**
> > + Retrieves the current CPU interrupt state.
> > +
> > + Returns TRUE is interrupts are currently enabled. Otherwise
> > + returns FALSE.
> > +
> > + @retval TRUE CPU interrupts are enabled.
> > + @retval FALSE CPU interrupts are disabled.
> > +
> > +**/
> > +BOOLEAN
> > +EFIAPI
> > +GetInterruptState (
> > + VOID
> > + )
> > +{
> > + unsigned long RetValue;
> > +
> > + RetValue = RiscVGetSupervisorModeInterrupts ();
> > + return RetValue? TRUE: FALSE;
> > +}
> > +
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> > b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> > new file mode 100644
> > index 0000000..1082d4e
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> > @@ -0,0 +1,55 @@
> > +/** @file
> > + Switch stack function for RISC-V
> > +
> > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +/**
> > + Transfers control to a function starting with a new stack.
> > +
> > + Transfers control to the function specified by EntryPoint using the
> > + new stack specified by NewStack and passing in the parameters
> > + specified by Context1 and Context2. Context1 and Context2 are
> > + optional and may be NULL. The function EntryPoint must never return.
> > + Marker will be ignored on IA-32, x64, and EBC.
> > + IPF CPUs expect one additional parameter of type VOID * that
> > + specifies the new backing store pointer.
> > +
> > + If EntryPoint is NULL, then ASSERT().
> > + If NewStack is NULL, then ASSERT().
> > +
> > + @param EntryPoint A pointer to function to call with the new stack.
> > + @param Context1 A pointer to the context to pass into the EntryPoint
> > + function.
> > + @param Context2 A pointer to the context to pass into the EntryPoint
> > + function.
> > + @param NewStack A pointer to the new stack to use for the EntryPoint
> > + function.
> > + @param Marker VA_LIST marker for the variable argument list.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +InternalSwitchStack (
> > + IN SWITCH_STACK_ENTRY_POINT EntryPoint,
> > + IN VOID *Context1, OPTIONAL
> > + IN VOID *Context2, OPTIONAL
> > + IN VOID *NewStack,
> > + IN VA_LIST Marker
> > + )
> > +{
> > + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
> > +
> > + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x
> Context1:%x Context2:%x NewStack%x\n", \
> > + EntryPoint, Context1, Context2, NewStack));
> > + JumpBuffer.RA = (UINTN)EntryPoint;
> > + JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
> > + JumpBuffer.S0 = (UINT64)(UINTN)Context1;
> > + JumpBuffer.S1 = (UINT64)(UINTN)Context2;
> > + LongJump (&JumpBuffer, (UINTN)-1);
> > + ASSERT(FALSE);
> > +}
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> > b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> > new file mode 100644
> > index 0000000..a62b882
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
> > @@ -0,0 +1,32 @@
> > +/** @file
> > + Long jump implementation of RISC-V
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +
> > +/**
> > + Restores the CPU context that was saved with SetJump().
> > +
> > + Restores the CPU context from the buffer specified by JumpBuffer.
> > + This function never returns to the caller.
> > + Instead is resumes execution based on the state of JumpBuffer.
> > +
> > + @param JumpBuffer A pointer to CPU context buffer.
> > + @param Value The value to return when the SetJump() context is
> restored.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +InternalLongJump (
> > + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
> > + IN UINTN Value
> > + )
> > +{
> > + ASSERT (FALSE);
> > +}
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> > b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> > new file mode 100644
> > index 0000000..1a45e2a
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> > @@ -0,0 +1,14 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// CpuBreakpoint for RISC-V
> > +//
> > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +
> > +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
> > +ASM_PFX(RiscVCpuBreakpoint):
> > + ebreak
> > + ret
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> > b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> > new file mode 100644
> > index 0000000..ceba0c0
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> > @@ -0,0 +1,14 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// CpuPause for RISC-V
> > +//
> > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +
> > +ASM_GLOBAL ASM_PFX(RiscVCpuPause)
> > +ASM_PFX(RiscVCpuPause):
> > + nop
> > + ret
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> > b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> > new file mode 100644
> > index 0000000..8fdb544
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> > @@ -0,0 +1,32 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// RISC-V Supervisor Mode interrupt enable/disable // // Copyright
> > +(c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +
> > +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
> > +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
> > +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
> > +
> > +# define MSTATUS_SIE 0x00000002
> > +# define CSR_SSTATUS 0x100
> > +
> > +ASM_PFX(RiscVDisableSupervisorModeInterrupts):
> > + li a1, MSTATUS_SIE
> > + csrc CSR_SSTATUS, a1
> > + ret
> > +
> > +ASM_PFX(RiscVEnableSupervisorModeInterrupt):
> > + li a1, MSTATUS_SIE
> > + csrs CSR_SSTATUS, a1
> > + ret
> > +
> > +ASM_PFX(RiscVGetSupervisorModeInterrupts):
> > + csrr a0, CSR_SSTATUS
> > + andi a0, a0, MSTATUS_SIE
> > + ret
> > +
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> > b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> > new file mode 100644
> > index 0000000..e72dd7f
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> > @@ -0,0 +1,55 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// Set/Long jump for RISC-V
> > +//
> > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +# define REG_S sd
> > +# define REG_L ld
> > +# define SZREG 8
> > +.align 3
> > + .globl SetJump
> > +
> > +SetJump:
> > + REG_S ra, 0*SZREG(a0)
> > + REG_S s0, 1*SZREG(a0)
> > + REG_S s1, 2*SZREG(a0)
> > + REG_S s2, 3*SZREG(a0)
> > + REG_S s3, 4*SZREG(a0)
> > + REG_S s4, 5*SZREG(a0)
> > + REG_S s5, 6*SZREG(a0)
> > + REG_S s6, 7*SZREG(a0)
> > + REG_S s7, 8*SZREG(a0)
> > + REG_S s8, 9*SZREG(a0)
> > + REG_S s9, 10*SZREG(a0)
> > + REG_S s10,11*SZREG(a0)
> > + REG_S s11,12*SZREG(a0)
> > + REG_S sp, 13*SZREG(a0)
>
> Please adjust indentation of all of the asm code so that there is space after ','
> and on both sides of '*'.
>
> > + li a0, 0
> > + ret
> > +
> > + .globl InternalLongJump
> > +InternalLongJump:
> > + REG_L ra, 0*SZREG(a0)
> > + REG_L s0, 1*SZREG(a0)
> > + REG_L s1, 2*SZREG(a0)
> > + REG_L s2, 3*SZREG(a0)
> > + REG_L s3, 4*SZREG(a0)
> > + REG_L s4, 5*SZREG(a0)
> > + REG_L s5, 6*SZREG(a0)
> > + REG_L s6, 7*SZREG(a0)
> > + REG_L s7, 8*SZREG(a0)
> > + REG_L s8, 9*SZREG(a0)
> > + REG_L s9, 10*SZREG(a0)
> > + REG_L s10,11*SZREG(a0)
> > + REG_L s11,12*SZREG(a0)
> > + REG_L sp, 13*SZREG(a0)
> > +
> > + add a0, s0, 0
> > + add a1, s1, 0
> > + add a2, s2, 0
> > + add a3, s3, 0
> > + ret
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> > b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> > new file mode 100644
> > index 0000000..012d913
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
>
> We do need to fix BaseLib/Unaligned.c (as well as the associated definitions
> in header file), but having a separate implementation for RISCV does not
> make sense.
>
Leif, not quite understand this. So you would like RISCV to use generic Unaligned.c?
> /
> Leif
>
>
> > @@ -0,0 +1,264 @@
> > +/** @file
> > + RISC-V specific functionality for (un)aligned memory read/write.
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#include "BaseLibInternals.h"
> > +
> > +/**
> > + Reads a 16-bit value from memory that may be unaligned.
> > +
> > + This function returns the 16-bit value pointed to by Buffer. The
> > + function guarantees that the read operation does not produce an
> alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 16-bit value that may be unaligned.
> > +
> > + @return The 16-bit value read from Buffer.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +ReadUnaligned16 (
> > + IN CONST UINT16 *Buffer
> > + )
> > +{
> > + UINT16 Value;
> > + INT8 Count;
> > +
> > + ASSERT (Buffer != NULL);
> > +
> > + for (Count = sizeof (UINT16) - 1, Value = 0; Count >= 0 ; Count --) {
> > + Value = Value << 8;
> > + Value |= *((UINT8*)Buffer + Count);
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Writes a 16-bit value to memory that may be unaligned.
> > +
> > + This function writes the 16-bit value specified by Value to Buffer.
> > + Value is returned. The function guarantees that the write operation
> > + does not produce an alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 16-bit value that may be unaligned.
> > + @param Value 16-bit value to write to Buffer.
> > +
> > + @return The 16-bit value to write to Buffer.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +WriteUnaligned16 (
> > + OUT UINT16 *Buffer,
> > + IN UINT16 Value
> > + )
> > +{
> > + INT8 Count;
> > + UINT16 ValueTemp;
> > +
> > + ASSERT (Buffer != NULL);
> > +
> > + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT16) ; Count ++) {
> > + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> > + ValueTemp = ValueTemp >> 8;
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Reads a 24-bit value from memory that may be unaligned.
> > +
> > + This function returns the 24-bit value pointed to by Buffer. The
> > + function guarantees that the read operation does not produce an
> alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 24-bit value that may be unaligned.
> > +
> > + @return The 24-bit value read from Buffer.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +ReadUnaligned24 (
> > + IN CONST UINT32 *Buffer
> > + )
> > +{
> > + UINT32 Value;
> > + INT8 Count;
> > +
> > + ASSERT (Buffer != NULL);
> > + for (Count = 2, Value = 0; Count >= 0 ; Count --) {
> > + Value = Value << 8;
> > + Value |= *((UINT8*)Buffer + Count);
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Writes a 24-bit value to memory that may be unaligned.
> > +
> > + This function writes the 24-bit value specified by Value to Buffer.
> > + Value is returned. The function guarantees that the write operation
> > + does not produce an alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 24-bit value that may be unaligned.
> > + @param Value 24-bit value to write to Buffer.
> > +
> > + @return The 24-bit value to write to Buffer.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +WriteUnaligned24 (
> > + OUT UINT32 *Buffer,
> > + IN UINT32 Value
> > + )
> > +{
> > + INT8 Count;
> > + UINT32 ValueTemp;
> > +
> > + ASSERT (Buffer != NULL);
> > + for (Count = 0, ValueTemp = Value; Count < 3 ; Count ++) {
> > + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> > + ValueTemp = ValueTemp >> 8;
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Reads a 32-bit value from memory that may be unaligned.
> > +
> > + This function returns the 32-bit value pointed to by Buffer. The
> > + function guarantees that the read operation does not produce an
> alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 32-bit value that may be unaligned.
> > +
> > + @return The 32-bit value read from Buffer.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +ReadUnaligned32 (
> > + IN CONST UINT32 *Buffer
> > + )
> > +{
> > + UINT32 Value;
> > + INT8 Count;
> > +
> > + ASSERT (Buffer != NULL);
> > +
> > + for (Count = sizeof (UINT32) - 1, Value = 0; Count >= 0 ; Count --) {
> > + Value = Value << 8;
> > + Value |= *((UINT8*)Buffer + Count);
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Writes a 32-bit value to memory that may be unaligned.
> > +
> > + This function writes the 32-bit value specified by Value to Buffer.
> > + Value is returned. The function guarantees that the write operation
> > + does not produce an alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 32-bit value that may be unaligned.
> > + @param Value The 32-bit value to write to Buffer.
> > +
> > + @return The 32-bit value to write to Buffer.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +WriteUnaligned32 (
> > + OUT UINT32 *Buffer,
> > + IN UINT32 Value
> > + )
> > +{
> > + INT8 Count;
> > + UINT32 ValueTemp;
> > +
> > + ASSERT (Buffer != NULL);
> > + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT32) ; Count ++) {
> > + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> > + ValueTemp = ValueTemp >> 8;
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Reads a 64-bit value from memory that may be unaligned.
> > +
> > + This function returns the 64-bit value pointed to by Buffer. The
> > + function guarantees that the read operation does not produce an
> alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 64-bit value that may be unaligned.
> > +
> > + @return The 64-bit value read from Buffer.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +ReadUnaligned64 (
> > + IN CONST UINT64 *Buffer
> > + )
> > +{
> > + UINT64 Value;
> > + INT8 Count;
> > +
> > + ASSERT (Buffer != NULL);
> > + for (Count = sizeof (UINT64) - 1, Value = 0; Count >= 0 ; Count --) {
> > + Value = Value << 8;
> > + Value |= *((UINT8*)Buffer + Count);
> > + }
> > + return Value;
> > +}
> > +
> > +/**
> > + Writes a 64-bit value to memory that may be unaligned.
> > +
> > + This function writes the 64-bit value specified by Value to Buffer.
> > + Value is returned. The function guarantees that the write operation
> > + does not produce an alignment fault.
> > +
> > + If the Buffer is NULL, then ASSERT().
> > +
> > + @param Buffer A pointer to a 64-bit value that may be unaligned.
> > + @param Value The 64-bit value to write to Buffer.
> > +
> > + @return The 64-bit value to write to Buffer.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +WriteUnaligned64 (
> > + OUT UINT64 *Buffer,
> > + IN UINT64 Value
> > + )
> > +{
> > + INT8 Count;
> > + UINT64 ValueTemp;
> > +
> > + ASSERT (Buffer != NULL);
> > + for (Count = 0, ValueTemp = Value; Count < sizeof (UINT64) ; Count ++) {
> > + *((UINT8*)Buffer + Count) = (UINT8)(ValueTemp & 0xff);
> > + ValueTemp = ValueTemp >> 8;
> > + }
> > + return Value;
> > +}
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
2019-10-14 16:47 ` Abner Chang
@ 2019-10-14 18:23 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-10-14 18:23 UTC (permalink / raw)
To: devel, abner.chang
On Mon, Oct 14, 2019 at 04:47:30PM +0000, Abner Chang wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, September 27, 2019 6:57 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29]
> > MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
> >
> > On Mon, Sep 23, 2019 at 08:31:32AM +0800, Abner Chang wrote:
> > > Add RISC-V RV64 BaseLib functions.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> > > b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> > > new file mode 100644
> > > index 0000000..012d913
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> >
> > We do need to fix BaseLib/Unaligned.c (as well as the associated definitions
> > in header file), but having a separate implementation for RISCV does not
> > make sense.
>
> Leif, not quite understand this. So you would like RISCV to use generic Unaligned.c?
Yes please.
/
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-09-30 20:03 ` [edk2-devel] " Leif Lindholm
@ 2019-10-15 1:21 ` Abner Chang
2019-10-15 8:35 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-15 1:21 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, October 1, 2019 4:04 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29]
> RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
>
> On Mon, Sep 23, 2019 at 08:31:44AM +0800, Abner Chang wrote:
> > EDK2 RISC-V OpenSBI library which pull in external source files under
> > RiscVPkg/opensbi to the build process.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52
> ++++++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> > create mode 100644
> > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> >
> > diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > new file mode 100644
> > index 0000000..640ffba
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > @@ -0,0 +1,52 @@
> > +## @file
> > +# RISC-V Opensbi Library Instance.
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> # # SPDX-License-Identifier:
> > +BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVOpensbiLib
> > + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVOpensbiLib
> > +
> > +[Sources]
> > + ../../opensbi/lib/sbi/riscv_asm.c
>
> Please move the opensbi directory to here instead.
>
This is good. Now [Includes] in RiscVPkg.dec looks like this,
[Includes]
Library/RiscvOpensbiLib/opensbi
Library/RiscvOpensbiLib/opensbi/include
> /
> Leif
>
> > + ../../opensbi/lib/sbi/riscv_atomic.c
> > + ../../opensbi/lib/sbi/riscv_hardfp.S
> > + ../../opensbi/lib/sbi/riscv_locks.c
> > + ../../opensbi/lib/sbi/riscv_unpriv.c
> > + ../../opensbi/lib/sbi/sbi_console.c
> > + ../../opensbi/lib/sbi/sbi_ecall.c
> > + ../../opensbi/lib/sbi/sbi_emulate_csr.c
> > + ../../opensbi/lib/sbi/sbi_fifo.c
> > + ../../opensbi/lib/sbi/sbi_hart.c
> > + ../../opensbi/lib/sbi/sbi_illegal_insn.c
> > + ../../opensbi/lib/sbi/sbi_init.c
> > + ../../opensbi/lib/sbi/sbi_ipi.c
> > + ../../opensbi/lib/sbi/sbi_misaligned_ldst.c
> > + ../../opensbi/lib/sbi/sbi_scratch.c
> > + ../../opensbi/lib/sbi/sbi_string.c
> > + ../../opensbi/lib/sbi/sbi_system.c
> > + ../../opensbi/lib/sbi/sbi_timer.c
> > + ../../opensbi/lib/sbi/sbi_tlb.c
> > + ../../opensbi/lib/sbi/sbi_trap.c
> > + ../../opensbi/lib/utils/sys/clint.c
> > + ../../opensbi/lib/utils/irqchip/plic.c
> > + ../../opensbi/lib/utils/serial/sifive-uart.c
> > + ../../opensbi/lib/utils/serial/uart8250.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + PcdLib
> > + RiscVCpuLib
> > +
> > --
> > 2.7.4
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library
2019-09-30 18:31 ` [edk2-devel] " Leif Lindholm
@ 2019-10-15 2:32 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 2:32 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, October 1, 2019 2:31 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 15/29]
> RiscVPkg/Library: RISC-V CPU library
>
> On Mon, Sep 23, 2019 at 08:31:41AM +0800, Abner Chang wrote:
> > This library provides CSR assembly functions to read/write RISC-V
> > specific Control and Status registers.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++
> > RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115
> +++++++++++++++++++++++++++
> > RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++
>
> Please ensure you have set up an orderfile, as described on
> https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-
> unkempt-git-guide-for-edk2-contributors-and-maintainers
> or by executing BaseTools/Scripts/SetupGit.py inside each repository.
>
> > 3 files changed, 217 insertions(+)
> > create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
> > create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
> > create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> >
> > diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h
> > b/RiscVPkg/Include/Library/RiscVCpuLib.h
> > new file mode 100644
> > index 0000000..c84d599
> > --- /dev/null
> > +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h
> > @@ -0,0 +1,68 @@
> > +/** @file
> > + RISC-V CPU library definitions.
> > +
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/
> > +
> > +#ifndef _RISCV_CPU_LIB_H_
> > +#define _RISCV_CPU_LIB_H_
>
> Please drop leading _.
>
> > +
> > +#include "RiscV.h"
>
> Hmm. This raises two concerns.
> First - style-wise, "" should not be used for anything but local (same
> directory) include files.
> Secondly, there are two separate files called RiscV.h introduced by this patch
> series:
> RiscVPkg/Include/IndustryStandard/RiscV.h
> RiscVPkg/Include/RiscV.h
> Have these been split solely in order to have one directly includable in
> assembler?
>
> If so, please merge them (in the IndustryStandard one), and put the C-
> specific bits inside an #ifndef __ASSEMBLY__ statement.
> If not, please provide a description of their logical split, and rename one of
> them.
I have same concerns of the same naming as well.
Actually one is for RISC-V industrial standard, another one is the definitions of EDK2 RISC-V implementation. I will name the last one to RiscVImpl.h.
>
> > +
> > +/**
> > + RISCV_TRAP_HANDLER
> > +**/
> > +typedef
> > +VOID
> > +(EFIAPI *RISCV_TRAP_HANDLER)(
> > + VOID
> > + );
> > +
> > +VOID
> > +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
>
> Please keep all names referring to architectural registers identifiable. A quick
> Internet search suggests this may mean Machine Scratch Register?
>
> > +
> > +UINT32
> > +RiscVGetScratch (VOID);
> > +
> > +UINT32
> > +RiscVGetTrapCause (VOID);
> > +
> > +UINT64
> > +RiscVReadMachineTimer (VOID);
> > +
> > +VOID
> > +RiscVSetMachineTimerCmp (UINT64);
>
> Cmp neds expanding to its full name.
>
> > +
> > +UINT64
> > +RiscVReadMachineTimerCmp(VOID);
> > +
> > +UINT64
> > +RiscVReadMachineIE(VOID);
> > +
> > +UINT64
> > +RiscVReadMachineIP(VOID);
>
> IE/IP needs expanding, unless these are the names used in the architecture
> reference. If it is, this file needs those terms introduced in a glossary section
> at the start of this file.
>
> > +
> > +UINT64
> > +RiscVReadMachineStatus(VOID);
> > +
> > +VOID
> > +RiscVWriteMachineStatus(UINT64);
> > +
> > +UINT64
> > +RiscVReadMachineTvec(VOID);
> > +
> > +UINT64
> > +RiscVReadMisa (VOID);
>
> Tvec/Misa need the same treatment as IE/IP.
> If the M stands for Machine, it should be written out fully, and likely isa
> should be Isa.
>
> > +
> > +UINT64
> > +RiscVReadMVendorId (VOID);
> > +
> > +UINT64
> > +RiscVReadMArchId (VOID);
> > +
> > +UINT64
> > +RiscVReadMImplId (VOID);
>
> Impl needs expanding - I can't tell whether that means Implementation or
> Implmenter.
> For all 3 above, is that M only an abbreviated Machine? If so, please write it
> out fully.
>
> > +
> > +#endif
> > diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> > b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> > new file mode 100644
> > index 0000000..f372397
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> > @@ -0,0 +1,115 @@
> > +//-------------------------------------------------------------------
> > +-----------
> > +//
> > +// RISC-V CPU functions.
> > +//
> > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> // // SPDX-License-Identifier:
> > +BSD-2-Clause-Patent //
> > +//-------------------------------------------------------------------
> > +-----------
> > +#include <Base.h>
> > +#include <RiscV.h>
> > +
> > +.data
> > +
> > +.text
> > +.align 3
> > +
> > +.global ASM_PFX(RiscVSetScratch)
> > +.global ASM_PFX(RiscVGetScratch)
> > +.global ASM_PFX(RiscVGetMachineTrapCause) .global
> > +ASM_PFX(RiscVReadMachineIE) .global ASM_PFX(RiscVReadMachineIP)
> > +.global ASM_PFX(RiscVReadMachineStatus) .global
> > +ASM_PFX(RiscVWriteMachineStatus) .global
> > +ASM_PFX(RiscVReadMachineTvec) .global
> ASM_PFX(RiscVReadMisa) .global
> > +ASM_PFX(RiscVReadMVendorId) .global
> ASM_PFX(RiscVReadMArchId) .global
> > +ASM_PFX(RiscVReadMImplId)
>
> This could get a lot neater if you replicate what we have for the
> ARM/AARCH64 ports and implement an ASM_FUNC macro that does both
> the global, and the prefix (and some more stuff that is less imortant now we
> use lto anyway).
>
> Have a look in ArmPkg/Include/AsmMacroIoLib*.h
>
> > +//
> > +// Set machine mode scratch.
> > +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
> > +//
> > +ASM_PFX (RiscVSetScratch):
> > + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
> > + ret
> > +
> > +//
> > +// Get machine mode scratch.
> > +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
> > +//
> > +ASM_PFX (RiscVGetScratch):
> > + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
> > + ret
> > +
> > +//
> > +// Get machine trap cause CSR.
> > +//
> > +ASM_PFX (RiscVGetMachineTrapCause):
> > + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
> > + ret
> > +
> > +//
> > +// Get machine interrupt enable
> > +//
> > +ASM_PFX (RiscVReadMachineIE):
> > + csrr a0, RISCV_CSR_MACHINE_MIE
> > + ret
> > +
> > +//
> > +// Get machine interrupt pending
> > +//
> > +ASM_PFX (RiscVReadMachineIP):
> > + csrr a0, RISCV_CSR_MACHINE_MIP
> > + ret
> > +
> > +//
> > +// Get machine status
> > +//
> > +ASM_PFX(RiscVReadMachineStatus):
> > + csrr a0, RISCV_CSR_MACHINE_MSTATUS
> > + ret
> > +
> > +//
> > +// Set machine status
> > +//
> > +ASM_PFX(RiscVWriteMachineStatus):
> > + csrw RISCV_CSR_MACHINE_MSTATUS, a0
> > + ret
> > +
> > +//
> > +// Get machine trap vector
> > +//
> > +ASM_PFX(RiscVReadMachineTvec):
> > + csrr a0, RISCV_CSR_MACHINE_MTVEC
> > + ret
> > +
> > +//
> > +// Read machine ISA
> > +//
> > +ASM_PFX(RiscVReadMisa):
> > + csrr a0, RISCV_CSR_MACHINE_MISA
> > + ret
> > +
> > +//
> > +// Read machine vendor ID
> > +//
> > +ASM_PFX(RiscVReadMVendorId):
> > + csrr a0, RISCV_CSR_MACHINE_MVENDORID
> > + ret
> > +
> > +//
> > +// Read machine architecture ID
> > +//
> > +ASM_PFX(RiscVReadMArchId):
> > + csrr a0, RISCV_CSR_MACHINE_MARCHID
> > + ret
> > +
> > +//
> > +// Read machine implementation ID
> > +//
> > +ASM_PFX(RiscVReadMImplId):
> > + csrr a0, RISCV_CSR_MACHINE_MIMPID
> > + ret
> > +
> > diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> > b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> > new file mode 100644
> > index 0000000..fc9131b
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> > @@ -0,0 +1,34 @@
> > +## @file
> > +# RISC-V RV64 CPU library
> > +#
> > +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
> > +LP. All rights reserved.<BR> # # SPDX-License-Identifier:
> > +BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVCpuLib
> > + FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVCpuLib
> > +
> > +#
> > +# The following information is for reference only and not required by the
> build tools.
> > +#
> > +# VALID_ARCHITECTURES = RISCV64
> > +#
> > +
> > +[Sources]
> > +
> > +[Sources.RISCV64]
> > + Cpu.S
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + MdeModulePkg/MdeModulePkg.dec
>
> Please sort the above two alphabetically.
>
> /
> Leif
>
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +
> > --
> > 2.7.4
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-09-26 23:46 ` [edk2-devel] " Leif Lindholm
@ 2019-10-15 4:02 ` Abner Chang
2019-10-15 10:31 ` Leif Lindholm
[not found] ` <15CDB6324F411B37.30896@groups.io>
1 sibling, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-15 4:02 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, September 27, 2019 7:46 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
>
> On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > Support RISC-V image relocation.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> +++++++++++++++++++++
> > 5 files changed, 152 insertions(+), 1 deletion(-) create mode 100644
> > MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> >
> > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > index 07bb62f..97e0ff4 100644
> > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > @@ -1,6 +1,6 @@
> > /** @file
> > Base PE/COFF loader supports loading any PE32/PE32+ or TE image,
> > but
> > - only supports relocating IA32, x64, IPF, and EBC images.
> > + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
> >
> > Caution: This file requires additional review when modified.
> > This library will have external input - PE/COFF image.
> > @@ -17,6 +17,7 @@
> >
> > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > reserved.<BR>
> > + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development
> > + LP. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > index 395c140..b190494 100644
> > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > @@ -3,6 +3,7 @@
> > # The IPF version library supports loading IPF and EBC PE/COFF image.
> > # The IA32 version library support loading IA32, X64 and EBC PE/COFF
> images.
> > # The X64 version library support loading IA32, X64 and EBC PE/COFF
> images.
> > +# The RISC-V version library support loading RISC-V images.
> > #
> > # Caution: This module requires additional review when modified.
> > # This library will have external input - PE/COFF image.
> > @@ -11,6 +12,7 @@
> > #
> > # Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All
> > rights reserved.<BR>
> > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR>
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@
> > [Sources.ARM]
> > Arm/PeCoffLoaderEx.c
> >
> > +[Sources.RISCV64]
> > + RiscV/PeCoffLoaderEx.c
> > +
> > [Packages]
> > MdePkg/MdePkg.dec
> >
> > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > index b0ea702..8616ca3 100644
> > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > @@ -4,6 +4,7 @@
> > // The IPF version library supports loading IPF and EBC PE/COFF image.
> > // The IA32 version library support loading IA32, X64 and EBC PE/COFF
> images.
> > // The X64 version library support loading IA32, X64 and EBC PE/COFF
> images.
> > +// The RISC-V version library support loading RISC-V32 and RISC-V64
> PE/COFF images.
> > //
> > // Caution: This module requires additional review when modified.
> > // This library will have external input - PE/COFF image.
> > @@ -12,6 +13,7 @@
> > //
> > // Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > reserved.<BR> // Portions copyright (c) 2008 - 2009, Apple Inc. All
> > rights reserved.<BR>
> > +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR>
> > //
> > // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git
> > a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > index b74277f..9c33703 100644
> > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > @@ -2,6 +2,7 @@
> > Declaration of internal functions in PE/COFF Lib.
> >
> > Copyright (c) 2006 - 2010, Intel Corporation. All rights
> > reserved.<BR>
> > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
>
> You only get to add copyright when you otherwise modify the file :)
>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > new file mode 100644
> > index 0000000..8eb37f9
> > --- /dev/null
> > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > @@ -0,0 +1,142 @@
> > +/** @file
> > + PE/Coff loader for RISC-V PE image
> > +
> > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR>
> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > +"BasePeCoffLibInternals.h"
> > +#include <Library/BaseLib.h>
> > +
> > +//
> > +// RISC-V definition.
> > +//
> > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> (1LL<<RISCV_IMM_BITS)
> > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
>
> This looked familiar, so I had a look.
> This block is copied around - it exists in:
> - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> - BaseTools/Source/C/GenFw/Elf64Convert.c
> - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
>
> This needs to be moved somewhere central and included elsewhere.
> BaseTools and MdePkg unfortunately duplicate a lot of stuff, but this still
> belongs in a common header file for either.
I can consolidate that macro in two files under BaseTools, but not consolidating macro in files in both MdePkg and BaseTools. BaseTools and edk2 are two separate projects and could be built individually based on my understanding.
I have no idea how to leverage one header file from both projects and I don't go that far to address it.
>
> > +
> > +/**
> > + Performs an RISC-V specific relocation fixup and is a no-op on
> > + other instruction sets.
> > + RISC-V splits 32-bit fixup into 20bit and 12-bit with two
> > +relocation
> > + types. We have to know the lower 12-bit fixup first then we can
> > +deal
> > + carry over on high 20-bit fixup. So we log the high 20-bit in
> > + FixupData.
> > +
> > + @param Reloc The pointer to the relocation record.
> > + @param Fixup The pointer to the address to fix up.
> > + @param FixupData The pointer to a buffer to log the fixups.
> > + @param Adjust The offset to adjust the fixup.
> > +
> > + @return Status code.
> > +
> > +**/
> > +RETURN_STATUS
> > +PeCoffLoaderRelocateImageEx (
> > + IN UINT16 *Reloc,
> > + IN OUT CHAR8 *Fixup,
> > + IN OUT CHAR8 **FixupData,
> > + IN UINT64 Adjust
> > + )
> > +{
> > + UINT32 Value;
> > + UINT32 Value2;
> > + UINT32 *RiscVHi20Fixup;
> > +
> > + switch ((*Reloc) >> 12) {
> > + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> > + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
> > + break;
> > +
> > + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> > + if (RiscVHi20Fixup != NULL) {
> > +
> > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value += (UINT32)Adjust;
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
> > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
> > + (RV_X (*(UINT32 *)Fixup, 0, 20));
> > + }
> > + break;
> > +
> > + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> > + if (RiscVHi20Fixup != NULL) {
> > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32
> *)Fixup, 25, 7) << 5));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value += (UINT32)Adjust;
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> > + Value &= RISCV_IMM_REACH - 1;
> > + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |
> (RV_X(Value, 5, 7) << 25)));
> > + }
> > + break;
> > +
> > + default:
> > + return RETURN_UNSUPPORTED;
> > +
> > + }
> > + return RETURN_SUCCESS;
> > +}
> > +
> > +/**
> > + Returns TRUE if the machine type of PE/COFF image is supported.
> > +Supported
> > + does not mean the image can be executed it means the PE/COFF loader
> > +supports
> > + loading and relocating of the image type. It's up to the caller to
> > +support
> > + the entry point.
> > +
> > + @param Machine Machine type from the PE Header.
> > +
> > + @return TRUE if this PE/COFF loader can load the image
> > +
> > +**/
> > +BOOLEAN
> > +PeCoffLoaderImageFormatSupported (
> > + IN UINT16 Machine
> > + )
> > +{
> > + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine ==
> > +IMAGE_FILE_MACHINE_RISCV64)) {
>
> RISCV32 is not supported by this set.
>
> /
> Leif
>
> > + return TRUE;
> > + }
> > +
> > + return FALSE;
> > +}
> > +
> > +/**
> > + Performs an Itanium-based specific re-relocation fixup and is a
> > +no-op on other
> > + instruction sets. This is used to re-relocated the image into the
> > +EFI virtual
> > + space for runtime calls.
> > +
> > + @param Reloc The pointer to the relocation record.
> > + @param Fixup The pointer to the address to fix up.
> > + @param FixupData The pointer to a buffer to log the fixups.
> > + @param Adjust The offset to adjust the fixup.
> > +
> > + @return Status code.
> > +
> > +**/
> > +RETURN_STATUS
> > +PeHotRelocateImageEx (
> > + IN UINT16 *Reloc,
> > + IN OUT CHAR8 *Fixup,
> > + IN OUT CHAR8 **FixupData,
> > + IN UINT64 Adjust
> > + )
> > +{
> > + return RETURN_UNSUPPORTED;
> > +}
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
[not found] ` <15CDB6324F411B37.30896@groups.io>
@ 2019-10-15 4:26 ` Abner Chang
2019-10-15 10:41 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-15 4:26 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist),
leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Tuesday, October 15, 2019 12:03 PM
> To: devel@edk2.groups.io; leif.lindholm@linaro.org
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
>
>
>
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, September 27, 2019 7:46 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> >
> > On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > > Support RISC-V image relocation.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> > +++++++++++++++++++++
> > > 5 files changed, 152 insertions(+), 1 deletion(-) create mode
> > > 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > >
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > index 07bb62f..97e0ff4 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > @@ -1,6 +1,6 @@
> > > /** @file
> > > Base PE/COFF loader supports loading any PE32/PE32+ or TE image,
> > > but
> > > - only supports relocating IA32, x64, IPF, and EBC images.
> > > + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
> > >
> > > Caution: This file requires additional review when modified.
> > > This library will have external input - PE/COFF image.
> > > @@ -17,6 +17,7 @@
> > >
> > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > > Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > > reserved.<BR>
> > > + Portions Copyright (c) 2016, Hewlett Packard Enterprise
> > > + Development LP. All rights reserved.<BR>
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > **/
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > index 395c140..b190494 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > @@ -3,6 +3,7 @@
> > > # The IPF version library supports loading IPF and EBC PE/COFF image.
> > > # The IA32 version library support loading IA32, X64 and EBC
> > > PE/COFF
> > images.
> > > # The X64 version library support loading IA32, X64 and EBC
> > > PE/COFF
> > images.
> > > +# The RISC-V version library support loading RISC-V images.
> > > #
> > > # Caution: This module requires additional review when modified.
> > > # This library will have external input - PE/COFF image.
> > > @@ -11,6 +12,7 @@
> > > #
> > > # Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All
> > > rights reserved.<BR>
> > > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > +All rights reserved.<BR>
> > > #
> > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9
> > > @@ [Sources.ARM]
> > > Arm/PeCoffLoaderEx.c
> > >
> > > +[Sources.RISCV64]
> > > + RiscV/PeCoffLoaderEx.c
> > > +
> > > [Packages]
> > > MdePkg/MdePkg.dec
> > >
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > index b0ea702..8616ca3 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > @@ -4,6 +4,7 @@
> > > // The IPF version library supports loading IPF and EBC PE/COFF image.
> > > // The IA32 version library support loading IA32, X64 and EBC
> > > PE/COFF
> > images.
> > > // The X64 version library support loading IA32, X64 and EBC
> > > PE/COFF
> > images.
> > > +// The RISC-V version library support loading RISC-V32 and RISC-V64
> > PE/COFF images.
> > > //
> > > // Caution: This module requires additional review when modified.
> > > // This library will have external input - PE/COFF image.
> > > @@ -12,6 +13,7 @@
> > > //
> > > // Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > reserved.<BR> // Portions copyright (c) 2008 - 2009, Apple Inc. All
> > > rights reserved.<BR>
> > > +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > +All rights reserved.<BR>
> > > //
> > > // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git
> > > a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > index b74277f..9c33703 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > @@ -2,6 +2,7 @@
> > > Declaration of internal functions in PE/COFF Lib.
> > >
> > > Copyright (c) 2006 - 2010, Intel Corporation. All rights
> > > reserved.<BR>
> > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > + All rights reserved.<BR>
> >
> > You only get to add copyright when you otherwise modify the file :)
> >
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > **/
> > > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > new file mode 100644
> > > index 0000000..8eb37f9
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > @@ -0,0 +1,142 @@
> > > +/** @file
> > > + PE/Coff loader for RISC-V PE image
> > > +
> > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > +All rights reserved.<BR>
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > > +"BasePeCoffLibInternals.h"
> > > +#include <Library/BaseLib.h>
> > > +
> > > +//
> > > +// RISC-V definition.
> > > +//
> > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> > (1LL<<RISCV_IMM_BITS)
> > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> >
> > This looked familiar, so I had a look.
> > This block is copied around - it exists in:
> > - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > - BaseTools/Source/C/GenFw/Elf64Convert.c
> > - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> >
> > This needs to be moved somewhere central and included elsewhere.
> > BaseTools and MdePkg unfortunately duplicate a lot of stuff, but this
> > still belongs in a common header file for either.
>
> I can consolidate that macro in two files under BaseTools, but not
> consolidating macro in files in both MdePkg and BaseTools. BaseTools and
> edk2 are two separate projects and could be built individually based on my
> understanding.
> I have no idea how to leverage one header file from both projects and I don't
> go that far to address it.
Leif, seem there is no good place and the existing header file to put this macro unless I create a new header file under BaseTools/Source/C/Include. I would like to keep this duplicate macro in both files rather than create an header file in which only define this macro. Do you have good idea?
>
> >
> > > +
> > > +/**
> > > + Performs an RISC-V specific relocation fixup and is a no-op on
> > > + other instruction sets.
> > > + RISC-V splits 32-bit fixup into 20bit and 12-bit with two
> > > +relocation
> > > + types. We have to know the lower 12-bit fixup first then we can
> > > +deal
> > > + carry over on high 20-bit fixup. So we log the high 20-bit in
> > > + FixupData.
> > > +
> > > + @param Reloc The pointer to the relocation record.
> > > + @param Fixup The pointer to the address to fix up.
> > > + @param FixupData The pointer to a buffer to log the fixups.
> > > + @param Adjust The offset to adjust the fixup.
> > > +
> > > + @return Status code.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +PeCoffLoaderRelocateImageEx (
> > > + IN UINT16 *Reloc,
> > > + IN OUT CHAR8 *Fixup,
> > > + IN OUT CHAR8 **FixupData,
> > > + IN UINT64 Adjust
> > > + )
> > > +{
> > > + UINT32 Value;
> > > + UINT32 Value2;
> > > + UINT32 *RiscVHi20Fixup;
> > > +
> > > + switch ((*Reloc) >> 12) {
> > > + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> > > + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
> > > + break;
> > > +
> > > + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> > > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> > > + if (RiscVHi20Fixup != NULL) {
> > > +
> > > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> > > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > > + Value2 |= ~(RISCV_IMM_REACH-1);
> > > + }
> > > + Value += Value2;
> > > + Value += (UINT32)Adjust;
> > > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
> > > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > > + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
> > > + (RV_X (*(UINT32 *)Fixup, 0, 20));
> > > + }
> > > + break;
> > > +
> > > + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> > > + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
> > > + if (RiscVHi20Fixup != NULL) {
> > > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) |
> > > + (RV_X(*(UINT32
> > *)Fixup, 25, 7) << 5));
> > > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > > + Value2 |= ~(RISCV_IMM_REACH-1);
> > > + }
> > > + Value += Value2;
> > > + Value += (UINT32)Adjust;
> > > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> > > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > > + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> > > + Value &= RISCV_IMM_REACH - 1;
> > > + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) <<
> > > + 7) |
> > (RV_X(Value, 5, 7) << 25)));
> > > + }
> > > + break;
> > > +
> > > + default:
> > > + return RETURN_UNSUPPORTED;
> > > +
> > > + }
> > > + return RETURN_SUCCESS;
> > > +}
> > > +
> > > +/**
> > > + Returns TRUE if the machine type of PE/COFF image is supported.
> > > +Supported
> > > + does not mean the image can be executed it means the PE/COFF
> > > +loader supports
> > > + loading and relocating of the image type. It's up to the caller
> > > +to support
> > > + the entry point.
> > > +
> > > + @param Machine Machine type from the PE Header.
> > > +
> > > + @return TRUE if this PE/COFF loader can load the image
> > > +
> > > +**/
> > > +BOOLEAN
> > > +PeCoffLoaderImageFormatSupported (
> > > + IN UINT16 Machine
> > > + )
> > > +{
> > > + if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine ==
> > > +IMAGE_FILE_MACHINE_RISCV64)) {
> >
> > RISCV32 is not supported by this set.
> >
> > /
> > Leif
> >
> > > + return TRUE;
> > > + }
> > > +
> > > + return FALSE;
> > > +}
> > > +
> > > +/**
> > > + Performs an Itanium-based specific re-relocation fixup and is a
> > > +no-op on other
> > > + instruction sets. This is used to re-relocated the image into the
> > > +EFI virtual
> > > + space for runtime calls.
> > > +
> > > + @param Reloc The pointer to the relocation record.
> > > + @param Fixup The pointer to the address to fix up.
> > > + @param FixupData The pointer to a buffer to log the fixups.
> > > + @param Adjust The offset to adjust the fixup.
> > > +
> > > + @return Status code.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +PeHotRelocateImageEx (
> > > + IN UINT16 *Reloc,
> > > + IN OUT CHAR8 *Fixup,
> > > + IN OUT CHAR8 **FixupData,
> > > + IN UINT64 Adjust
> > > + )
> > > +{
> > > + return RETURN_UNSUPPORTED;
> > > +}
> > > --
> > > 2.7.4
> > >
> > >
> > >
> > >
> >
> >
>
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-09-26 22:09 ` [edk2-devel] " Leif Lindholm
@ 2019-10-15 6:18 ` Abner Chang
2019-10-15 10:56 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-15 6:18 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, September 27, 2019 6:10 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> BaseTools: BaseTools changes for RISC-V platform.
>
> On Mon, Sep 23, 2019 at 08:31:50AM +0800, Abner Chang wrote:
> > BaseTools changes for building EDK2 RISC-V platform.
> > The changes made to build_rule.template is to avoid build errors
> > cause by GCC711RISCV tool chain.
>
> Thank you, this is much cleaner.
> There are however some issues in this patch that prevent building on
> any platform. Please ensure to give a local build test before
> submitting a 3.
>
> First of all, this still does not contain the addition to
> BaseTools/Source/Python/Common/buildoptions.py that I mentioned in
> INVALID URI REMOVED
> 3A__edk2.groups.io_g_devel_message_47036&d=DwIBAg&c=C5b8zRQO1mi
> GmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=
> YclXVT-
> dumczX_RwFNv_GDdWAp1gvJXUN0KRfNaGEtw&s=Gp1kHhT9Z6PR93PmPN
> ZD-_0h0rPDXLsODbhLWyQs8NA&e= - meaning that attempting
> to build anything for RISCV64 gives an error.
I thought you were saying to use ENV(GCC5_RISCV64_PREFIX) to point to build tool binaries, no?
>
> Other minor issues reviewed inline:
>
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > BaseTools/Conf/build_rule.template | 62 ++---
> > BaseTools/Conf/tools_def.template | 64 ++++-
> > BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
> > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> > BaseTools/Source/C/GenFw/Elf64Convert.c | 260
> ++++++++++++++++++++-
> > BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> > .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> > BaseTools/Source/Python/Common/DataType.py | 7 +-
> > 10 files changed, 659 insertions(+), 45 deletions(-)
> >
> > diff --git a/BaseTools/Conf/build_rule.template
> b/BaseTools/Conf/build_rule.template
> > index db06d3a..fab3926 100755
> > --- a/BaseTools/Conf/build_rule.template
> > +++ b/BaseTools/Conf/build_rule.template
> > @@ -1,6 +1,7 @@
> > #
> > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> > # Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> > +# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development
> LP. All rights reserved.<BR>
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> >
> > @@ -145,14 +146,6 @@
> > <Command.GCC, Command.RVCT>
> > "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src}
> >
> > -[C-Header-File]
> > - <InputFile>
> > - *.h, *.H
> > -
> > - <OutputFile>
> > -
> > - <Command>
> > -
>
> Header files are good, please don't delete them.
>
> > [Assembly-Code-File.COMMON.COMMON]
> > <InputFile.MSFT, InputFile.INTEL, InputFile.RVCT>
> > ?.asm, ?.Asm, ?.ASM
> > @@ -266,10 +259,10 @@
> > <Command.GCC>
> > $(RM) ${dst}
> > "$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST)
> > -
> > +
>
> Please address these line ending issues..
>
> > <Command.RVCT>
> > "$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST)
> > -
> > +
> > <Command.RVCTCYGWIN>
> > # $(OBJECT_FILES_LIST) has wrong paths for cygwin
> > "$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES)
> > @@ -304,8 +297,8 @@
> >
> > <Command.XCODE>
> > "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist
> $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> > -
> > -
> > +
> > +
> > [Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64,
> Static-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-
> File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM]
> > <InputFile>
> > *.lib
> > @@ -321,6 +314,21 @@
> > "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> >
> >
> > +[Static-Library-File.COMMON.RISCV64, Static-Library-
> File.COMMON.RISCV32]
> > + <InputFile>
> > + *.lib
> > +
> > + <ExtraDependency>
> > + $(MAKE_FILE)
> > +
> > + <OutputFile>
> > + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> > +
> > + <Command.GCC>
> > + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH)
> @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
>
> This line looks to me like the only thing that is actually changed
> here, and I am not convinced it is necessary.
> "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
> group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
> $(DLINK2_FLAGS)
>
> On the ARM/AARCH64 side, we use gcc as the DLINK, and pass the
> required flags through to the linker with -Wl. Please have a look and
> try to rework at that end rather than fundamentally revamping the
> basic build rules differently for RISCV than other architectures.
>
> Basically, please discard all changes to this file, apply the below
> diff, and rework the flags to resolve the builds. (Basically, add a
> bunch of -Wl,)
I got build error when use -Wl with the specific version of RISC-V GCC toolchain (the old and workable one). I will revisit this when I investigate the issue caused by latest RISC-V build tool.
>
> diff --git a/BaseTools/Conf/tools_def.template
> b/BaseTools/Conf/tools_def.template
> index b96b394dc441..b6d5c25ba5b5 100755
> --- a/BaseTools/Conf/tools_def.template
> +++ b/BaseTools/Conf/tools_def.template
> @@ -2286,11 +2286,10 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z
> common-page-size=0x20
> ##################
> # GCC5 RISCV64 definitions
> ##################
> -*_GCC5_RISCV64_OBJCOPY_PATH =
> ENV(GCC5_RISCV64_PREFIX)objcopy
> *_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> -*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
> -*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> -*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> +*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ar
> +*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> +*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> *_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> *_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> *_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
>
>
> > + "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> > +
> > +
> > [Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION]
> > <InputFile>
> > *.lib
> > @@ -346,8 +354,8 @@
> >
> > <Command.XCODE>
> > "$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist
> $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> > -
> > -
> > +
> > +
> > [Dynamic-Library-File]
> > <InputFile>
> > ?.dll
> > @@ -360,7 +368,7 @@
> > $(CP) ${dst} $(DEBUG_DIR)
> > $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> > -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> > - -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> > + -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> > <Command.GCC>
> > $(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
> > $(OBJCOPY) --strip-unneeded -R .eh_frame ${src}
> > @@ -375,7 +383,7 @@
> > $(CP) ${dst} $(DEBUG_DIR)
> > $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> > -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> > -
> > +
> > <Command.XCODE>
> > # tool to convert Mach-O to PE/COFF
> > "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src}
> $(DEBUG_DIR)(+)$(MODULE_NAME).pecoff
> > @@ -414,13 +422,13 @@
> > <Command.MSFT, Command.INTEL>
> > Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST)
> ${src}
> > "$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path}
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i >
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst}
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> >
> > <Command.GCC>
> > Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST)
> ${src}
> > "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path}
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i >
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> > "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst}
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
> >
> > [C-Code-File.AcpiTable]
> > @@ -462,14 +470,14 @@
> > "$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> $(CC_FLAGS) $(ASLCC_FLAGS) $(INC) ${src}
> > "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll
> $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> > "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll
> $(GENFW_FLAGS)
> > -
> > - <Command.XCODE>
> > +
> > + <Command.XCODE>
> > "$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> $(ASLCC_FLAGS) $(INC) ${src}
> > "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll
> $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> > "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS)
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff
> > "$(GENFW)" -o ${dst} -c
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff $(GENFW_FLAGS)
> > -
> > -
> > +
> > +
> > [Masm16-Code-File]
> > <InputFile>
> > ?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16
> > @@ -492,14 +500,14 @@
> > Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> > "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS)
> $(INC) ${d_path}(+)${s_base}.iii
> > "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH)
> $(LIBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group
> > -
> > +
> > <Command.XCODE>
> > "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
> > Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> > "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS)
> $(INC) ${d_path}(+)${s_base}.iii
> > "$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib
> $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> > otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${dst}
> > -
> > +
> >
> > [Nasm-to-Binary-Code-File]
> > <InputFile>
> > @@ -635,8 +643,8 @@
> > <Command.GCC>
> > "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g
> $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
> $(GENFW_FLAGS)
> > "$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
> > -
> > +
> > <Command.XCODE, Command.RVCT>
> > GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g
> $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
> > -
> > -
> > +
> > +
> > diff --git a/BaseTools/Conf/tools_def.template
> b/BaseTools/Conf/tools_def.template
> > index 8f0e6cb..54c3dc5 100755
> > --- a/BaseTools/Conf/tools_def.template
> > +++ b/BaseTools/Conf/tools_def.template
> > @@ -3,7 +3,7 @@
> > # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> > # Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
> > # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
> > -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> > +# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development
> LP<BR>
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> > @@ -231,11 +231,12 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
> > # Intel(r) ACPI Compiler from
> > # https://acpica.org/downloads
> > # GCC5 -Linux,Windows- Requires:
> > -# GCC 5 with LTO support, targeting x86_64-linux-gnu,
> aarch64-linux-gnu, or arm-linux-gnueabi
> > +# GCC 5 with LTO support, targeting x86_64-linux-gnu,
> aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
> > # Optional:
> > # Required to build platforms or ACPI tables:
> > # Intel(r) ACPI Compiler from
> > # https://acpica.org/downloads
> > +#
> > # CLANG35 -Linux,Windows- Requires:
> > # Clang v3.5 or later, and GNU binutils targeting aarch64-
> linux-gnu or arm-linux-gnueabi
> > # Optional:
> > @@ -1735,6 +1736,7 @@ DEFINE GCC_IA32_RC_FLAGS = -I binary -O
> elf32-i386 -B i386
> > DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --
> rename-section .data=.hii
> > DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm
> --rename-section .data=.hii
> > DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B
> aarch64 --rename-section .data=.hii
> > +DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv - B
> riscv64 --rename-section .data=.hii
>
> The above line requires two changes in order to work. The first one is
> the two spaces between the - and the B. The second is that "riscv64"
> is not accepted by the toolchain. "riscv" works.
>
> >
> > DEFINE GCC48_ALL_CC_FLAGS = -g -fshort-wchar -fno-builtin -fno-
> strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-
> sections -include AutoGen.h -fno-common -
> DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
> > DEFINE GCC48_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-n,-q,--gc-
> sections -z common-page-size=0x20
> > @@ -1806,6 +1808,21 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS =
> DEF(GCC49_ARM_ASLDLINK_FLAGS)
> > DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =
> DEF(GCC49_AARCH64_ASLDLINK_FLAGS)
> > DEFINE GCC5_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -fno-lto
> >
> > +DEFINE GCC5_RISCV_ALL_CC_FLAGS = -g -fshort-wchar -fno-
> strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-
> sections -c -include AutoGen.h -fno-common -
> DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
> > +DEFINE GCC5_RISCV_ALL_DLINK_COMMON = -nostdlib -n -q --gc-
> sections -z common-page-size=0x40
> > +DEFINE GCC5_RISCV_ALL_DLINK_FLAGS =
> DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -
> u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
> > +DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS = --
> defsym=PECOFF_HEADER_SIZE=0x220 --
> script=$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds
> > +DEFINE GCC5_RISCV_ALL_ASM_FLAGS = -c -x assembler -
> imacros $(DEST_DIR_DEBUG)/AutoGen.h
> > +DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-
> tautological-compare -Wno-pointer-compare
> > +
> > +DEFINE GCC5_RISCV64_ARCH = rv64imafdc
> > +DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =
> DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry ReferenceAcpiTable -u
> ReferenceAcpiTable
> > +DEFINE GCC5_RISCV32_RISCV64_DLINK_FLAGS =
> DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -
> u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
> > +DEFINE GCC5_RISCV64_CC_FLAGS =
> DEF(GCC5_RISCV_ALL_CC_FLAGS)
> DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) -
> march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-
> stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-
> unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64
> > +DEFINE GCC5_RISCV64_DLINK_FLAGS =
> DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -melf64lriscv --oformat=elf64-
> littleriscv --no-relax
> > +DEFINE GCC5_RISCV64_DLINK2_FLAGS =
> DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
> > +DEFINE GCC5_ASM_FLAGS =
> DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -
> mcmodel=medany -mabi=lp64
> > +
> >
> ##########################################################
> ##########################
> > #
> > # GCC 4.8 - This configuration is used to compile under Linux to produce
> > @@ -2247,6 +2264,49 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z
> common-page-size=0x20
> > NOOPT_GCC5_AARCH64_DLINK_FLAGS =
> DEF(GCC5_AARCH64_DLINK_FLAGS) -O0
> > NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
> -O0
> >
> >
> +#########################################################
> ##########################
> >
> +#########################################################
> ###########################
> > +#
> > +# GCC RISC-V This configuration is used to compile under Linux to produce
> > +# PE/COFF binaries using GCC RISC-V tool chain
> > +#
> >
> +#########################################################
> ###########################
> > +
> > +#*_GCC5_*_*_FAMILY = GCC
> > +
> > +#*_GCC5_*_MAKE_PATH = DEF(GCC49_IA32_PREFIX)make
> > +#*_GCC5_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
> > +#*_GCC5_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
> > +#*_GCC5_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> > +#*_GCC5_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
> > +#*_GCC5_*_APP_FLAGS =
> > +#*_GCC5_*_ASL_FLAGS = DEF(IASL_FLAGS)
> > +#*_GCC5_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
> > +
> > +##################
> > +# GCC5 RISCV64 definitions
> > +##################
> > +*_GCC5_RISCV64_OBJCOPY_PATH =
> ENV(GCC5_RISCV64_PREFIX)objcopy
> > +*_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
> > +*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> > +*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
> > +*_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_ASLCC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_ASLPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
> > +*_GCC5_RISCV64_RC_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
> > +
> > +*_GCC5_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> > +*_GCC5_RISCV64_ASLDLINK_FLAGS =
> DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
> > +*_GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS)
> > +*_GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) -
> save-temps
> > +*_GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV64_DLINK_FLAGS)
> > +*_GCC5_RISCV64_DLINK2_FLAGS =
> DEF(GCC5_RISCV64_DLINK2_FLAGS)
> > +*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
> > +*_GCC5_RISCV64_OBJCOPY_FLAGS =
> > +
> >
> ##########################################################
> ##########################
> > #
> > # CLANG35 - This configuration is used to compile under Linux to produce
> > diff --git a/BaseTools/Source/C/Common/BasePeCoff.c
> b/BaseTools/Source/C/Common/BasePeCoff.c
> > index e7566b3..640f7a1 100644
> > --- a/BaseTools/Source/C/Common/BasePeCoff.c
> > +++ b/BaseTools/Source/C/Common/BasePeCoff.c
> > @@ -4,6 +4,7 @@
> >
> > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage (
> > IN UINT64 Adjust
> > );
> >
> > +RETURN_STATUS
> > +PeCoffLoaderRelocateRiscVImage (
> > + IN UINT16 *Reloc,
> > + IN OUT CHAR8 *Fixup,
> > + IN OUT CHAR8 **FixupData,
> > + IN UINT64 Adjust
> > + );
> > +
> > STATIC
> > RETURN_STATUS
> > PeCoffLoaderGetPeHeader (
> > @@ -174,7 +183,8 @@ Returns:
> > ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
> > ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
> > ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
> > - ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
> > + ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
> > + ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
> > if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
> > //
> > // There are two types of ARM images. Pure ARM and ARM/Thumb.
> > @@ -802,6 +812,9 @@ Returns:
> > case EFI_IMAGE_MACHINE_ARMT:
> > Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData,
> Adjust);
> > break;
> > + case EFI_IMAGE_MACHINE_RISCV64:
> > + Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData,
> Adjust);
> > + break;
> > default:
> > Status = RETURN_UNSUPPORTED;
> > break;
> > diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > index e367836..36797d9 100644
> > --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > @@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups
> >
> > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > +Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All
> rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > --*/
> > @@ -61,6 +62,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #define IMM64_SIGN_INST_WORD_POS_X 27
> > #define IMM64_SIGN_VAL_POS_X 63
> >
> > +//
> > +// RISC-V definition.
> > +//
> > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> > +#define RISCV_IMM_BITS 12
> > +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > +
> > +UINT32 *RiscVHi20Fixup = NULL;
> > +
> > RETURN_STATUS
> > PeCoffLoaderRelocateIa32Image (
> > IN UINT16 *Reloc,
> > @@ -93,6 +105,89 @@ Returns:
> > return RETURN_UNSUPPORTED;
> > }
> >
> > +/*++
> > +
> > +Routine Description:
> > +
> > + Performs an RISC-V specific relocation fixup
> > +
> > +Arguments:
> > +
> > + Reloc - Pointer to the relocation record
> > +
> > + Fixup - Pointer to the address to fix up
> > +
> > + FixupData - Pointer to a buffer to log the fixups
> > +
> > + Adjust - The offset to adjust the fixup
> > +
> > +Returns:
> > +
> > + Status code
> > +
> > +--*/
> > +RETURN_STATUS
> > +PeCoffLoaderRelocateRiscVImage (
> > + IN UINT16 *Reloc,
> > + IN OUT CHAR8 *Fixup,
> > + IN OUT CHAR8 **FixupData,
> > + IN UINT64 Adjust
> > + )
> > +{
> > + UINT32 Value;
> > + UINT32 Value2;
> > + UINT32 OrgValue;
> > +
> > + OrgValue = *(UINT32 *) Fixup;
> > + OrgValue = OrgValue;
> > + switch ((*Reloc) >> 12) {
> > + case EFI_IMAGE_REL_BASED_RISCV_HI20:
> > + RiscVHi20Fixup = (UINT32 *) Fixup;
> > + break;
> > +
> > + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
> > + if (RiscVHi20Fixup != NULL) {
> > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value += (UINT32)Adjust;
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
> > + (RV_X (*(UINT32 *)Fixup, 0, 20));
> > + }
> > + RiscVHi20Fixup = NULL;
> > + break;
> > +
> > + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
> > + if (RiscVHi20Fixup != NULL) {
> > + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32
> *)Fixup, 25, 7) << 5));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value += (UINT32)Adjust;
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
> > + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
> > + Value2 = *(UINT32 *)Fixup & 0x01fff07f;
> > + Value &= RISCV_IMM_REACH - 1;
> > + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |
> (RV_X(Value, 5, 7) << 25)));
> > + }
> > + RiscVHi20Fixup = NULL;
> > + break;
> > +
> > + default:
> > + return EFI_UNSUPPORTED;
> > +
> > + }
> > + return RETURN_SUCCESS;
> > +}
> >
> > /**
> > Pass in a pointer to an ARM MOVT or MOVW immediate instruction and
> > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > index 908740d..fdbdd42 100644
> > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > @@ -4,6 +4,7 @@ This file contains the internal functions required to
> generate a Firmware Volume
> > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > Portions Copyright (c) 2016 HP Development Company, L.P.<BR>
> > +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000
> >
> > BOOLEAN mArm = FALSE;
> > +BOOLEAN mRiscV = FALSE;
> > STATIC UINT32 MaxFfsAlignment = 0;
> > BOOLEAN VtfFileFlag = FALSE;
> >
> > @@ -2274,6 +2276,104 @@ Returns:
> > }
> >
> > EFI_STATUS
> > +UpdateRiscvResetVectorIfNeeded (
> > + MEMORY_FILE *FvImage,
> > + FV_INFO *FvInfo
> > + )
> > +/*++
> > +
> > +Routine Description:
> > + This parses the FV looking for SEC and patches that address into the
> > + beginning of the FV header.
> > +
> > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > +
> > +Arguments:
> > + FvImage Memory file for the FV memory image/
> > + FvInfo Information read from INF file.
> > +
> > +Returns:
> > +
> > + EFI_SUCCESS Function Completed successfully.
> > + EFI_ABORTED Error encountered.
> > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > + EFI_NOT_FOUND PEI Core file not found.
> > +
> > +--*/
> > +{
> > + EFI_STATUS Status;
> > + UINT16 MachineType;
> > + EFI_FILE_SECTION_POINTER SecPe32;
> > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > +
> > + UINT32 bSecCore;
> > + UINT32 tmp;
> > +
> > +
> > + //
> > + // Verify input parameters
> > + //
> > + if (FvImage == NULL || FvInfo == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > + //
> > + // Initialize FV library
> > + //
> > + InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > +
> > + //
> > + // Find the Sec Core
> > + //
> > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > + if(EFI_ERROR(Status)) {
> > + printf("skip because Secutiry Core not found\n");
> > + return EFI_SUCCESS;
> > + }
> > +
> > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > +
> > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > + if(EFI_ERROR(Status)) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for
> SEC core.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + if (MachineType != EFI_IMAGE_MACHINE_RISCV64) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because
> Machine type is not RiscV.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> SecPe32, &SecCoreEntryAddress);
> > + if(EFI_ERROR(Status)) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point
> address for SEC Core.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long
> long) SecCoreEntryAddress);
> > + VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo-
> >BaseAddress);
> > + bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
> > + VerboseMsg("offset = 0x%llX", bSecCore);
> > +
> > + if(bSecCore > 0x0fffff) {
> > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of
> start of the FV");
> > + return EFI_ABORTED;
> > + }
> > +
> > + tmp = bSecCore;
> > + bSecCore = 0;
> > + //J-type
> > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > + bSecCore |= 0x6F; //JAL opcode
> > +
> > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +EFI_STATUS
> > GetPe32Info (
> > IN UINT8 *Pe32,
> > OUT UINT32 *EntryPoint,
> > @@ -2365,7 +2465,8 @@ Returns:
> > // Verify machine type is supported
> > //
> > if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType !=
> EFI_IMAGE_MACHINE_X64) && (*MachineType !=
> EFI_IMAGE_MACHINE_EBC) &&
> > - (*MachineType != EFI_IMAGE_MACHINE_ARMT) &&
> (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
> > + (*MachineType != EFI_IMAGE_MACHINE_ARMT) &&
> (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
> > + (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32
> file.");
> > return EFI_UNSUPPORTED;
> > }
> > @@ -2808,7 +2909,8 @@ Returns:
> > Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad file
> between the last file and the VTF file.");
> > goto Finish;
> > }
> > - if (!mArm) {
> > +
> > + if (!mArm && !mRiscV) {
> > //
> > // Update reset vector (SALE_ENTRY for IPF)
> > // Now for IA32 and IA64 platform, the fv which has bsf file must have
> the
> > @@ -2843,6 +2945,22 @@ Returns:
> > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT16));
> > }
> >
> > + if (mRiscV) {
> > + //
> > + // Update RISCV reset vector.
> > + //
> > + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> &mFvDataInfo);
> > + if (EFI_ERROR (Status)) {
> > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for
> RISC-V.");
> > + goto Finish;
> > + }
> > + //
> > + // Update Checksum for FvHeader
> > + //
> > + FvHeader->Checksum = 0;
> > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT16));
> > + }
> > +
> > //
> > // Update FV Alignment attribute to the largest alignment of all the FFS
> files in the FV
> > //
> > @@ -3430,6 +3548,10 @@ Returns:
> > mArm = TRUE;
> > }
> >
> > + if (ImageContext.Machine == EFI_IMAGE_MACHINE_RISCV64) {
> > + mRiscV = TRUE;
> > + }
> > +
> > //
> > // Keep Image Context for PE image in FV
> > //
> > @@ -3583,7 +3705,7 @@ Returns:
> > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > Status = PeCoffLoaderRelocateImage (&ImageContext);
> > if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of
> %s", FileName);
> > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of
> %s Status=%d", FileName, Status);
> > free ((VOID *) MemoryImagePointer);
> > return Status;
> > }
> > diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c
> b/BaseTools/Source/C/GenFw/Elf32Convert.c
> > index 46089ff..4095b7c 100644
> > --- a/BaseTools/Source/C/GenFw/Elf32Convert.c
> > +++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
> > @@ -3,6 +3,7 @@ Elf32 Convert solution
> >
> > Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
> > +Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -141,8 +142,8 @@ InitializeElf32 (
> > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or
> ET_DYN");
> > return FALSE;
> > }
> > - if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine ==
> EM_ARM))) {
> > - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or
> EM_ARM");
> > + if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine ==
> EM_ARM) || (mEhdr->e_machine == EM_RISCV))) {
> > + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32
> machine.");
> > return FALSE;
> > }
> > if (mEhdr->e_version != EV_CURRENT) {
> > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > index 3d6319c..2aa09fd 100644
> > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > @@ -3,6 +3,7 @@ Elf64 convert solution
> >
> > Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
> > +Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #include "ElfConvert.h"
> > #include "Elf64Convert.h"
> >
> > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> > +#define RISCV_IMM_BITS 12
> > +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > +
> > STATIC
> > VOID
> > ScanSections64 (
> > @@ -153,8 +160,8 @@ InitializeElf64 (
> > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or
> ET_DYN");
> > return FALSE;
> > }
> > - if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> EM_AARCH64))) {
> > - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or
> EM_AARCH64");
> > + if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
> > + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64
> machine.");
> > return FALSE;
> > }
> > if (mEhdr->e_version != EV_CURRENT) {
> > @@ -481,6 +488,7 @@ ScanSections64 (
> > switch (mEhdr->e_machine) {
> > case EM_X86_64:
> > case EM_AARCH64:
> > + case EM_RISCV64:
> > mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
> > break;
> > default:
> > @@ -690,6 +698,11 @@ ScanSections64 (
> > NtHdr->Pe32Plus.FileHeader.Machine =
> EFI_IMAGE_MACHINE_AARCH64;
> > NtHdr->Pe32Plus.OptionalHeader.Magic =
> EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > break;
> > + case EM_RISCV64:
> > + NtHdr->Pe32Plus.FileHeader.Machine =
> EFI_IMAGE_MACHINE_RISCV64;
> > + NtHdr->Pe32Plus.OptionalHeader.Magic =
> EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > + break;
> > +
> > default:
> > VerboseMsg ("%s unknown e_machine type. Assume X64",
> (UINTN)mEhdr->e_machine);
> > NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
> > @@ -769,6 +782,11 @@ WriteSections64 (
> > Elf_Shdr *SecShdr;
> > UINT32 SecOffset;
> > BOOLEAN (*Filter)(Elf_Shdr *);
> > + UINT32 Value;
> > + UINT32 Value2;
> > + UINT8 *Pass1Targ = NULL;
> > + Elf_Shdr *Pass1Sym = NULL;
> > + Elf64_Half Pass1SymSecIndex = 0;
> > Elf64_Addr GOTEntryRva;
> >
> > //
> > @@ -893,13 +911,14 @@ WriteSections64 (
> > if (SymName == NULL) {
> > SymName = (const UINT8 *)"<unknown>";
> > }
> > + if (mEhdr->e_machine != EM_RISCV64) {
>
> This needs a comment explaining why this does not apply to RISCV.
>
> > + Error (NULL, 0, 3000, "Invalid",
> > + "%s: Bad definition for symbol '%s'@%#llx or unsupported
> symbol type. "
> > + "For example, absolute and undefined symbols are not
> supported.",
> > + mInImageName, SymName, Sym->st_value);
> >
> > - Error (NULL, 0, 3000, "Invalid",
> > - "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol
> type. "
> > - "For example, absolute and undefined symbols are not
> supported.",
> > - mInImageName, SymName, Sym->st_value);
> > -
> > - exit(EXIT_FAILURE);
> > + exit(EXIT_FAILURE);
> > + }
> > }
> > SymShdr = GetShdrByIndex(Sym->st_shndx);
> >
> > @@ -1114,6 +1133,128 @@ WriteSections64 (
> > default:
> > Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported
> ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned)
> ELF_R_TYPE(Rel->r_info));
> > }
> > + } else if (mEhdr->e_machine == EM_RISCV64) {
>
> Yeah, this code block is just *waaaay* too big.
> Please break it out into its own helper function.
Leif, I am not going to address this issue this time. I just follow what other archs done in this function. I agree with you this function is way too long. I could create a task to refine this function once RISC-V part is reviewed and pushed to the mainstream.
>
> > + switch (ELF_R_TYPE(Rel->r_info)) {
> > + case R_RISCV_NONE:
> > + break;
> > + case R_RISCV_32:
> > + *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr-
> >sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
> > + break;
> > + case R_RISCV_64:
> > + *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr +
> mCoffSectionsOffset[Sym->st_shndx];
> > + break;
> > + case R_RISCV_HI20:
> > + Pass1Targ = Targ;
> > + Pass1Sym = SymShdr;
> > + Pass1SymSecIndex = Sym->st_shndx;
> > + break;
> > + case R_RISCV_LO12_I:
> > + if (Pass1Sym == SymShdr && Pass1Targ != NULL &&
> Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
> > + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym-
> >st_shndx];
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
> > + (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
> > + *(UINT32 *)Targ = (RV_X (Value, 0, 12) << 20) | \
> > + (RV_X (*(UINT32 *)Targ, 0, 20));
> > + }
> > + Pass1Sym = NULL;
> > + Pass1Targ = NULL;
> > + Pass1SymSecIndex = 0;
> > + break;
> > +
> > + case R_RISCV_LO12_S:
> > + if (Pass1Sym == SymShdr && Pass1Targ != NULL &&
> Pass1SymSecIndex == Sym->st_shndx && Pass1SymSecIndex != 0) {
> > + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12);
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UINT32
> *)Targ, 25, 7) << 5));
> > + if (Value2 & (RISCV_IMM_REACH/2)) {
> > + Value2 |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value += Value2;
> > + Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym-
> >st_shndx];
> > + Value2 = RISCV_CONST_HIGH_PART (Value);
> > + *(UINT32 *)Pass1Targ = (RV_X (Value2, 12, 20) << 12) | \
> > + (RV_X (*(UINT32 *)Pass1Targ, 0, 12));
> > +
> > + Value2 = *(UINT32 *)Targ & 0x01fff07f;
> > + Value &= RISCV_IMM_REACH - 1;
> > + *(UINT32 *)Targ = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |
> (RV_X(Value, 5, 7) << 25)));
> > + }
> > + Pass1Sym = NULL;
> > + Pass1Targ = NULL;
> > + Pass1SymSecIndex = 0;
> > + break;
> > +
> > + case R_RISCV_PCREL_HI20:
> > + Pass1Targ = Targ;
> > + Pass1Sym = SymShdr;
> > + Pass1SymSecIndex = Sym->st_shndx;
> > +
> > + Value = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
> > + break;
> > + case R_RISCV_PCREL_LO12_I:
> > + if (Pass1Targ != NULL && Pass1Sym != NULL &&
> Pass1SymSecIndex != 0) {
> > + int i;
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20));
> > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > + if(Value & (RISCV_IMM_REACH/2)) {
> > + Value |= ~(RISCV_IMM_REACH-1);
> > + }
> > + Value = Value - Pass1Sym->sh_addr +
> mCoffSectionsOffset[Pass1SymSecIndex];
> > + if(-2048 > (INT32)Value) {
> > + i = (-Value / 4096);
> > + Value2 -= i;
> > + Value += 4096 * i;
> > + if(-2048 > (INT32)Value) {
> > + Value2 -= 1;
> > + Value += 4096;
> > + }
> > + }
> > + else if( 2047 < (INT32)Value) {
> > + i = (Value / 4096);
> > + Value2 += i;
> > + Value -= 4096 * i;
> > + if(2047 < (INT32)Value) {
> > + Value2 += 1;
> > + Value -= 4096;
> > + }
> > + }
> > +
> > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> (RV_X(*(UINT32*)Targ, 0, 20));
> > + *(UINT32 *)Pass1Targ = (RV_X(Value2, 0, 20)<<12) |
> (RV_X(*(UINT32 *)Pass1Targ, 0, 12));
> > + }
> > + Pass1Sym = NULL;
> > + Pass1Targ = NULL;
> > + Pass1SymSecIndex = 0;
> > + break;
> > +
> > + case R_RISCV_ADD64:
> > + case R_RISCV_SUB64:
> > + case R_RISCV_ADD32:
> > + case R_RISCV_SUB32:
> > + case R_RISCV_BRANCH:
> > + case R_RISCV_JAL:
> > + case R_RISCV_GPREL_I:
> > + case R_RISCV_GPREL_S:
> > + case R_RISCV_CALL:
> > + case R_RISCV_RVC_BRANCH:
> > + case R_RISCV_RVC_JUMP:
> > + case R_RISCV_RELAX:
> > + case R_RISCV_SUB6:
> > + case R_RISCV_SET6:
> > + case R_RISCV_SET8:
> > + case R_RISCV_SET16:
> > + case R_RISCV_SET32:
> > + break;
> > +
> > + default:
> > + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported
> ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned)
> ELF_R_TYPE(Rel->r_info));
> > + }
> > } else {
> > Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
> > }
> > @@ -1133,6 +1274,7 @@ WriteRelocations64 (
> > UINT32 Index;
> > EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
> > EFI_IMAGE_DATA_DIRECTORY *Dir;
> > + UINT32 RiscVRelType;
> >
> > for (Index = 0; Index < mEhdr->e_shnum; Index++) {
> > Elf_Shdr *RelShdr = GetShdrByIndex(Index);
> > @@ -1237,6 +1379,108 @@ WriteRelocations64 (
> > default:
> > Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s
> unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName,
> (unsigned) ELF_R_TYPE(Rel->r_info));
> > }
> > + } else if (mEhdr->e_machine == EM_RISCV64) {
> > + RiscVRelType = ELF_R_TYPE(Rel->r_info);
> > + switch (RiscVRelType) {
> > + case R_RISCV_NONE:
> > + break;
> > +
> > + case R_RISCV_32:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_HIGHLOW);
> > + break;
> > +
> > + case R_RISCV_64:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_DIR64);
> > + break;
> > +
> > + case R_RISCV_HI20:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_RISCV_HI20);
> > + break;
> > +
> > + case R_RISCV_LO12_I:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_RISCV_LOW12I);
> > + break;
> > +
> > + case R_RISCV_LO12_S:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_RISCV_LOW12S);
> > + break;
> > +
> > + case R_RISCV_ADD64:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_SUB64:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_ADD32:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_SUB32:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_BRANCH:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_JAL:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_GPREL_I:
> > + case R_RISCV_GPREL_S:
> > + case R_RISCV_CALL:
> > + case R_RISCV_RVC_BRANCH:
> > + case R_RISCV_RVC_JUMP:
> > + case R_RISCV_RELAX:
> > + case R_RISCV_SUB6:
> > + case R_RISCV_SET6:
> > + case R_RISCV_SET8:
> > + case R_RISCV_SET16:
> > + case R_RISCV_SET32:
> > + case R_RISCV_PCREL_HI20:
> > + case R_RISCV_PCREL_LO12_I:
> > + break;
> > +
> > + default:
> > + printf ("Unsupported RISCV64 ELF relocation type 0x%x, offset:
> %lx\n", RiscVRelType, Rel->r_offset);
>
> printf is not a supported output function in this file. Please use Error.
>
> > + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s
> unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned)
> ELF_R_TYPE(Rel->r_info));
> > + }
> > } else {
> > Error (NULL, 0, 3000, "Not Supported", "This tool does not support
> relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr-
> >e_machine);
> > }
> > diff --git a/BaseTools/Source/C/GenFw/elf_common.h
> b/BaseTools/Source/C/GenFw/elf_common.h
> > index 15c9e33..1321f78 100644
> > --- a/BaseTools/Source/C/GenFw/elf_common.h
> > +++ b/BaseTools/Source/C/GenFw/elf_common.h
> > @@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD
> >
> > Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > +Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >
> > @@ -178,6 +179,8 @@ typedef struct {
> > #define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
> > #define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64
> (compat) */
> > #define EM_AARCH64 183 /* ARM 64bit Architecture */
> > +#define EM_RISCV64 243 /* 64bit RISC-V Architecture */
> > +#define EM_RISCV 244 /* 32bit RISC-V Architecture */
> >
> > /* Non-standard or deprecated. */
> > #define EM_486 6 /* Intel i486. */
> > @@ -979,5 +982,64 @@ typedef struct {
> > #define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative
> offset to GOT entry without REX prefix, relaxable. */
> > #define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc
> relative offset to GOT entry with REX prefix, relaxable. */
> >
> > +/*
> > + * RISC-V relocation types
> > + */
> > +
> > +/* Relocation types used by the dynamic linker */
> > +#define R_RISCV_NONE 0
> > +#define R_RISCV_32 1
> > +#define R_RISCV_64 2
> > +#define R_RISCV_RELATIVE 3
> > +#define R_RISCV_COPY 4
> > +#define R_RISCV_JUMP_SLOT 5
> > +#define R_RISCV_TLS_DTPMOD32 6
> > +#define R_RISCV_TLS_DTPMOD64 7
> > +#define R_RISCV_TLS_DTPREL32 8
> > +#define R_RISCV_TLS_DTPREL64 9
> > +#define R_RISCV_TLS_TPREL32 10
> > +#define R_RISCV_TLS_TPREL64 11
> >
> > +/* Relocation types not used by the dynamic linker */
> > +#define R_RISCV_BRANCH 16
> > +#define R_RISCV_JAL 17
> > +#define R_RISCV_CALL 18
> > +#define R_RISCV_CALL_PLT 19
> > +#define R_RISCV_GOT_HI20 20
> > +#define R_RISCV_TLS_GOT_HI20 21
> > +#define R_RISCV_TLS_GD_HI20 22
> > +#define R_RISCV_PCREL_HI20 23
> > +#define R_RISCV_PCREL_LO12_I 24
> > +#define R_RISCV_PCREL_LO12_S 25
> > +#define R_RISCV_HI20 26
> > +#define R_RISCV_LO12_I 27
> > +#define R_RISCV_LO12_S 28
> > +#define R_RISCV_TPREL_HI20 29
> > +#define R_RISCV_TPREL_LO12_I 30
> > +#define R_RISCV_TPREL_LO12_S 31
> > +#define R_RISCV_TPREL_ADD 32
> > +#define R_RISCV_ADD8 33
> > +#define R_RISCV_ADD16 34
> > +#define R_RISCV_ADD32 35
> > +#define R_RISCV_ADD64 36
> > +#define R_RISCV_SUB8 37
> > +#define R_RISCV_SUB16 38
> > +#define R_RISCV_SUB32 39
> > +#define R_RISCV_SUB64 40
> > +#define R_RISCV_GNU_VTINHERIT 41
> > +#define R_RISCV_GNU_VTENTRY 42
> > +#define R_RISCV_ALIGN 43
> > +#define R_RISCV_RVC_BRANCH 44
> > +#define R_RISCV_RVC_JUMP 45
> > +#define R_RISCV_RVC_LUI 46
> > +#define R_RISCV_GPREL_I 47
> > +#define R_RISCV_GPREL_S 48
> > +#define R_RISCV_TPREL_I 49
> > +#define R_RISCV_TPREL_S 50
> > +#define R_RISCV_RELAX 51
> > +#define R_RISCV_SUB6 52
> > +#define R_RISCV_SET6 53
> > +#define R_RISCV_SET8 54
> > +#define R_RISCV_SET16 55
> > +#define R_RISCV_SET32 56
> > #endif /* !_SYS_ELF_COMMON_H_ */
> > diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> > index 44037d1..2ed3008 100644
> > --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> > +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> > @@ -6,6 +6,7 @@
> >
> > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> All rights reserved.<BR>
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -41,6 +42,7 @@
> > #define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
> > #define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and
> Thumb/Thumb 2 Little Endian
> > #define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM
> Architecture, Little Endian
> > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
> >
> > //
> > // Support old names for backward compatible
> > @@ -50,6 +52,7 @@
> > #define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
> > #define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
> > #define EFI_IMAGE_MACHINE_AARCH64
> IMAGE_FILE_MACHINE_ARM64
> > +#define EFI_IMAGE_MACHINE_RISCV64
> IMAGE_FILE_MACHINE_RISCV64
> >
> > #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
> > #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
> > @@ -504,7 +507,10 @@ typedef struct {
> > #define EFI_IMAGE_REL_BASED_HIGHADJ 4
> > #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
> > #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
> > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
> > #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
> > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
> > #define EFI_IMAGE_REL_BASED_IA64_IMM64 9
> > #define EFI_IMAGE_REL_BASED_DIR64 10
> >
> > diff --git a/BaseTools/Source/Python/Common/DataType.py
> b/BaseTools/Source/Python/Common/DataType.py
> > index 8ae1bd2..fc23e8c 100644
> > --- a/BaseTools/Source/Python/Common/DataType.py
> > +++ b/BaseTools/Source/Python/Common/DataType.py
> > @@ -3,6 +3,7 @@
> > #
> > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> > # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> > +# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise
> Development LP. All rights reserved.<BR>
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > ##
> > @@ -52,7 +53,9 @@ TAB_ARCH_ARM = 'ARM'
> > TAB_ARCH_EBC = 'EBC'
> > TAB_ARCH_AARCH64 = 'AARCH64'
> >
> > -ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM,
> TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_COMMON}
> > +TAB_ARCH_RISCV64 = 'RISCV64'
> > +
> > +ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM,
> TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64,
> TAB_ARCH_COMMON}
> >
> > SUP_MODULE_BASE = 'BASE'
> > SUP_MODULE_SEC = 'SEC'
> > @@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE = {8:'=Q',
> > 0:'=B',
> > 16:""}
> >
> > -TAB_COMPILER_MSFT = 'MSFT'
> > \ No newline at end of file
> > +TAB_COMPILER_MSFT = 'MSFT'
>
> Please either fix in a separate patch or leave out altogether.
>
> /
> Leif
>
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
2019-09-26 20:50 ` [edk2-devel] " Leif Lindholm
@ 2019-10-15 6:31 ` Abner Chang
2019-10-15 11:00 ` Leif Lindholm
0 siblings, 1 reply; 108+ messages in thread
From: Abner Chang @ 2019-10-15 6:31 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, September 27, 2019 4:51 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29]
> BaseTools/Scripts
>
> On Mon, Sep 23, 2019 at 08:31:51AM +0800, Abner Chang wrote:
> > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > GccBase.lds causes PE32 relocation error.
> > This is the temporaty solution untill we find the root casue.
>
> I presume you mean that having a separate version for RISCV is temporary? I
> am OK with this for now. However, the diff is not what I would expect. Can
> you verify that the difference is only what you actually need?
Yes. Hope I can remove this change after I figuring out the toolchain issue.
>
> For example:
>
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > BaseTools/Scripts/GccBaseRiscV.lds | 66
> > ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 66 insertions(+)
> > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> >
> > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > b/BaseTools/Scripts/GccBaseRiscV.lds
> > new file mode 100644
> > index 0000000..7f9fae6
> > --- /dev/null
> > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > @@ -0,0 +1,66 @@
> > +/** @file
> > +
> > + Unified linker script for GCC based builds
> > +
> > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > + Development LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +SECTIONS {
> > +
> > + /*
> > + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> sequence of
> > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> differs
> > + * between 32-bit and 64-bit builds). The actual start of the .text section
> > + * will be rounded up based on its actual alignment.
> > + */
> > + . = PECOFF_HEADER_SIZE;
> > +
> > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > + *(.rodata .rodata.* .gnu.linkonce.r.*)
> > + *(.got .got.*)
> > +
> > + /*
> > + * The contents of AutoGen.c files are constant from the POV of the
> program,
> > + * but most of its contents end up in .data or .bss by default since few of
> > + * the variable definitions that get emitted are declared as CONST.
> > + */
>
> The above comment block looks completely different - in GccBase.lds:
> /*
> * The contents of AutoGen.c files are mostly constant from the POV of
> the
> * program, but most of it ends up in .data or .bss by default since few of
> * the variable definitions that get emitted are declared as CONST.
> * Unfortunately, we cannot pull it into the .text section entirely, since
> * patchable PCDs are also emitted here, but we can at least move all of
> the
> * emitted GUIDs here.
> */
>
> > + *:AutoGen.obj(.data.g*Guid)
> > + }
> > +
> > + /*
> > + * The alignment of the .data section should be less than or equal to the
> > + * alignment of the .text section. This ensures that the relative offset
> > + * between these sections is the same in the ELF and the PE/COFF
> versions of
> > + * this binary.
> > + */
> > + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
> {
> > + *(.data .data.* .gnu.linkonce.d.*)
> > + *(.bss .bss.*)
> > + }
> > +
> > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > + KEEP (*(.eh_frame))
> > + }
> > +
> > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
>
> The above line is, I believe, the only necessary change for your workaround?
Yes. only this line is necessary. I guess I copied entire lds file from my old edk2 tree.
>
> > + *(.rela .rela.*)
> > + }
> > +
>
> The original one as the following:
> .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> KEEP (*(.hii))
> }
>
> I do not think including this could be the cause of any issues.
>
> Also, GccBase.lds includes here:
> /*
> * Retain the GNU build id but in a non-allocatable section so GenFw
> * does not copy it into the PE/COFF image.
> */
> .build-id (INFO) : { *(.note.gnu.build-id) }
>
> > + /DISCARD/ : {
> > + *(.note.GNU-stack)
> > + *(.gnu_debuglink)
> > + *(.interp)
> > + *(.dynsym)
> > + *(.dynstr)
> > + *(.dynamic)
> > + *(.hash)
>
> In GccBase.lds:
> *(.hash .gnu.hash)
>
> /
> Leif
>
> > + *(.comment)
> > + *(COMMON)
> > + }
> > +}
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on
2019-09-26 22:22 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Leif Lindholm
@ 2019-10-15 6:39 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 6:39 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
Hi Leif, thanks for spending lot of time to review the set of RISC-V edk2 patches. I addressed most of comments and gave back few feedbacks to you in email.
I think the major remaining issue is the toolchain problem. I will investigate toolchain issue while you review v3 patches. I think most of patches should look fine now. How do you think?
Abner
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, September 27, 2019 6:23 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V
> EDK2 Port on
>
> On Mon, Sep 23, 2019 at 08:31:25AM +0800, Abner Chang wrote:
> > This branch "RISC-V-V2" is used to contribute RISC-V architecture on EDK2.
> > Compare to the old branch "RISC-V", this branch "RISC-V-V2" is created
> > based on the most recent edk2/master @37eef910. This is easier for
> > reviewers to have clear ideas of edk2 code changes for RISC-V EDK2
> implementation.
> > Because of the code changes made on old branch "RISC-V" is stale and
> > not compliant with the latest RISC-V spec, this new branch has the
> > fresh changes for RISC-V EDK2 implementation.
> >
> > The main changes of these series of patches are,
> > - Add RiscVPkg which conform with RISC-V Privilege Spec v1.10.
> > - Incorporate and leverage RISC-V OpenSBI to provide EDK2 port OpenSBI
> library.
> > - Provide RISC-V platform implementation specific drivers to EDK2 RISC-V
> platform
> > package.
> > - Provide generic RISC-V SMBIOS DXE drive to create SMBIOS type 4, 7 and
> 44 records,
> > in which the SMBIOS type 44 record is introduced in SMBIOS spec 3.3.0.
> >
> > Abner Chang (29):
> > RiscVPkg: RISC-V processor package.
> > RiscVPkg/Include: Add header files of RISC-V CPU package
> > RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
>
> PatchCheck.py warns about long line in commit message.
>
> > MdePkg: RISC-V RV64 binding in MdePkg
> > MdePkg/Include: RISC-V definitions.
> > MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
> > MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
> > MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
> > implementation.
>
> PatchCheck.py warns about long line in commit message.
>
> > MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
> > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> > MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
> > MdePkg/BaseSynchronizationLib: RISC-V cache related code.
> > MdeModulePkg/Logo
> > NetworkPkg
> > RiscVPkg/Library: RISC-V CPU library
> > RiscVPkg/Library: Add RISC-V exception library
> > RiscVPkg/Library: Add RISC-V timer library
> > RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
> > RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
> > MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
> > RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service
> > Table Pointer library
>
> PatchCheck.py warns about long line in commit message.
>
> > RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary
> > Memory library
>
> PatchCheck.py warns about long line in commit message.
>
> /
> Leif
>
> > RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
> > BaseTools: BaseTools changes for RISC-V platform.
> > BaseTools/Scripts
> > RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
> > platforms.
> > edk2-staging/RISC-V-V2: Add submodule
> > edk2-staging/RISC-V-V2: Add ReadMe
> > edk2-staging: Update Maintainers.txt
> >
> > .gitmodules | 16 +-
> > BaseTools/Conf/build_rule.template | 62 ++-
> > BaseTools/Conf/tools_def.template | 64 ++-
> > BaseTools/Scripts/GccBaseRiscV.lds | 66 +++
> > BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++
> > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++-
> > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> > BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++-
> > BaseTools/Source/C/GenFw/elf_common.h | 62 +++
> > .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> > BaseTools/Source/Python/Common/DataType.py | 7 +-
> > Maintainers.txt | 5 +
> > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +-
> > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 +++
> > MdeModulePkg/Logo/Logo.inf | 2 +-
> > .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +-
> > MdePkg/Include/IndustryStandard/PeImage.h | 12 +
> > MdePkg/Include/Library/BaseLib.h | 26 +
> > MdePkg/Include/Protocol/DebugSupport.h | 55 ++
> > MdePkg/Include/Protocol/PxeBaseCode.h | 4 +
> > MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++
> > MdePkg/Include/Uefi/UefiBaseType.h | 13 +
> > MdePkg/Include/Uefi/UefiSpec.h | 5 +
> > .../BaseCacheMaintenanceLib.inf | 4 +
> > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++
> > MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-
> > MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
> > MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +
> > .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +-
> > MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601
> +++++++++++++++++++++
> > MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
> > MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +
> > MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +
> > MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 +
> > MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 +
> > MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +
> > MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++
> > .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++
> > MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 ++
> > .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +
> > MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +
> > MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 ++
> > .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++
> > MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++
> > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++
> > .../BaseSynchronizationLib.inf | 6 +
> > .../RiscV64/Synchronization.c | 183 +++++++
> > .../RiscV64/SynchronizationAsm.S | 78 +++
> > MdePkg/MdePkg.dec | 5 +-
> > NetworkPkg/Network.dsc.inc | 2 +-
> > RiscVEdk2Readme.md | 34 ++
> > RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++
> > RiscVPkg/Include/Library/RiscVCpuLib.h | 68 +++
> > RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++
> > .../Library/RiscVPlatformTempMemoryInitLib.h | 17 +
> > RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++
> > RiscVPkg/Include/RiscV.h | 72 +++
> > RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++
> > RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++
> > RiscVPkg/Include/sbi/sbi.h | 96 ++++
> > RiscVPkg/Include/sbi/sbi_bits.h | 17 +
> > RiscVPkg/Include/sbi/sbi_types.h | 18 +
> > .../PeiServicesTablePointerLibOpenSbi.inf | 38 ++
> > .../PeiServicesTablePointerLibOpenSbi.uni | 23 +
> > .../PeiServicesTablePointerOpenSbi.c | 121 +++++
> > RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 ++++
> > RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++
> > .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 ++
> > .../RiscVDxeIplHandoffLib.inf | 32 ++
> > .../RiscVDxeIplHandoffOpenSbiLib.c | 102 ++++
> > .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 ++
> > .../RiscVExceptionLib/CpuExceptionHandler.S | 88 +++
> > .../CpuExceptionHandlerDxeLib.inf | 42 ++
> > .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++
> > .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 +
> > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++
> > .../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++
> > .../Riscv64/TempMemInit.S | 26 +
> > .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++
> > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++
> > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +
> > RiscVPkg/RiscVPkg.dec | 42 ++
> > RiscVPkg/RiscVPkg.uni | 13 +
> > RiscVPkg/RiscVPkgExtra.uni | 13 +
> > RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 +++++++++++
> > RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++
> > RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++
> > RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
> > RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 ++++++++++++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
> > .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
> > RiscVPkg/opensbi | 1 +
> > 100 files changed, 6085 insertions(+), 66 deletions(-) create mode
> > 100644 BaseTools/Scripts/GccBaseRiscV.lds
> > create mode 100644
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> > create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
> > create mode 100644
> > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> > create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c
> > create mode 100644
> > MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > create mode 100644
> > MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c
> > create mode 100644
> > MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> > create mode 100644 RiscVEdk2Readme.md create mode 100644
> > RiscVPkg/Include/IndustryStandard/RiscV.h
> > create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
> > create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
> > create mode 100644
> > RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
> > create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
> > create mode 100644 RiscVPkg/Include/RiscV.h create mode 100644
> > RiscVPkg/Include/SmbiosProcessorSpecificData.h
> > create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
> > create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644
> > RiscVPkg/Include/sbi/sbi_bits.h create mode 100644
> > RiscVPkg/Include/sbi/sbi_types.h create mode 100644
> > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi
> > nterLibOpenSbi.inf create mode 100644
> > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi
> > nterLibOpenSbi.uni create mode 100644
> > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi
> > nterOpenSbi.c create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
> > create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> > create mode 100644
> > RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
> > create mode 100644
> > RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
> > create mode 100644
> >
> RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS
> b
> > iLib.c create mode 100644
> >
> RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS
> b
> > iLib.inf create mode 100644
> > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
> > create mode 100644
> > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> > create mode 100644
> > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> > create mode 100644
> > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> > create mode 100644
> > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > create mode 100644
> >
> RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTemp
> M
> > emoryInitLibNull.inf create mode 100644
> >
> RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemI
> ni
> > t.S create mode 100644
> > RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h
> > create mode 100644 RiscVPkg/RiscVPkg.dec create mode 100644
> > RiscVPkg/RiscVPkg.uni create mode 100644 RiscVPkg/RiscVPkgExtra.uni
> > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
> > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
> > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> > create mode 100644
> > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> > create mode 160000 RiscVPkg/opensbi
> >
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-10-15 1:21 ` Abner Chang
@ 2019-10-15 8:35 ` Leif Lindholm
0 siblings, 0 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-10-15 8:35 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io
On Tue, Oct 15, 2019 at 01:21:35AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Tuesday, October 1, 2019 4:04 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29]
> > RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
> >
> > On Mon, Sep 23, 2019 at 08:31:44AM +0800, Abner Chang wrote:
> > > EDK2 RISC-V OpenSBI library which pull in external source files under
> > > RiscVPkg/opensbi to the build process.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52
> > ++++++++++++++++++++++
> > > 1 file changed, 52 insertions(+)
> > > create mode 100644
> > > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > >
> > > diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > new file mode 100644
> > > index 0000000..640ffba
> > > --- /dev/null
> > > +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > @@ -0,0 +1,52 @@
> > > +## @file
> > > +# RISC-V Opensbi Library Instance.
> > > +#
> > > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > > +rights reserved.<BR> # # SPDX-License-Identifier:
> > > +BSD-2-Clause-Patent # ##
> > > +
> > > +[Defines]
> > > + INF_VERSION = 0x0001001b
> > > + BASE_NAME = RiscVOpensbiLib
> > > + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> > > + MODULE_TYPE = BASE
> > > + VERSION_STRING = 1.0
> > > + LIBRARY_CLASS = RiscVOpensbiLib
> > > +
> > > +[Sources]
> > > + ../../opensbi/lib/sbi/riscv_asm.c
> >
> > Please move the opensbi directory to here instead.
> >
> This is good. Now [Includes] in RiscVPkg.dec looks like this,
> [Includes]
> Library/RiscvOpensbiLib/opensbi
> Library/RiscvOpensbiLib/opensbi/include
Exactly, thanks!
/
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-10-15 4:02 ` Abner Chang
@ 2019-10-15 10:31 ` Leif Lindholm
2019-10-15 10:56 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-15 10:31 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io
On Tue, Oct 15, 2019 at 04:02:47AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, September 27, 2019 7:46 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> >
> > On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > > Support RISC-V image relocation.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> > +++++++++++++++++++++
> > > 5 files changed, 152 insertions(+), 1 deletion(-) create mode 100644
> > > MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > >
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > index 07bb62f..97e0ff4 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > @@ -1,6 +1,6 @@
> > > /** @file
> > > Base PE/COFF loader supports loading any PE32/PE32+ or TE image,
> > > but
> > > - only supports relocating IA32, x64, IPF, and EBC images.
> > > + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
> > >
> > > Caution: This file requires additional review when modified.
> > > This library will have external input - PE/COFF image.
> > > @@ -17,6 +17,7 @@
> > >
> > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > > Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > > reserved.<BR>
> > > + Portions Copyright (c) 2016, Hewlett Packard Enterprise Development
> > > + LP. All rights reserved.<BR>
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > **/
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > index 395c140..b190494 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > @@ -3,6 +3,7 @@
> > > # The IPF version library supports loading IPF and EBC PE/COFF image.
> > > # The IA32 version library support loading IA32, X64 and EBC PE/COFF
> > images.
> > > # The X64 version library support loading IA32, X64 and EBC PE/COFF
> > images.
> > > +# The RISC-V version library support loading RISC-V images.
> > > #
> > > # Caution: This module requires additional review when modified.
> > > # This library will have external input - PE/COFF image.
> > > @@ -11,6 +12,7 @@
> > > #
> > > # Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All
> > > rights reserved.<BR>
> > > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > > +rights reserved.<BR>
> > > #
> > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@
> > > [Sources.ARM]
> > > Arm/PeCoffLoaderEx.c
> > >
> > > +[Sources.RISCV64]
> > > + RiscV/PeCoffLoaderEx.c
> > > +
> > > [Packages]
> > > MdePkg/MdePkg.dec
> > >
> > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > index b0ea702..8616ca3 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > @@ -4,6 +4,7 @@
> > > // The IPF version library supports loading IPF and EBC PE/COFF image.
> > > // The IA32 version library support loading IA32, X64 and EBC PE/COFF
> > images.
> > > // The X64 version library support loading IA32, X64 and EBC PE/COFF
> > images.
> > > +// The RISC-V version library support loading RISC-V32 and RISC-V64
> > PE/COFF images.
> > > //
> > > // Caution: This module requires additional review when modified.
> > > // This library will have external input - PE/COFF image.
> > > @@ -12,6 +13,7 @@
> > > //
> > > // Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > reserved.<BR> // Portions copyright (c) 2008 - 2009, Apple Inc. All
> > > rights reserved.<BR>
> > > +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > > +rights reserved.<BR>
> > > //
> > > // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git
> > > a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > index b74277f..9c33703 100644
> > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > @@ -2,6 +2,7 @@
> > > Declaration of internal functions in PE/COFF Lib.
> > >
> > > Copyright (c) 2006 - 2010, Intel Corporation. All rights
> > > reserved.<BR>
> > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > > + rights reserved.<BR>
> >
> > You only get to add copyright when you otherwise modify the file :)
> >
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > **/
> > > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > new file mode 100644
> > > index 0000000..8eb37f9
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > @@ -0,0 +1,142 @@
> > > +/** @file
> > > + PE/Coff loader for RISC-V PE image
> > > +
> > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All
> > > +rights reserved.<BR>
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > > +"BasePeCoffLibInternals.h"
> > > +#include <Library/BaseLib.h>
> > > +
> > > +//
> > > +// RISC-V definition.
> > > +//
> > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> > (1LL<<RISCV_IMM_BITS)
> > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> >
> > This looked familiar, so I had a look.
> > This block is copied around - it exists in:
> > - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > - BaseTools/Source/C/GenFw/Elf64Convert.c
> > - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> >
> > This needs to be moved somewhere central and included elsewhere.
> > BaseTools and MdePkg unfortunately duplicate a lot of stuff, but this still
> > belongs in a common header file for either.
>
> I can consolidate that macro in two files under BaseTools, but not
> consolidating macro in files in both MdePkg and BaseTools. BaseTools
> and edk2 are two separate projects and could be built individually
> based on my understanding.
>
> I have no idea how to leverage one header file from both projects
> and I don't go that far to address it.
Oh, indeed. This was me bemoaning the current state of things - not
suggesting you need to fix it (beyond having only one copy for
BaseTools and one copy for the platform code.).
I need to check my use of English subtleties:
"belongs in a common header file for either" means "one for each".
Best Regards,
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-10-15 4:26 ` Abner Chang
@ 2019-10-15 10:41 ` Leif Lindholm
2019-10-15 10:59 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-15 10:41 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io
On Tue, Oct 15, 2019 at 04:26:12AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
>
>
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Abner Chang
> > Sent: Tuesday, October 15, 2019 12:03 PM
> > To: devel@edk2.groups.io; leif.lindholm@linaro.org
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> >
> >
> >
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > > Leif Lindholm
> > > Sent: Friday, September 27, 2019 7:46 AM
> > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > <abner.chang@hpe.com>
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> > >
> > > On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > > > Support RISC-V image relocation.
> > > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> > > +++++++++++++++++++++
> > > > 5 files changed, 152 insertions(+), 1 deletion(-) create mode
> > > > 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > new file mode 100644
> > > > index 0000000..8eb37f9
> > > > --- /dev/null
> > > > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > @@ -0,0 +1,142 @@
> > > > +/** @file
> > > > + PE/Coff loader for RISC-V PE image
> > > > +
> > > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > +All rights reserved.<BR>
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > > > +"BasePeCoffLibInternals.h"
> > > > +#include <Library/BaseLib.h>
> > > > +
> > > > +//
> > > > +// RISC-V definition.
> > > > +//
> > > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> > > (1LL<<RISCV_IMM_BITS)
> > > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > >
> > > This looked familiar, so I had a look.
> > > This block is copied around - it exists in:
> > > - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > > - BaseTools/Source/C/GenFw/Elf64Convert.c
> > > - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > >
> > > This needs to be moved somewhere central and included elsewhere.
> > > BaseTools and MdePkg unfortunately duplicate a lot of stuff, but this
> > > still belongs in a common header file for either.
> >
> > I can consolidate that macro in two files under BaseTools, but not
> > consolidating macro in files in both MdePkg and BaseTools. BaseTools and
> > edk2 are two separate projects and could be built individually based on my
> > understanding.
> > I have no idea how to leverage one header file from both projects and I don't
> > go that far to address it.
>
> Leif, seem there is no good place and the existing header file to
> put this macro unless I create a new header file under
> BaseTools/Source/C/Include. I would like to keep this duplicate
> macro in both files rather than create an header file in which only
> define this macro. Do you have good idea?
There is never a good reason to duplicate code. You will always end up
changing one and forgetting the other.
I see no problem with creating a header file which contains nothing
else. But I also think it would be valid to put this into
C/Common/PeCoffLib.h - and this file is already included by the
affected .c files.
/
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-10-15 10:31 ` Leif Lindholm
@ 2019-10-15 10:56 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 10:56 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Tuesday, October 15, 2019 6:32 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
>
> On Tue, Oct 15, 2019 at 04:02:47AM +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > Of Leif Lindholm
> > > Sent: Friday, September 27, 2019 7:46 AM
> > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > <abner.chang@hpe.com>
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> > >
> > > On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > > > Support RISC-V image relocation.
> > > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> > > +++++++++++++++++++++
> > > > 5 files changed, 152 insertions(+), 1 deletion(-) create mode
> > > > 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > >
> > > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > > b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > > index 07bb62f..97e0ff4 100644
> > > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
> > > > @@ -1,6 +1,6 @@
> > > > /** @file
> > > > Base PE/COFF loader supports loading any PE32/PE32+ or TE
> > > > image, but
> > > > - only supports relocating IA32, x64, IPF, and EBC images.
> > > > + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
> > > >
> > > > Caution: This file requires additional review when modified.
> > > > This library will have external input - PE/COFF image.
> > > > @@ -17,6 +17,7 @@
> > > >
> > > > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > > > Portions copyright (c) 2008 - 2009, Apple Inc. All rights
> > > > reserved.<BR>
> > > > + Portions Copyright (c) 2016, Hewlett Packard Enterprise
> > > > + Development LP. All rights reserved.<BR>
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > **/
> > > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > > index 395c140..b190494 100644
> > > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > > > @@ -3,6 +3,7 @@
> > > > # The IPF version library supports loading IPF and EBC PE/COFF image.
> > > > # The IA32 version library support loading IA32, X64 and EBC
> > > > PE/COFF
> > > images.
> > > > # The X64 version library support loading IA32, X64 and EBC
> > > > PE/COFF
> > > images.
> > > > +# The RISC-V version library support loading RISC-V images.
> > > > #
> > > > # Caution: This module requires additional review when modified.
> > > > # This library will have external input - PE/COFF image.
> > > > @@ -11,6 +12,7 @@
> > > > #
> > > > # Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > > reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc.
> > > > All rights reserved.<BR>
> > > > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > +All rights reserved.<BR>
> > > > #
> > > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9
> > > > @@ [Sources.ARM]
> > > > Arm/PeCoffLoaderEx.c
> > > >
> > > > +[Sources.RISCV64]
> > > > + RiscV/PeCoffLoaderEx.c
> > > > +
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > >
> > > > diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > > index b0ea702..8616ca3 100644
> > > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
> > > > @@ -4,6 +4,7 @@
> > > > // The IPF version library supports loading IPF and EBC PE/COFF image.
> > > > // The IA32 version library support loading IA32, X64 and EBC
> > > > PE/COFF
> > > images.
> > > > // The X64 version library support loading IA32, X64 and EBC
> > > > PE/COFF
> > > images.
> > > > +// The RISC-V version library support loading RISC-V32 and
> > > > +RISC-V64
> > > PE/COFF images.
> > > > //
> > > > // Caution: This module requires additional review when modified.
> > > > // This library will have external input - PE/COFF image.
> > > > @@ -12,6 +13,7 @@
> > > > //
> > > > // Copyright (c) 2006 - 2018, Intel Corporation. All rights
> > > > reserved.<BR> // Portions copyright (c) 2008 - 2009, Apple Inc.
> > > > All rights reserved.<BR>
> > > > +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > +All rights reserved.<BR>
> > > > //
> > > > // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git
> > > > a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > > b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > > index b74277f..9c33703 100644
> > > > --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > > +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
> > > > @@ -2,6 +2,7 @@
> > > > Declaration of internal functions in PE/COFF Lib.
> > > >
> > > > Copyright (c) 2006 - 2010, Intel Corporation. All rights
> > > > reserved.<BR>
> > > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > >
> > > You only get to add copyright when you otherwise modify the file :)
> > >
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > **/
> > > > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > new file mode 100644
> > > > index 0000000..8eb37f9
> > > > --- /dev/null
> > > > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > @@ -0,0 +1,142 @@
> > > > +/** @file
> > > > + PE/Coff loader for RISC-V PE image
> > > > +
> > > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > +All rights reserved.<BR>
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > > > +"BasePeCoffLibInternals.h"
> > > > +#include <Library/BaseLib.h>
> > > > +
> > > > +//
> > > > +// RISC-V definition.
> > > > +//
> > > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> > > (1LL<<RISCV_IMM_BITS)
> > > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > >
> > > This looked familiar, so I had a look.
> > > This block is copied around - it exists in:
> > > - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > > - BaseTools/Source/C/GenFw/Elf64Convert.c
> > > - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > >
> > > This needs to be moved somewhere central and included elsewhere.
> > > BaseTools and MdePkg unfortunately duplicate a lot of stuff, but
> > > this still belongs in a common header file for either.
> >
> > I can consolidate that macro in two files under BaseTools, but not
> > consolidating macro in files in both MdePkg and BaseTools. BaseTools
> > and edk2 are two separate projects and could be built individually
> > based on my understanding.
> >
> > I have no idea how to leverage one header file from both projects and
> > I don't go that far to address it.
>
> Oh, indeed. This was me bemoaning the current state of things - not
> suggesting you need to fix it (beyond having only one copy for BaseTools and
> one copy for the platform code.).
>
> I need to check my use of English subtleties:
> "belongs in a common header file for either" means "one for each".
Hah Hah. My bad.
Ok! Then it's much easier! Let me see if I can put RISC-V specific macro into an existing header file or a new one.
>
> Best Regards,
>
> Leif
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-10-15 6:18 ` Abner Chang
@ 2019-10-15 10:56 ` Leif Lindholm
2019-10-15 11:13 ` Abner Chang
2019-10-16 5:06 ` Abner Chang
0 siblings, 2 replies; 108+ messages in thread
From: Leif Lindholm @ 2019-10-15 10:56 UTC (permalink / raw)
To: devel, abner.chang
On Tue, Oct 15, 2019 at 06:18:29AM +0000, Abner Chang wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, September 27, 2019 6:10 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> > BaseTools: BaseTools changes for RISC-V platform.
> >
> > On Mon, Sep 23, 2019 at 08:31:50AM +0800, Abner Chang wrote:
> > > BaseTools changes for building EDK2 RISC-V platform.
> > > The changes made to build_rule.template is to avoid build errors
> > > cause by GCC711RISCV tool chain.
> >
> > Thank you, this is much cleaner.
> > There are however some issues in this patch that prevent building on
> > any platform. Please ensure to give a local build test before
> > submitting a 3.
> >
> > First of all, this still does not contain the addition to
> > BaseTools/Source/Python/Common/buildoptions.py that I mentioned in
> > INVALID URI REMOVED
> > 3A__edk2.groups.io_g_devel_message_47036&d=DwIBAg&c=C5b8zRQO1mi
> > GmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=
> > YclXVT-
> > dumczX_RwFNv_GDdWAp1gvJXUN0KRfNaGEtw&s=Gp1kHhT9Z6PR93PmPN
> > ZD-_0h0rPDXLsODbhLWyQs8NA&e= - meaning that attempting
> > to build anything for RISCV64 gives an error.
>
> I thought you were saying to use ENV(GCC5_RISCV64_PREFIX) to point
> to build tool binaries, no?
That is unrelated.
I am talking about that the build command needs to be aware of the
existence of the RISCV64 architecture. The version of the build
command included in v2 cannot be used to build the tree. Just like I
commented on, and provided the patch for, for v1. In the message
linked to above.
How *have* you tested the build without a working build command?
> >
> > Other minor issues reviewed inline:
> >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > BaseTools/Conf/build_rule.template | 62 ++---
> > > BaseTools/Conf/tools_def.template | 64 ++++-
> > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
> > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> > > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> > > BaseTools/Source/C/GenFw/Elf64Convert.c | 260
> > ++++++++++++++++++++-
> > > BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> > > .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> > > BaseTools/Source/Python/Common/DataType.py | 7 +-
> > > 10 files changed, 659 insertions(+), 45 deletions(-)
> > >
> > > diff --git a/BaseTools/Conf/build_rule.template
> > b/BaseTools/Conf/build_rule.template
> > > index db06d3a..fab3926 100755
> > > --- a/BaseTools/Conf/build_rule.template
> > > +++ b/BaseTools/Conf/build_rule.template
> > > @@ -321,6 +314,21 @@
> > > "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> > >
> > >
> > > +[Static-Library-File.COMMON.RISCV64, Static-Library-
> > File.COMMON.RISCV32]
> > > + <InputFile>
> > > + *.lib
> > > +
> > > + <ExtraDependency>
> > > + $(MAKE_FILE)
> > > +
> > > + <OutputFile>
> > > + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> > > +
> > > + <Command.GCC>
> > > + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH)
> > @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
> >
> > This line looks to me like the only thing that is actually changed
> > here, and I am not convinced it is necessary.
> > "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
> > group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
> > $(DLINK2_FLAGS)
> >
> > On the ARM/AARCH64 side, we use gcc as the DLINK, and pass the
> > required flags through to the linker with -Wl. Please have a look and
> > try to rework at that end rather than fundamentally revamping the
> > basic build rules differently for RISCV than other architectures.
> >
> > Basically, please discard all changes to this file, apply the below
> > diff, and rework the flags to resolve the builds. (Basically, add a
> > bunch of -Wl,)
>
> I got build error when use -Wl with the specific version of RISC-V
> GCC toolchain (the old and workable one). I will revisit this when I
> investigate the issue caused by latest RISC-V build tool.
OK.
> > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > index 3d6319c..2aa09fd 100644
> > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > @@ -3,6 +3,7 @@ Elf64 convert solution
> > >
> > > Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> > > Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
> > > +Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise
> > Development LP. All rights reserved.<BR>
> > >
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > > #include "ElfConvert.h"
> > > #include "Elf64Convert.h"
> > >
> > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
> > > +#define RISCV_IMM_BITS 12
> > > +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
> > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > > +
> > > STATIC
> > > VOID
> > > ScanSections64 (
> > > @@ -153,8 +160,8 @@ InitializeElf64 (
> > > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or
> > ET_DYN");
> > > return FALSE;
> > > }
> > > - if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > EM_AARCH64))) {
> > > - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or
> > EM_AARCH64");
> > > + if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
> > > + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64
> > machine.");
> > > return FALSE;
> > > }
> > > if (mEhdr->e_version != EV_CURRENT) {
> > > @@ -481,6 +488,7 @@ ScanSections64 (
> > > switch (mEhdr->e_machine) {
> > > case EM_X86_64:
> > > case EM_AARCH64:
> > > + case EM_RISCV64:
> > > mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
> > > break;
> > > default:
> > > @@ -690,6 +698,11 @@ ScanSections64 (
> > > NtHdr->Pe32Plus.FileHeader.Machine =
> > EFI_IMAGE_MACHINE_AARCH64;
> > > NtHdr->Pe32Plus.OptionalHeader.Magic =
> > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > break;
> > > + case EM_RISCV64:
> > > + NtHdr->Pe32Plus.FileHeader.Machine =
> > EFI_IMAGE_MACHINE_RISCV64;
> > > + NtHdr->Pe32Plus.OptionalHeader.Magic =
> > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > + break;
> > > +
> > > default:
> > > VerboseMsg ("%s unknown e_machine type. Assume X64",
> > (UINTN)mEhdr->e_machine);
> > > NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
> > > @@ -769,6 +782,11 @@ WriteSections64 (
> > > Elf_Shdr *SecShdr;
> > > UINT32 SecOffset;
> > > BOOLEAN (*Filter)(Elf_Shdr *);
> > > + UINT32 Value;
> > > + UINT32 Value2;
> > > + UINT8 *Pass1Targ = NULL;
> > > + Elf_Shdr *Pass1Sym = NULL;
> > > + Elf64_Half Pass1SymSecIndex = 0;
> > > Elf64_Addr GOTEntryRva;
> > >
> > > //
> > > @@ -893,13 +911,14 @@ WriteSections64 (
> > > if (SymName == NULL) {
> > > SymName = (const UINT8 *)"<unknown>";
> > > }
> > > + if (mEhdr->e_machine != EM_RISCV64) {
> >
> > This needs a comment explaining why this does not apply to RISCV.
>
> >
> > > + Error (NULL, 0, 3000, "Invalid",
> > > + "%s: Bad definition for symbol '%s'@%#llx or unsupported
> > symbol type. "
> > > + "For example, absolute and undefined symbols are not
> > supported.",
> > > + mInImageName, SymName, Sym->st_value);
> > >
> > > - Error (NULL, 0, 3000, "Invalid",
> > > - "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol
> > type. "
> > > - "For example, absolute and undefined symbols are not
> > supported.",
> > > - mInImageName, SymName, Sym->st_value);
> > > -
> > > - exit(EXIT_FAILURE);
> > > + exit(EXIT_FAILURE);
> > > + }
> > > }
> > > SymShdr = GetShdrByIndex(Sym->st_shndx);
> > >
> > > @@ -1114,6 +1133,128 @@ WriteSections64 (
> > > default:
> > > Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported
> > ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned)
> > ELF_R_TYPE(Rel->r_info));
> > > }
> > > + } else if (mEhdr->e_machine == EM_RISCV64) {
> >
> > Yeah, this code block is just *waaaay* too big.
> > Please break it out into its own helper function.
>
> Leif, I am not going to address this issue this time. I just follow
> what other archs done in this function. I agree with you this
> function is way too long. I could create a task to refine this
> function once RISC-V part is reviewed and pushed to the mainstream.
I don't understand this logic.
Breaking this out into a helper function would take no more time than
you spent on typing the above response that you don't intend to do.
Yes, the code for the other architectures is also bad, and we should
revisit and fix it. But that doesn't mean we should keep making the
file worse.
I am already giving a pass on how even if you break this hunk out into
its own helper function, that one is itself way too long and needs to
be broken up. But at least if we move it out, we've compartmentalised
the problem.
Merging something bad in order to fix it later is never the answer.
(And not only because in 95% in cases, that later never happens.)
Best Regards,
Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-10-15 10:41 ` Leif Lindholm
@ 2019-10-15 10:59 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 10:59 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, October 15, 2019 6:42 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
>
> On Tue, Oct 15, 2019 at 04:26:12AM +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> >
> >
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > Of Abner Chang
> > > Sent: Tuesday, October 15, 2019 12:03 PM
> > > To: devel@edk2.groups.io; leif.lindholm@linaro.org
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > > Of Leif Lindholm
> > > > Sent: Friday, September 27, 2019 7:46 AM
> > > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > > <abner.chang@hpe.com>
> > > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29]
> > > > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> > > >
> > > > On Mon, Sep 23, 2019 at 08:31:36AM +0800, Abner Chang wrote:
> > > > > Support RISC-V image relocation.
> > > > >
> > > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > > ---
> > > > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
> > > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
> > > > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
> > > > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
> > > > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142
> > > > +++++++++++++++++++++
> > > > > 5 files changed, 152 insertions(+), 1 deletion(-) create mode
> > > > > 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
>
> > > > > diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > > b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > > new file mode 100644
> > > > > index 0000000..8eb37f9
> > > > > --- /dev/null
> > > > > +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > > > @@ -0,0 +1,142 @@
> > > > > +/** @file
> > > > > + PE/Coff loader for RISC-V PE image
> > > > > +
> > > > > + Copyright (c) 2016, Hewlett Packard Enterprise Development LP.
> > > > > +All rights reserved.<BR>
> > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
> > > > > +"BasePeCoffLibInternals.h"
> > > > > +#include <Library/BaseLib.h>
> > > > > +
> > > > > +//
> > > > > +// RISC-V definition.
> > > > > +//
> > > > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> > > > (1LL<<RISCV_IMM_BITS)
> > > > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > > >
> > > > This looked familiar, so I had a look.
> > > > This block is copied around - it exists in:
> > > > - BaseTools/Source/C/Common/PeCoffLoaderEx.c
> > > > - BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> > > >
> > > > This needs to be moved somewhere central and included elsewhere.
> > > > BaseTools and MdePkg unfortunately duplicate a lot of stuff, but
> > > > this still belongs in a common header file for either.
> > >
> > > I can consolidate that macro in two files under BaseTools, but not
> > > consolidating macro in files in both MdePkg and BaseTools. BaseTools
> > > and
> > > edk2 are two separate projects and could be built individually based
> > > on my understanding.
> > > I have no idea how to leverage one header file from both projects
> > > and I don't go that far to address it.
> >
> > Leif, seem there is no good place and the existing header file to put
> > this macro unless I create a new header file under
> > BaseTools/Source/C/Include. I would like to keep this duplicate macro
> > in both files rather than create an header file in which only define
> > this macro. Do you have good idea?
>
> There is never a good reason to duplicate code. You will always end up
> changing one and forgetting the other.
Sure.
>
> I see no problem with creating a header file which contains nothing else. But I
> also think it would be valid to put this into C/Common/PeCoffLib.h - and this
> file is already included by the affected .c files.
Hmm. Then put it into PeCoffLib. I am good with this if no one opposite.
>
> /
> Leif
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
2019-10-15 6:31 ` Abner Chang
@ 2019-10-15 11:00 ` Leif Lindholm
2019-10-15 11:03 ` Abner Chang
0 siblings, 1 reply; 108+ messages in thread
From: Leif Lindholm @ 2019-10-15 11:00 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io
On Tue, Oct 15, 2019 at 06:31:06AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, September 27, 2019 4:51 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29]
> > BaseTools/Scripts
> >
> > On Mon, Sep 23, 2019 at 08:31:51AM +0800, Abner Chang wrote:
> > > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > > GccBase.lds causes PE32 relocation error.
> > > This is the temporaty solution untill we find the root casue.
> >
> > I presume you mean that having a separate version for RISCV is temporary? I
> > am OK with this for now. However, the diff is not what I would expect. Can
> > you verify that the difference is only what you actually need?
>
> Yes. Hope I can remove this change after I figuring out the toolchain issue.
>
> > For example:
> >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > BaseTools/Scripts/GccBaseRiscV.lds | 66
> > > ++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 66 insertions(+)
> > > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> > >
> > > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > > b/BaseTools/Scripts/GccBaseRiscV.lds
> > > new file mode 100644
> > > index 0000000..7f9fae6
> > > --- /dev/null
> > > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > > @@ -0,0 +1,66 @@
> > > +/** @file
> > > +
> > > + Unified linker script for GCC based builds
> > > +
> > > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > > + Development LP. All rights reserved.<BR>
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +
> > > +SECTIONS {
> > > +
> > > + /*
> > > + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> > sequence of
> > > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> > differs
> > > + * between 32-bit and 64-bit builds). The actual start of the .text section
> > > + * will be rounded up based on its actual alignment.
> > > + */
> > > + . = PECOFF_HEADER_SIZE;
> > > +
> > > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > > + *(.rodata .rodata.* .gnu.linkonce.r.*)
> > > + *(.got .got.*)
> > > +
> > > + /*
> > > + * The contents of AutoGen.c files are constant from the POV of the
> > program,
> > > + * but most of its contents end up in .data or .bss by default since few of
> > > + * the variable definitions that get emitted are declared as CONST.
> > > + */
> >
> > The above comment block looks completely different - in GccBase.lds:
> > /*
> > * The contents of AutoGen.c files are mostly constant from the POV of
> > the
> > * program, but most of it ends up in .data or .bss by default since few of
> > * the variable definitions that get emitted are declared as CONST.
> > * Unfortunately, we cannot pull it into the .text section entirely, since
> > * patchable PCDs are also emitted here, but we can at least move all of
> > the
> > * emitted GUIDs here.
> > */
> >
> > > + *:AutoGen.obj(.data.g*Guid)
> > > + }
> > > +
> > > + /*
> > > + * The alignment of the .data section should be less than or equal to the
> > > + * alignment of the .text section. This ensures that the relative offset
> > > + * between these sections is the same in the ELF and the PE/COFF
> > versions of
> > > + * this binary.
> > > + */
> > > + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
> > {
> > > + *(.data .data.* .gnu.linkonce.d.*)
> > > + *(.bss .bss.*)
> > > + }
> > > +
> > > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > > + KEEP (*(.eh_frame))
> > > + }
> > > +
> > > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> >
> > The above line is, I believe, the only necessary change for your workaround?
>
> Yes. only this line is necessary. I guess I copied entire lds file from my old edk2 tree.
Yeah, that makes sense.
If you can provide an updated version based on the current common
.lds, I'm OK for that to go into the -staging branch.
/
Leif
> >
> > > + *(.rela .rela.*)
> > > + }
> > > +
> >
> > The original one as the following:
> > .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > KEEP (*(.hii))
> > }
> >
> > I do not think including this could be the cause of any issues.
> >
> > Also, GccBase.lds includes here:
> > /*
> > * Retain the GNU build id but in a non-allocatable section so GenFw
> > * does not copy it into the PE/COFF image.
> > */
> > .build-id (INFO) : { *(.note.gnu.build-id) }
> >
> > > + /DISCARD/ : {
> > > + *(.note.GNU-stack)
> > > + *(.gnu_debuglink)
> > > + *(.interp)
> > > + *(.dynsym)
> > > + *(.dynstr)
> > > + *(.dynamic)
> > > + *(.hash)
> >
> > In GccBase.lds:
> > *(.hash .gnu.hash)
> >
> > /
> > Leif
> >
> > > + *(.comment)
> > > + *(COMMON)
> > > + }
> > > +}
> > > --
> > > 2.7.4
> > >
> > >
> > >
> > >
> >
> >
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts
2019-10-15 11:00 ` Leif Lindholm
@ 2019-10-15 11:03 ` Abner Chang
0 siblings, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 11:03 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, October 15, 2019 7:00 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29]
> BaseTools/Scripts
>
> On Tue, Oct 15, 2019 at 06:31:06AM +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > Of Leif Lindholm
> > > Sent: Friday, September 27, 2019 4:51 AM
> > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > <abner.chang@hpe.com>
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29]
> > > BaseTools/Scripts
> > >
> > > On Mon, Sep 23, 2019 at 08:31:51AM +0800, Abner Chang wrote:
> > > > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > > > GccBase.lds causes PE32 relocation error.
> > > > This is the temporaty solution untill we find the root casue.
> > >
> > > I presume you mean that having a separate version for RISCV is
> > > temporary? I am OK with this for now. However, the diff is not what
> > > I would expect. Can you verify that the difference is only what you
> actually need?
> >
> > Yes. Hope I can remove this change after I figuring out the toolchain issue.
> >
> > > For example:
> > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > BaseTools/Scripts/GccBaseRiscV.lds | 66
> > > > ++++++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 66 insertions(+)
> > > > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> > > >
> > > > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > > > b/BaseTools/Scripts/GccBaseRiscV.lds
> > > > new file mode 100644
> > > > index 0000000..7f9fae6
> > > > --- /dev/null
> > > > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > > > @@ -0,0 +1,66 @@
> > > > +/** @file
> > > > +
> > > > + Unified linker script for GCC based builds
> > > > +
> > > > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > > > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > > > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > > > + Development LP. All rights reserved.<BR>
> > > > +
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > +
> > > > +**/
> > > > +
> > > > +SECTIONS {
> > > > +
> > > > + /*
> > > > + * The PE/COFF binary consists of DOS and PE/COFF headers, and
> > > > + a
> > > sequence of
> > > > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> > > differs
> > > > + * between 32-bit and 64-bit builds). The actual start of the .text
> section
> > > > + * will be rounded up based on its actual alignment.
> > > > + */
> > > > + . = PECOFF_HEADER_SIZE;
> > > > +
> > > > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > > > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > > > + *(.rodata .rodata.* .gnu.linkonce.r.*)
> > > > + *(.got .got.*)
> > > > +
> > > > + /*
> > > > + * The contents of AutoGen.c files are constant from the POV
> > > > + of the
> > > program,
> > > > + * but most of its contents end up in .data or .bss by default since
> few of
> > > > + * the variable definitions that get emitted are declared as CONST.
> > > > + */
> > >
> > > The above comment block looks completely different - in GccBase.lds:
> > > /*
> > > * The contents of AutoGen.c files are mostly constant from the
> > > POV of the
> > > * program, but most of it ends up in .data or .bss by default since few
> of
> > > * the variable definitions that get emitted are declared as CONST.
> > > * Unfortunately, we cannot pull it into the .text section entirely, since
> > > * patchable PCDs are also emitted here, but we can at least
> > > move all of the
> > > * emitted GUIDs here.
> > > */
> > >
> > > > + *:AutoGen.obj(.data.g*Guid)
> > > > + }
> > > > +
> > > > + /*
> > > > + * The alignment of the .data section should be less than or equal to
> the
> > > > + * alignment of the .text section. This ensures that the relative offset
> > > > + * between these sections is the same in the ELF and the
> > > > + PE/COFF
> > > versions of
> > > > + * this binary.
> > > > + */
> > > > + .data ALIGN(ALIGNOF(.text)) :
> ALIGN(CONSTANT(COMMONPAGESIZE))
> > > {
> > > > + *(.data .data.* .gnu.linkonce.d.*)
> > > > + *(.bss .bss.*)
> > > > + }
> > > > +
> > > > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > > > + KEEP (*(.eh_frame))
> > > > + }
> > > > +
> > > > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > >
> > > The above line is, I believe, the only necessary change for your
> workaround?
> >
> > Yes. only this line is necessary. I guess I copied entire lds file from my old
> edk2 tree.
>
> Yeah, that makes sense.
> If you can provide an updated version based on the current common .lds, I'm
> OK for that to go into the -staging branch.
It will be in the v3.
>
> /
> Leif
>
> > >
> > > > + *(.rela .rela.*)
> > > > + }
> > > > +
> > >
> > > The original one as the following:
> > > .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > > KEEP (*(.hii))
> > > }
> > >
> > > I do not think including this could be the cause of any issues.
> > >
> > > Also, GccBase.lds includes here:
> > > /*
> > > * Retain the GNU build id but in a non-allocatable section so GenFw
> > > * does not copy it into the PE/COFF image.
> > > */
> > > .build-id (INFO) : { *(.note.gnu.build-id) }
> > >
> > > > + /DISCARD/ : {
> > > > + *(.note.GNU-stack)
> > > > + *(.gnu_debuglink)
> > > > + *(.interp)
> > > > + *(.dynsym)
> > > > + *(.dynstr)
> > > > + *(.dynamic)
> > > > + *(.hash)
> > >
> > > In GccBase.lds:
> > > *(.hash .gnu.hash)
> > >
> > > /
> > > Leif
> > >
> > > > + *(.comment)
> > > > + *(COMMON)
> > > > + }
> > > > +}
> > > > --
> > > > 2.7.4
> > > >
> > > >
> > > >
> > > >
> > >
> > >
> >
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-10-15 10:56 ` Leif Lindholm
@ 2019-10-15 11:13 ` Abner Chang
2019-10-16 5:06 ` Abner Chang
1 sibling, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-15 11:13 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Tuesday, October 15, 2019 6:57 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> BaseTools: BaseTools changes for RISC-V platform.
>
> On Tue, Oct 15, 2019 at 06:18:29AM +0000, Abner Chang wrote:
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > Of Leif Lindholm
> > > Sent: Friday, September 27, 2019 6:10 AM
> > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > <abner.chang@hpe.com>
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> > > BaseTools: BaseTools changes for RISC-V platform.
> > >
> > > On Mon, Sep 23, 2019 at 08:31:50AM +0800, Abner Chang wrote:
> > > > BaseTools changes for building EDK2 RISC-V platform.
> > > > The changes made to build_rule.template is to avoid build errors
> > > > cause by GCC711RISCV tool chain.
> > >
> > > Thank you, this is much cleaner.
> > > There are however some issues in this patch that prevent building on
> > > any platform. Please ensure to give a local build test before
> > > submitting a 3.
> > >
> > > First of all, this still does not contain the addition to
> > > BaseTools/Source/Python/Common/buildoptions.py that I mentioned in
> > > INVALID URI REMOVED
> > >
> 3A__edk2.groups.io_g_devel_message_47036&d=DwIBAg&c=C5b8zRQO1mi
> > >
> GmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=
> > > YclXVT-
> > >
> dumczX_RwFNv_GDdWAp1gvJXUN0KRfNaGEtw&s=Gp1kHhT9Z6PR93PmPN
> > > ZD-_0h0rPDXLsODbhLWyQs8NA&e= - meaning that attempting to build
> > > anything for RISCV64 gives an error.
> >
> > I thought you were saying to use ENV(GCC5_RISCV64_PREFIX) to point to
> > build tool binaries, no?
>
> That is unrelated.
>
> I am talking about that the build command needs to be aware of the
> existence of the RISCV64 architecture. The version of the build command
> included in v2 cannot be used to build the tree. Just like I commented on,
> and provided the patch for, for v1. In the message linked to above.
>
> How *have* you tested the build without a working build command?
>
> > >
> > > Other minor issues reviewed inline:
> > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > BaseTools/Conf/build_rule.template | 62 ++---
> > > > BaseTools/Conf/tools_def.template | 64 ++++-
> > > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> > > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
> > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> > > > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> > > > BaseTools/Source/C/GenFw/Elf64Convert.c | 260
> > > ++++++++++++++++++++-
> > > > BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> > > > .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> > > > BaseTools/Source/Python/Common/DataType.py | 7 +-
> > > > 10 files changed, 659 insertions(+), 45 deletions(-)
> > > >
> > > > diff --git a/BaseTools/Conf/build_rule.template
> > > b/BaseTools/Conf/build_rule.template
> > > > index db06d3a..fab3926 100755
> > > > --- a/BaseTools/Conf/build_rule.template
> > > > +++ b/BaseTools/Conf/build_rule.template
> > > > @@ -321,6 +314,21 @@
> > > > "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> > > >
> > > >
> > > > +[Static-Library-File.COMMON.RISCV64, Static-Library-
> > > File.COMMON.RISCV32]
> > > > + <InputFile>
> > > > + *.lib
> > > > +
> > > > + <ExtraDependency>
> > > > + $(MAKE_FILE)
> > > > +
> > > > + <OutputFile>
> > > > + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> > > > +
> > > > + <Command.GCC>
> > > > + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group
> > > > + $(DLINK_SPATH)
> > > @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
> > >
> > > This line looks to me like the only thing that is actually changed
> > > here, and I am not convinced it is necessary.
> > > "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
> > > group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
> > > $(DLINK2_FLAGS)
> > >
> > > On the ARM/AARCH64 side, we use gcc as the DLINK, and pass the
> > > required flags through to the linker with -Wl. Please have a look
> > > and try to rework at that end rather than fundamentally revamping
> > > the basic build rules differently for RISCV than other architectures.
> > >
> > > Basically, please discard all changes to this file, apply the below
> > > diff, and rework the flags to resolve the builds. (Basically, add a
> > > bunch of -Wl,)
> >
> > I got build error when use -Wl with the specific version of RISC-V GCC
> > toolchain (the old and workable one). I will revisit this when I
> > investigate the issue caused by latest RISC-V build tool.
>
> OK.
>
> > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > index 3d6319c..2aa09fd 100644
> > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > @@ -3,6 +3,7 @@ Elf64 convert solution
> > > >
> > > > Copyright (c) 2010 - 2018, Intel Corporation. All rights
> > > > reserved.<BR> Portions copyright (c) 2013-2014, ARM Ltd. All
> > > > rights reserved.<BR>
> > > > +Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise
> > > Development LP. All rights reserved.<BR>
> > > >
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > #include "ElfConvert.h"
> > > > #include "Elf64Convert.h"
> > > >
> > > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> (1LL<<RISCV_IMM_BITS)
> > > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > > > +
> > > > STATIC
> > > > VOID
> > > > ScanSections64 (
> > > > @@ -153,8 +160,8 @@ InitializeElf64 (
> > > > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC
> > > > or
> > > ET_DYN");
> > > > return FALSE;
> > > > }
> > > > - if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > > EM_AARCH64))) {
> > > > - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not
> EM_X86_64 or
> > > EM_AARCH64");
> > > > + if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > > EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
> > > > + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not
> > > > + Elf64
> > > machine.");
> > > > return FALSE;
> > > > }
> > > > if (mEhdr->e_version != EV_CURRENT) { @@ -481,6 +488,7 @@
> > > > ScanSections64 (
> > > > switch (mEhdr->e_machine) {
> > > > case EM_X86_64:
> > > > case EM_AARCH64:
> > > > + case EM_RISCV64:
> > > > mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
> > > > break;
> > > > default:
> > > > @@ -690,6 +698,11 @@ ScanSections64 (
> > > > NtHdr->Pe32Plus.FileHeader.Machine =
> > > EFI_IMAGE_MACHINE_AARCH64;
> > > > NtHdr->Pe32Plus.OptionalHeader.Magic =
> > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > > break;
> > > > + case EM_RISCV64:
> > > > + NtHdr->Pe32Plus.FileHeader.Machine =
> > > EFI_IMAGE_MACHINE_RISCV64;
> > > > + NtHdr->Pe32Plus.OptionalHeader.Magic =
> > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > > + break;
> > > > +
> > > > default:
> > > > VerboseMsg ("%s unknown e_machine type. Assume X64",
> > > (UINTN)mEhdr->e_machine);
> > > > NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
> > > > @@ -769,6 +782,11 @@ WriteSections64 (
> > > > Elf_Shdr *SecShdr;
> > > > UINT32 SecOffset;
> > > > BOOLEAN (*Filter)(Elf_Shdr *);
> > > > + UINT32 Value;
> > > > + UINT32 Value2;
> > > > + UINT8 *Pass1Targ = NULL;
> > > > + Elf_Shdr *Pass1Sym = NULL;
> > > > + Elf64_Half Pass1SymSecIndex = 0;
> > > > Elf64_Addr GOTEntryRva;
> > > >
> > > > //
> > > > @@ -893,13 +911,14 @@ WriteSections64 (
> > > > if (SymName == NULL) {
> > > > SymName = (const UINT8 *)"<unknown>";
> > > > }
> > > > + if (mEhdr->e_machine != EM_RISCV64) {
> > >
> > > This needs a comment explaining why this does not apply to RISCV.
> >
> > >
> > > > + Error (NULL, 0, 3000, "Invalid",
> > > > + "%s: Bad definition for symbol '%s'@%#llx or
> > > > + unsupported
> > > symbol type. "
> > > > + "For example, absolute and undefined symbols
> > > > + are not
> > > supported.",
> > > > + mInImageName, SymName, Sym->st_value);
> > > >
> > > > - Error (NULL, 0, 3000, "Invalid",
> > > > - "%s: Bad definition for symbol '%s'@%#llx or unsupported
> symbol
> > > type. "
> > > > - "For example, absolute and undefined symbols are not
> > > supported.",
> > > > - mInImageName, SymName, Sym->st_value);
> > > > -
> > > > - exit(EXIT_FAILURE);
> > > > + exit(EXIT_FAILURE);
> > > > + }
> > > > }
> > > > SymShdr = GetShdrByIndex(Sym->st_shndx);
> > > >
> > > > @@ -1114,6 +1133,128 @@ WriteSections64 (
> > > > default:
> > > > Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > %s unsupported
> > > ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned)
> > > ELF_R_TYPE(Rel->r_info));
> > > > }
> > > > + } else if (mEhdr->e_machine == EM_RISCV64) {
> > >
> > > Yeah, this code block is just *waaaay* too big.
> > > Please break it out into its own helper function.
> >
> > Leif, I am not going to address this issue this time. I just follow
> > what other archs done in this function. I agree with you this
> > function is way too long. I could create a task to refine this
> > function once RISC-V part is reviewed and pushed to the mainstream.
>
> I don't understand this logic.
> Breaking this out into a helper function would take no more time than you
> spent on typing the above response that you don't intend to do.
Come on man~
>
> Yes, the code for the other architectures is also bad, and we should revisit
> and fix it. But that doesn't mean we should keep making the file worse.
>
> I am already giving a pass on how even if you break this hunk out into its own
> helper function, that one is itself way too long and needs to be broken up.
> But at least if we move it out, we've compartmentalised the problem.
>
> Merging something bad in order to fix it later is never the answer.
> (And not only because in 95% in cases, that later never happens.)
I totally understand what is the best engineer practice...
Yes. I know you won't let this code to get into staging if I don't fix this. You win~ :)
>
> Best Regards,
>
> Leif
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform.
2019-10-15 10:56 ` Leif Lindholm
2019-10-15 11:13 ` Abner Chang
@ 2019-10-16 5:06 ` Abner Chang
1 sibling, 0 replies; 108+ messages in thread
From: Abner Chang @ 2019-10-16 5:06 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Tuesday, October 15, 2019 6:57 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> BaseTools: BaseTools changes for RISC-V platform.
>
> On Tue, Oct 15, 2019 at 06:18:29AM +0000, Abner Chang wrote:
> > > -----Original Message-----
> > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf
> > > Of Leif Lindholm
> > > Sent: Friday, September 27, 2019 6:10 AM
> > > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > > <abner.chang@hpe.com>
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29]
> > > BaseTools: BaseTools changes for RISC-V platform.
> > >
> > > On Mon, Sep 23, 2019 at 08:31:50AM +0800, Abner Chang wrote:
> > > > BaseTools changes for building EDK2 RISC-V platform.
> > > > The changes made to build_rule.template is to avoid build errors
> > > > cause by GCC711RISCV tool chain.
> > >
> > > Thank you, this is much cleaner.
> > > There are however some issues in this patch that prevent building on
> > > any platform. Please ensure to give a local build test before
> > > submitting a 3.
> > >
> > > First of all, this still does not contain the addition to
> > > BaseTools/Source/Python/Common/buildoptions.py that I mentioned in
> > > INVALID URI REMOVED
> > >
> 3A__edk2.groups.io_g_devel_message_47036&d=DwIBAg&c=C5b8zRQO1mi
> > >
> GmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=
> > > YclXVT-
> > >
> dumczX_RwFNv_GDdWAp1gvJXUN0KRfNaGEtw&s=Gp1kHhT9Z6PR93PmPN
> > > ZD-_0h0rPDXLsODbhLWyQs8NA&e= - meaning that attempting to build
> > > anything for RISCV64 gives an error.
> >
> > I thought you were saying to use ENV(GCC5_RISCV64_PREFIX) to point to
> > build tool binaries, no?
>
> That is unrelated.
>
> I am talking about that the build command needs to be aware of the
> existence of the RISCV64 architecture. The version of the build command
> included in v2 cannot be used to build the tree. Just like I commented on,
> and provided the patch for, for v1. In the message linked to above.
>
> How *have* you tested the build without a working build command?
Ah I see.
You were saying -a in build command line. That was fixed in v3.
>
> > >
> > > Other minor issues reviewed inline:
> > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > BaseTools/Conf/build_rule.template | 62 ++---
> > > > BaseTools/Conf/tools_def.template | 64 ++++-
> > > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> > > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++
> > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> > > > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> > > > BaseTools/Source/C/GenFw/Elf64Convert.c | 260
> > > ++++++++++++++++++++-
> > > > BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> > > > .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> > > > BaseTools/Source/Python/Common/DataType.py | 7 +-
> > > > 10 files changed, 659 insertions(+), 45 deletions(-)
> > > >
> > > > diff --git a/BaseTools/Conf/build_rule.template
> > > b/BaseTools/Conf/build_rule.template
> > > > index db06d3a..fab3926 100755
> > > > --- a/BaseTools/Conf/build_rule.template
> > > > +++ b/BaseTools/Conf/build_rule.template
> > > > @@ -321,6 +314,21 @@
> > > > "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> > > >
> > > >
> > > > +[Static-Library-File.COMMON.RISCV64, Static-Library-
> > > File.COMMON.RISCV32]
> > > > + <InputFile>
> > > > + *.lib
> > > > +
> > > > + <ExtraDependency>
> > > > + $(MAKE_FILE)
> > > > +
> > > > + <OutputFile>
> > > > + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> > > > +
> > > > + <Command.GCC>
> > > > + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group
> > > > + $(DLINK_SPATH)
> > > @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
> > >
> > > This line looks to me like the only thing that is actually changed
> > > here, and I am not convinced it is necessary.
> > > "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
> > > group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
> > > $(DLINK2_FLAGS)
> > >
> > > On the ARM/AARCH64 side, we use gcc as the DLINK, and pass the
> > > required flags through to the linker with -Wl. Please have a look
> > > and try to rework at that end rather than fundamentally revamping
> > > the basic build rules differently for RISCV than other architectures.
> > >
> > > Basically, please discard all changes to this file, apply the below
> > > diff, and rework the flags to resolve the builds. (Basically, add a
> > > bunch of -Wl,)
> >
> > I got build error when use -Wl with the specific version of RISC-V GCC
> > toolchain (the old and workable one). I will revisit this when I
> > investigate the issue caused by latest RISC-V build tool.
>
> OK.
>
> > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > index 3d6319c..2aa09fd 100644
> > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > @@ -3,6 +3,7 @@ Elf64 convert solution
> > > >
> > > > Copyright (c) 2010 - 2018, Intel Corporation. All rights
> > > > reserved.<BR> Portions copyright (c) 2013-2014, ARM Ltd. All
> > > > rights reserved.<BR>
> > > > +Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise
> > > Development LP. All rights reserved.<BR>
> > > >
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > #include "ElfConvert.h"
> > > > #include "Elf64Convert.h"
> > > >
> > > > +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) #define
> > > > +RISCV_IMM_BITS 12 #define RISCV_IMM_REACH
> (1LL<<RISCV_IMM_BITS)
> > > > +#define RISCV_CONST_HIGH_PART(VALUE) \
> > > > + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
> > > > +
> > > > STATIC
> > > > VOID
> > > > ScanSections64 (
> > > > @@ -153,8 +160,8 @@ InitializeElf64 (
> > > > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC
> > > > or
> > > ET_DYN");
> > > > return FALSE;
> > > > }
> > > > - if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > > EM_AARCH64))) {
> > > > - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not
> EM_X86_64 or
> > > EM_AARCH64");
> > > > + if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine ==
> > > EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
> > > > + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not
> > > > + Elf64
> > > machine.");
> > > > return FALSE;
> > > > }
> > > > if (mEhdr->e_version != EV_CURRENT) { @@ -481,6 +488,7 @@
> > > > ScanSections64 (
> > > > switch (mEhdr->e_machine) {
> > > > case EM_X86_64:
> > > > case EM_AARCH64:
> > > > + case EM_RISCV64:
> > > > mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
> > > > break;
> > > > default:
> > > > @@ -690,6 +698,11 @@ ScanSections64 (
> > > > NtHdr->Pe32Plus.FileHeader.Machine =
> > > EFI_IMAGE_MACHINE_AARCH64;
> > > > NtHdr->Pe32Plus.OptionalHeader.Magic =
> > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > > break;
> > > > + case EM_RISCV64:
> > > > + NtHdr->Pe32Plus.FileHeader.Machine =
> > > EFI_IMAGE_MACHINE_RISCV64;
> > > > + NtHdr->Pe32Plus.OptionalHeader.Magic =
> > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> > > > + break;
> > > > +
> > > > default:
> > > > VerboseMsg ("%s unknown e_machine type. Assume X64",
> > > (UINTN)mEhdr->e_machine);
> > > > NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
> > > > @@ -769,6 +782,11 @@ WriteSections64 (
> > > > Elf_Shdr *SecShdr;
> > > > UINT32 SecOffset;
> > > > BOOLEAN (*Filter)(Elf_Shdr *);
> > > > + UINT32 Value;
> > > > + UINT32 Value2;
> > > > + UINT8 *Pass1Targ = NULL;
> > > > + Elf_Shdr *Pass1Sym = NULL;
> > > > + Elf64_Half Pass1SymSecIndex = 0;
> > > > Elf64_Addr GOTEntryRva;
> > > >
> > > > //
> > > > @@ -893,13 +911,14 @@ WriteSections64 (
> > > > if (SymName == NULL) {
> > > > SymName = (const UINT8 *)"<unknown>";
> > > > }
> > > > + if (mEhdr->e_machine != EM_RISCV64) {
> > >
> > > This needs a comment explaining why this does not apply to RISCV.
> >
> > >
> > > > + Error (NULL, 0, 3000, "Invalid",
> > > > + "%s: Bad definition for symbol '%s'@%#llx or
> > > > + unsupported
> > > symbol type. "
> > > > + "For example, absolute and undefined symbols
> > > > + are not
> > > supported.",
> > > > + mInImageName, SymName, Sym->st_value);
> > > >
> > > > - Error (NULL, 0, 3000, "Invalid",
> > > > - "%s: Bad definition for symbol '%s'@%#llx or unsupported
> symbol
> > > type. "
> > > > - "For example, absolute and undefined symbols are not
> > > supported.",
> > > > - mInImageName, SymName, Sym->st_value);
> > > > -
> > > > - exit(EXIT_FAILURE);
> > > > + exit(EXIT_FAILURE);
> > > > + }
> > > > }
> > > > SymShdr = GetShdrByIndex(Sym->st_shndx);
> > > >
> > > > @@ -1114,6 +1133,128 @@ WriteSections64 (
> > > > default:
> > > > Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > %s unsupported
> > > ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned)
> > > ELF_R_TYPE(Rel->r_info));
> > > > }
> > > > + } else if (mEhdr->e_machine == EM_RISCV64) {
> > >
> > > Yeah, this code block is just *waaaay* too big.
> > > Please break it out into its own helper function.
> >
> > Leif, I am not going to address this issue this time. I just follow
> > what other archs done in this function. I agree with you this
> > function is way too long. I could create a task to refine this
> > function once RISC-V part is reviewed and pushed to the mainstream.
>
> I don't understand this logic.
> Breaking this out into a helper function would take no more time than you
> spent on typing the above response that you don't intend to do.
>
> Yes, the code for the other architectures is also bad, and we should revisit
> and fix it. But that doesn't mean we should keep making the file worse.
>
> I am already giving a pass on how even if you break this hunk out into its own
> helper function, that one is itself way too long and needs to be broken up.
> But at least if we move it out, we've compartmentalised the problem.
>
> Merging something bad in order to fix it later is never the answer.
> (And not only because in 95% in cases, that later never happens.)
>
> Best Regards,
>
> Leif
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread
end of thread, other threads:[~2019-10-16 5:06 UTC | newest]
Thread overview: 108+ messages (download: mbox.gz follow: Atom feed
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2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
2019-09-26 22:26 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-26 22:29 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-09-26 22:41 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-09-26 22:44 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
2019-09-26 22:45 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-09-26 22:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-26 22:56 ` [edk2-devel] " Leif Lindholm
2019-10-14 16:47 ` Abner Chang
2019-10-14 18:23 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-01 8:44 ` [edk2-devel] " Philippe Mathieu-Daudé
2019-09-23 0:31 ` Abner Chang
2019-09-26 23:30 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-26 23:39 ` [edk2-devel] " Leif Lindholm
2019-10-01 8:49 ` Philippe Mathieu-Daudé
2019-10-01 9:07 ` Leif Lindholm
2019-10-02 1:30 ` Abner Chang
2019-10-02 9:13 ` Leif Lindholm
2019-10-02 16:14 ` Abner Chang
2019-10-02 16:27 ` Andrew Fish
2019-10-02 16:35 ` Leif Lindholm
2019-10-03 0:52 ` Abner Chang
2019-10-03 8:38 ` Leif Lindholm
2019-10-03 11:34 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-09-26 23:46 ` [edk2-devel] " Leif Lindholm
2019-10-15 4:02 ` Abner Chang
2019-10-15 10:31 ` Leif Lindholm
2019-10-15 10:56 ` Abner Chang
[not found] ` <15CDB6324F411B37.30896@groups.io>
2019-10-15 4:26 ` Abner Chang
2019-10-15 10:41 ` Leif Lindholm
2019-10-15 10:59 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-26 23:47 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-27 0:19 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-09-30 18:31 ` [edk2-devel] " Leif Lindholm
2019-10-15 2:32 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-09-30 19:15 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-09-30 19:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-09-30 20:03 ` [edk2-devel] " Leif Lindholm
2019-10-15 1:21 ` Abner Chang
2019-10-15 8:35 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
2019-09-30 20:15 ` [edk2-devel] " Leif Lindholm
2019-09-30 20:44 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-09-30 20:31 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-09-30 20:54 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-09-30 20:56 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-30 21:11 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-26 22:09 ` [edk2-devel] " Leif Lindholm
2019-10-15 6:18 ` Abner Chang
2019-10-15 10:56 ` Leif Lindholm
2019-10-15 11:13 ` Abner Chang
2019-10-16 5:06 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 20:50 ` [edk2-devel] " Leif Lindholm
2019-10-15 6:31 ` Abner Chang
2019-10-15 11:00 ` Leif Lindholm
2019-10-15 11:03 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-09-30 22:39 ` [edk2-devel] " Leif Lindholm
2019-10-14 11:27 ` Abner Chang
2019-10-14 11:56 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
2019-09-26 22:24 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
2019-09-30 22:48 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
2019-09-30 22:50 ` [edk2-devel] " Leif Lindholm
[not found] ` <15C6EB9824DD2A88.29693@groups.io>
2019-09-24 1:52 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
[not found] ` <15C6EB994C26E5C4.2053@groups.io>
2019-09-24 1:52 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
[not found] ` <15C6EB9950232DB5.29693@groups.io>
2019-09-24 1:53 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
[not found] ` <15C6EB9A049FF8A4.24160@groups.io>
2019-09-24 1:54 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
[not found] ` <15C6EB9B3E887BEB.29693@groups.io>
2019-09-24 1:55 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
[not found] ` <15C6EB9A40C408A0.24160@groups.io>
2019-09-24 1:56 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
[not found] ` <15C6EB9B872A5B83.24160@groups.io>
2019-09-24 1:57 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
[not found] ` <15C6EB99CBC780B5.2053@groups.io>
2019-09-24 1:57 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
[not found] ` <15C6EB9A9BD83853.2053@groups.io>
2019-09-24 1:58 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
[not found] ` <15C6EB9AEB7BB057.24160@groups.io>
2019-09-24 1:58 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
[not found] ` <15C6EB99608359A3.24160@groups.io>
2019-09-24 1:59 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
[not found] ` <15C6EB9D6C0EC3B0.29693@groups.io>
2019-09-24 2:00 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
[not found] ` <15C6EB98AD6CCCEB.24160@groups.io>
2019-09-24 2:01 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
[not found] ` <15C6EB9F04387439.29693@groups.io>
2019-09-24 2:02 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 22:22 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Leif Lindholm
2019-10-15 6:39 ` Abner Chang
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